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At least 163 records · Page 9

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope integrators. They are capable of working from room to cryogenic temperatures, down to 84 K. The present iteration of the ASIC has been fabricated including several design updates and the addition of an on-chip voltage reference, resulting in improved performance. This work presents the main vulnerabilities solved, the changes carried out, and the resulting performance benefits. Measurements with a skipper-CCD and the ASIC at 140 K showed that the single-electron resolution can be reached by averaging the measured charge in the analog domain using the analog pile-up technique with a readout noise as low as 0.11 erms of equivalent charge for 1200 samples. The channel-to-channel crosstalk was also characterized showing values better than -62 dB.

Alcalde Bessia, Fabricio↗

A virtual Frisch-grid geometry-based CZT gamma detector for in-field radioisotope identification

Here, we present a Virtual Frisch-Grid geometry-based CZT gamma detector developed for identifying different radioisotopes over an energy range from a few keV up to 2 MeV, and useful for efficient characterization of CZT crystals. The detector is built with a 3 x 3 matrix of CZT crystals, each measuring approximately 6 mm x 6 mm x 15 mm. The charge generated within the sensor’s active volume is read out via an anode connected directly to the AVG3_Dev integrated circuit. A current signal induced by charge drift is collected on side pads of the crystals, enabling reconstruction of a 3D interaction position. This paper discusses the design, development, and performance of the standalone, mobile detector system, which integrates the AVG3_Dev readout IC developed at Brookhaven National Laboratory, a high-speed FPGA-based with per-channel digital signal processing, and embedded system capabilities. The device is compact, battery-powered, and supports wireless data streaming, making it suitable for field operations for radioisotope identification.

47 OTHER INSTRUMENTATION↗

Design of digital acquisition for beam current monitor

As a part of the Proton Improvement Plan – II (PIP-II) at Fermilab, instrumentation systems are being modernized to take advantage of the higher speeds and ease of use offered by standardized embedded systems like MicroTCA. A rear-transition module (RTM) is being designed to interface with said embedded systems. In each of the four identical channels on the RTM, the differential signal from an alternating-current current transformer (ACCT) transimpedance amplifier will again be amplified by a differential operation-amplifier, then filtered by a low-pass topology. The conditioned signal is then digitized at a maximum of 10MS/s by an analog to digital converter (ADC) integrated circuit. After digitization, the ADC passes the data to an off the shelf AdvancedMC (AMC) Xilinx FPGA module using low voltage differential signals. This paper will describe the simulation of analog circuitry for signal conditioning, simulation of digital signal integrity based on physical design as well as verification of design characteristics critical to signal integrity. This work aims to create a methodology that can be applied to future RTMs requiring application of high-speed digital design principles.

White, R.Turner [Fermilab]↗

Design of Digital Acquisition for Beam Current Monitor

As a part of the Proton Improvement Plan II (PIP-II) at Fermilab, instrumentation systems are being modernized to take advantage of the higher speeds and ease of use offered by standardized embedded systems like MicroTCA. A rear-transition module (RTM) is being designed to interface with said embedded systems. In each of the four identical channels on the RTM, the differential signal from an alternating-current current transformer (ACCT) transimpedance amplifier will again be amplified by a differential operation-amplifier, then filtered by a low-pass topology. The conditioned signal is then digitized at a maximum of 10MS/s by an analog to digital converter (ADC) integrated circuit. After digitization, the ADC passes the data to an off the shelf AdvancedMC (AMC) Xilinx FPGA module using low voltage differential signals. This paper will describe the simulation of analog circuitry for signal conditioning, simulation of digital signal integrity based on physical design as well as verification of design characteristics critical to signal integrity. This work aims to create a methodology that can be applied to future RTMs requiring application of high-speed digital design principles.

White, Turner [Fermilab] (ORCID:0009000348159256)↗

A novel approach to interface high-Q Fabry–Pérot resonators with photonic circuits

The unique benefits of Fabry–Pérot resonators as frequency-stable reference cavities and as an efficient interface between atoms and photons make them an indispensable resource for emerging photonic technologies. To bring these performance benefits to next-generation communications, computation, and time-keeping systems, it will be necessary to develop strategies to integrate compact Fabry–Pérot resonators with photonic integrated circuits. In this paper, we demonstrate a novel reflection cancellation circuit that utilizes a numerically optimized multi-port polarization-splitting grating coupler to efficiently interface high-finesse Fabry–Pérot resonators with a silicon photonic circuit. This circuit interface produces a spatial separation of the incident and reflected waves, as required for on-chip Pound–Drever–Hall frequency locking, while also suppressing unwanted back reflections from the Fabry–Pérot resonator. Using inverse design principles, we design and fabricate a polarization-splitting grating coupler that achieves 55% coupling efficiency. This design realizes an insertion loss of 5.8 dB for the circuit interface and more than 9 dB of back reflection suppression, and we demonstrate the versatility of this system by using it to interface several reflective off-chip devices.

Optics↗

Programmable photonic integrated meshes for modular generation of optical entanglement links

Abstract Large-scale generation of quantum entanglement between individually controllable qubits is at the core of quantum computing, communications, and sensing. Modular architectures of remotely-connected quantum technologies have been proposed for a variety of physical qubits, with demonstrations reported in atomic and all-photonic systems. However, an open challenge in these architectures lies in constructing high-speed and high-fidelity reconfigurable photonic networks for optically-heralded entanglement among target qubits. Here we introduce a programmable photonic integrated circuit (PIC), realized in a piezo-actuated silicon nitride (SiN)-in-oxide CMOS-compatible process, that implements an N × N Mach–Zehnder mesh (MZM) capable of high-speed execution of linear optical transformations. The visible-spectrum photonic integrated mesh is programmed to generate optical connectivity on up to N = 8 inputs for a range of optically-heralded entanglement protocols. In particular, we experimentally demonstrated optical connections between 16 independent pairwise mode couplings through the MZM, with optical transformation fidelities averaging 0.991 ± 0.0063. The PIC’s reconfigurable optical connectivity suffices for the production of 8-qubit resource states as building blocks of larger topological cluster states for quantum computing. Our programmable PIC platform enables the fast and scalable optical switching technology necessary for network-based quantum information processors.

47 OTHER INSTRUMENTATION↗

Integrated quantum optical phase sensor in thin film lithium niobate

Abstract The quantum noise of light, attributed to the random arrival time of photons from a coherent light source, fundamentally limits optical phase sensors. An engineered source of squeezed states suppresses this noise and allows phase detection sensitivity beyond the quantum noise limit (QNL). We need ways to use quantum light within deployable quantum sensors. Here we present a photonic integrated circuit in thin-film lithium niobate that meets these requirements. We use the second-order nonlinearity to produce a squeezed state at the same frequency as the pump light and realize circuit control and sensing with electro-optics. Using 26.2 milliwatts of optical power, we measure (2.7 ± 0.2)% squeezing and apply it to increase the signal-to-noise ratio of phase measurement. We anticipate that photonic systems like this, which operate with low power and integrate all of the needed functionality on a single die, will open new opportunities for quantum optical sensing.

47 OTHER INSTRUMENTATION↗

Millimeter-Wave Imaging Technology Development for Real-Time 2D and 3D Fusion Plasma Diagnostics

Including a one year No-Cost Extension, The University of California, Davis has been funded since 2020 to advance innovative millimeter-wave diagnostics for fusion plasma research. This work includes: (1) Developing and applying cutting-edge System-on-Chip millimeter wave Integrated Circuit (IC) technology for Electron Cyclotron Emission Imaging (ECEI) and Microwave Imaging Reflectometry (MIR) on the DIII-D tokamak and the NSTX-U spherical tokamak. (2) Development of radiation-hardened millimeter-wave chip for diagnostics in harsh environments, utilizing wide bandgap Gallium Nitride (GaN) semiconductors. (3) Integrating forward-modeling synthetic diagnostics to enable advanced, real-time plasma prediction and feedback control. Originally planned as a three-year program (2020–2023), the project was granted a one-year no-cost extension, extending its duration through the end of 2024.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗

Hybrid integrated photonic platforms: opinion

While photonic integration has made remarkable progress in recent years, there is no one integrated photonic platform that offers all desired functionalities and manufacturability on the same platform. GaAs and InP-based optoelectronic integrated circuits (OEICs) were very popular in the past decades; however, silicon photonics has recently emerged as a preferred platform due to its high-density and high-yield manufacturability leveraging the CMOS ecosystem, although it lacks optical gain, the Pockels effect, and other characteristics. On the other hand, hybrid photonic integration adds new and diverse functionalities to the host materials like silicon. This opinion paper investigates hybrid integrated photonic platforms, and discusses the new functionalities added to the silicon CMOS photonic platform.

42 ENGINEERING↗

Reconfigurable quantum phononic circuits via piezo-acoustomechanical interactions

Abstract We show that piezoelectric strain actuation of acoustomechanical interactions can produce large phase velocity changes in an existing quantum phononic platform: aluminum nitride on suspended silicon. Using finite element analysis, we demonstrate a piezo-acoustomechanical phase shifter waveguide capable of producing ± π phase shifts for GHz frequency phonons in 10s of μm with 10s of volts applied. Then, using the phase shifter as a building block, we demonstrate several phononic integrated circuit elements useful for quantum information processing. In particular, we show how to construct programmable multi-mode interferometers for linear phononic processing and a dynamically reconfigurable phononic memory that can switch between an ultra-long-lifetime state and a state strongly coupled to its bus waveguide. From the master equation for the full open quantum system of the reconfigurable phononic memory, we show that it is possible to perform read and write operations with over 90% quantum state transfer fidelity for an exponentially decaying pulse.

Taylor, Jeffrey C. (ORCID:0000000215982436)↗

Studies in pulse shape discrimination for an optimized ASIC design

The continued advancements of Silicon Photomultipliers (SiPMs) have made them viable photosensors for low recoil energy Pulse Shape Discrimination (PSD) between fast neutron and gamma interactions when coupled to an appropriate scintillator. At the same time, the large number of channels in a typical array calls for the development of low-cost and low-power electronics. A custom integrated circuit (ASIC) is an ideal solution for this purpose. To assess the requirements for such an ASIC, studies were performed using two scintillators, Stilbene and EJ-276, coupled to a 6 x 6 mm SiPM from Onsemi. We demonstrate that both scintillators are viable for performing PSD for interaction energies from 100 keV to several MeV while optimizing the integration periods used in the PSD metric. These measurements inform the design parameters of the ASIC under development.

Si-PMTs↗

Cryogenic-Refined MOSFET Modeling for Oscillator, Frequency Divider, and Amplifier Designs Below 4 K

Capturing device characteristic changes at cryogenic temperatures is crucial for cryo-CMOS circuit designs. In this work, we present an isothermal cryogenic-refined modeling approach for CMOS transistors that is simple, low overhead, and easy to implement while offering the required accuracy for predicting circuit performance at the designated temperatures. Guided by die-level measurement data and circuit design principles, the model introduces corrections to only five critical parameters: threshold voltage, carrier mobility, elevated low-frequency flicker noise, dominant high-frequency shot noise, and subthreshold swing (SS). These refinements are implemented around the foundry-provided SPICE model, which is typically validated only down to about 200 K. With these adjustments, the proposed cryogenic-refined model achieves less than 5% error in both large-signal metrics (I–V characteristics) and small-signal parameters (e.g., transconductance) when compared with device measurements at deep-cryogenic temperatures. The methodology is validated in two advanced technologies: TSMC 40-nm CMOS and GlobalFoundries (GF) 45-nm RF-SOI. We further demonstrate its applicability in three representative RF circuits: a 30-GHz LC oscillator, a high-speed current-mode-logic (CML) frequency divider (FD), and a subthreshold Gb/s amplifier, all showing close agreement between simulated predictions and measurements performed at 4 and 2.5 K. Finally, we believe that the proposed approach is implementation-friendly and can significantly accelerate the development of cryo-CMOS integrated circuits.

circuit modeling↗

Compiling Quantum Circuits for Dynamically Field-Programmable Neutral Atoms Array Processors

Dynamically field-programmable qubit arrays (DPQA) have recently emerged as a promising platform for quantum information processing. In DPQA, atomic qubits are selectively loaded into arrays of optical traps that can be reconfigured during the computation itself. Leveraging qubit transport and parallel, entangling quantum operations, different pairs of qubits, even those initially far away, can be entangled at different stages of the quantum program execution. Such reconfigurability and non-local connectivity present new challenges for compilation, especially in the layout synthesis step which places and routes the qubits and schedules the gates. In this paper, we consider a DPQA architecture that contains multiple arrays and supports 2D array movements, representing cutting-edge experimental platforms. Within this architecture, we discretize the state space and formulate layout synthesis as a satisfiability modulo theories problem, which can be solved by existing solvers optimally in terms of circuit depth. For a set of benchmark circuits generated by random graphs with complex connectivities, our compiler OLSQ-DPQA reduces the number of two-qubit entangling gates on small problem instances by 1.7x compared to optimal compilation results on a fixed planar architecture. To further improve scalability and practicality of the method, we introduce a greedy heuristic inspired by the iterative peeling approach in classical integrated circuit routing. Using a hybrid approach that combined the greedy and optimal methods, we demonstrate that our DPQA-based compiled circuits feature reduced scaling overhead compared to a grid fixed architecture, resulting in 5.1X less two-qubit gates for 90 qubit quantum circuits. These methods enable programmable, complex quantum circuits with neutral atom quantum computers, as well as informing both future compilers and future hardware choices.

Physics↗

A MEMS Gyroscope for Reliable Long Duration Measurement While Drilling at 300°C

The 300°C Microelectromechanical system (MEMS) gyroscope project aims to contribute to DOE’s goal of increased geothermal drilling efficiency by 2025 through the development of a 300°C MEMS gyroscope for Measurement While Drilling (MWD). At the conclusion of the 2-year project, the team will develop a 300°C capable MEMS gyroscope containing GE’s patented Multi-Ring Gyroscope Transducer (MRGT) design, custom Silicon-On-Insulator (SOI) based frontend and feedback control electronics, and with demonstrated functionality and lifetime beyond 1000 hours. The project is divided into two budget periods with Go/No-Go decision at the end of the first budget period. The goal for the first budget period is to establish the feasibility of the MRGT and electronics design for meeting the 300°C performance requirements. The goal for the second budget period is to integrate the MRGT with the SOI-based application specific integrated circuit (ASIC) and demonstrate capability to operate at 300°C for 1000 hours. In Budget Period 1 we met the phase 1 goal. We successfully validated the combined MRG, electronics and packaging capability entitlement to achieving 0.5 degrees azimuth uncertainty while enabling operation at significantly higher temperatures than the state-of-the-art. In Budget Period 2, we successfully completed the integration of the MRGT and ASIC with associated high temperature, high reliability packaging to demonstrate the performance and functionality of the integrated gyroscope across the temperature range from room temperature to at 300°C. Furthermore, the team demonstrated operating life of >1,000 hours at 300°C, thus providing a validation of application-relevant lifetime capability.

15 GEOTHERMAL ENERGY↗

Bound States in the Continuum on a Silicon Chip with Dynamic Tuning

Expanding bound states in the continuum (BIC) beyond photonic crystal systems may enable broader applications benefiting from the unique properties of BIC states. We use photonic integrated circuit to realize a Fabry-Pérot BIC on a silicon chip. The devices consist of cascaded ring resonators with tunable resonance frequencies and phase delays. As a result, the BIC state is dynamically tuned with electrical I/O. We analyze the mechanism of the formation of BIC states in this waveguide system and point out the fundamental differences between the BIC states and electromagnetically induced transparency states in integrated photonics. The high transmission protected by the BIC state enables versatile optical filters, which are capable of independent control over switching, peak position, and quality factor. We also demonstrate the scalability of this platform. As a result, this integrated silicon photonic platform brings opportunities for practical BIC applications.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Characterization of the First Prototype of the L1K65n Differential-Output Charge-Sensitive Preamplifier ASIC for High-Performance, Low-Background HPGe Detector Readout

Next-generation neutrinoless double-beta (0νββ) decay searches require a large detector/isotope mass and very low radioactive backgrounds. The upcoming LEGEND-1000 experiment (Large Enriched Germanium Experiment for Neutrinoless double-beta Decay) constitute a ton-scale array of several hundred high-purity germanium (HPGe) detectors enriched in 76Ge, the isotope of interest. It aims to reach a sensitivity beyond 10 28 years on the 0νββ decay half-life of 76Ge, necessitating an order of magnitude reduction in background with respect to the state of the art. This will require the implementation of a dedicated application specific integrated circuit (ASIC) preamplifier that will significantly lower background contribution compared to the conventional low-mass front end (LMFE) employed in the Majorana Demonstrator and LEGEND-200 experiments while maintaining or improving energy resolution and other performance parameters. Features include a high (9 MeV) dynamic range with noise low enough to achieve a trigger threshold of <1 keV, a single power supply to reduce background-inducing cabling, and a differential output to maintain signal integrity over several meters of transmission line. The chip would be optimized to operate in liquid argon (87 K) and be able to do so reliably for ten years. Following on from an earlier 180-nm prototype, we have developed a differential-output charge-sensitive preamplifier ASIC fabricated in a 65-nm process, 1×2 mm in size, that addresses these needs. Here, we present recent results from the successful testing and characterization of the first version of this device.

ASIC↗

Intelligent Proppants for Hydraulic Fracture Diagnostics

This Phase 1 Report details our Phase 1 progress in proving the feasibility of a highly integrated, highly miniaturized sensor ball. The ball contains sensors, analog to digital converters, memory, a clock, and an acoustic communications module all integrated onto a single silicon chip. Phase 2 is to focus on the application specific integrated circuit (ASIC). Phase 1 piecewise proves the feasibility of this innovation by examining a few critical subsystems including the communications module and inertial sensor performance. Acoustic simulations of an acoustically active and traceable proppant are also performed and summarized in this report.

01 COAL, LIGNITE, AND PEAT↗

Physics and applications of quantum dot lasers for silicon photonics

Abstract Photonic integrated circuits (PICs) have enabled numerous high performance, energy efficient, and compact technologies for optical communications, sensing, and metrology. One of the biggest challenges in scaling PICs comes from the parasitic reflections that feed light back into the laser source. These reflections increase noise and may cause laser destabilization. To avoid parasitic reflections, expensive and bulky optical isolators have been placed between the laser and the rest of the PIC leading to large increases in device footprint for on-chip integration schemes and significant increases in packaging complexity and cost for lasers co-packaged with passive PICs. This review article reports new findings on epitaxial quantum dot lasers on silicon and studies both theoretically and experimentally the connection between the material properties and the ultra-low reflection sensitivity that is achieved. Our results show that such quantum dot lasers on silicon exhibit much lower linewidth enhancement factors than any quantum well lasers. Together with the large damping factor, we show that the quantum dot gain medium is fundamentally dependent on dot uniformity, but through careful optimization, even epitaxial lasers on silicon can operate without an optical isolator, which is of paramount importance for the future high-speed silicon photonic systems.

36 MATERIALS SCIENCE↗