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At least 163 records · Page 9

MAFT: The Multicomputer Architecture for Fault-Tolerance

Multicomputer Architecture for Fault-Tolerance (MAFT) is a loosely coupled multiprocessor system designed to achieve an unreliability of less than 10(exp -10)/hr in flight-critical real time applications. The MAFT design objectives and architecture are presented. The fault-tolerance implementation of major functions in MAFT is also presented, including communication; task scheduling; reconfiguration; clock synchronization; and data handling and voting. The need for Byzantine agreement or approximate agreement in various functions is discussed. Different methods were selected to achieve agreement in various subsystems. These methods are illustrated by a more detailed description of the task scheduling and error handling subsystems.

Kieckhafer, Roger M.↗

Resilience and fault tolerance in high-performance computing for numerical weather and climate prediction

Progress in numerical weather and climate prediction accuracy greatly depends on the growth of the available computing power. As the number of cores in top computing facilities pushes into the millions, increased average frequency of hardware and software failures forces users to review their algorithms and systems in order to protect simulations from breakdown. This report surveys hardware, application-level and algorithm-level resilience approaches of particular relevance to time-critical numerical weather and climate prediction systems. A selection of applicable existing strategies is analysed, featuring interpolation-restart and compressed checkpointing for the numerical schemes, in-memory checkpointing, user-level failure mitigation and backup-based methods for the systems. Numerical examples showcase the performance of the techniques in addressing faults, with particular emphasis on iterative solvers for linear systems, a staple of atmospheric fluid flow solvers. The potential impact of these strategies is discussed in relation to current development of numerical weather prediction algorithms and systems towards the exascale. Trade-offs between performance, efficiency and effectiveness of resiliency strategies are analysed and some recommendations outlined for future developments.

54 ENVIRONMENTAL SCIENCES↗

The software-implemented fault tolerance /SIFT/ approach to fault tolerant computing

SIFT is an experimental computer designed for highly reliable flight-control service in advanced air transports. Its development was intended to integrate and demonstrate the latest techniques in fault-tolerant computing. During its development, several new problems of some generality were uncovered and solved. The technology developed for the validation of its design is seen as being perhaps as important as the design itself. The SIFT design is described, as is the way in which the design and its validation were shaped by the requirements of its intended application. Attention is also given to reliability and fault tolerance. The most significant feature of the hardware design is the absence of elements that can generate multiple faults, such as shared clocks or data buses. It is noted that the software is realized in only 800 lines of code, of which 80% are in a high-level language.

Goldberg, J.↗

Design for dependability: A simulation-based approach

This research addresses issues in simulation-based system level dependability analysis of fault-tolerant computer systems. The issues and difficulties of providing a general simulation-based approach for system level analysis are discussed and a methodology that address and tackle these issues is presented. The proposed methodology is designed to permit the study of a wide variety of architectures under various fault conditions. It permits detailed functional modeling of architectural features such as sparing policies, repair schemes, routing algorithms as well as other fault-tolerant mechanisms, and it allows the execution of actual application software. One key benefit of this approach is that the behavior of a system under faults does not have to be pre-defined as it is normally done. Instead, a system can be simulated in detail and injected with faults to determine its failure modes. The thesis describes how object-oriented design is used to incorporate this methodology into a general purpose design and fault injection package called DEPEND. A software model is presented that uses abstractions of application programs to study the behavior and effect of software on hardware faults in the early design stage when actual code is not available. Finally, an acceleration technique that combines hierarchical simulation, time acceleration algorithms and hybrid simulation to reduce simulation time is introduced.

Goswami, Kumar K.↗

A performance assessment of a byzantine resilient fault-tolerant computer

This report presents the results of a performance analysis of a quad-redundant Fault-Tolerant Processor (FTP). The FTP is a computing system specifically designed for applications where very high reliability is required. Examples of such applications are flight control systems, nuclear power systems, and spacecraft control systems. The FTP performance was analyzed in a hierarchical manner encompassing the hardware, the operating system, and the application. At the hardware level, the hardware organization and design was assessed in relation to system throughput and response. Analysis at the operating system level revealed that the scheduler took only 3.2 percent of each 40ms frame, while the redundancy management software took 10.4 percent. The application level performance was analyzed via a synthetic workload and a representative flight control model. The estimated throughput for this application was found to be 317.6 KIPS if not exercising the voter. Exercising the voter to ensure fault tolerance will diminish this number linearly as the number of votes is increased. This performance analysis method was proven effective by uncovering undesirable behavior and anomalies in the FTP system.

Young, Steven D.↗

Advanced Visualization of Silent Error Propagation in HPC Applications

Last year, we refactored the major components of the SpotSDC visualization platform and added a visualization component for fault tolerance boundary. Also, we designed a new analysis framework to understand an application resiliency with a significantly less amount of samples compared to previous approaches. We evaluated the visualization platform and analysis framework for multiple critical HPC computation kernels and collected evidence for the effectiveness of the method developed.

97 MATHEMATICS AND COMPUTING↗

Advanced Visualization of Silent Error Propagation in HPC Applications

Last year, we refactored the major components of the SpotSDC visualization platform and added a visualization component for fault tolerance boundary. Also, we designed a new analysis framework to understand an application resiliency with a significantly less amount of samples compared to previous approaches. We evaluated the visualization platform and analysis framework for multiple critical HPC computation kernels and collected evidence for the effectiveness of the method developed. We published the findings of our research in the IEEE Transactions on Visualization and Computer Graphics (TVCG), the top journal in visualization. Moreover, we submitted a new paper, "Understanding a Program's Resiliency Through Error Propagation," to the PPOPP 2021 conference.

97 MATHEMATICS AND COMPUTING↗

Peer-to-Peer Communication Trade-Offs for Smart Grid Applications: Preprint

Peer-to-peer energy management systems for smart grids require developers to consider the trade-offs between the amount of communication traffic generated and the quality and speed of convergence of the control algorithms that are deployed. Employing a fully connected communication causes messages to scale exponentially with the number of nodes, while using a sparse connectivity causes less information dissemination leading to degradation of the algorithm performance. The best communication topology for a particular application lies somewhere in between and often requires empirical evaluation by application designers. Existing methods do not put focus on the needs for smart grid applications, which is information dissemination throughout the network and they do not provide a flexible solution for application developers to prototype and deploy different topologies without modifying the application code. This paper introduces a configurable virtual communication topology framework TopLinkMgr, allowing users to specify any chosen communication topology and deploy peer-to-peer applications using it. It also introduces a self-adaptive, fault-tolerant topology management algorithm, Bounded Path Dissemination that can ensure the dissemination of information to all peers within a specified threshold for a sparsely connected topology. Experiments show that the algorithm improves on convergence speed and accuracy over state-of-the-art methods and is also robust against node failures. The results indicate the possibility of achieving a close-to optimal convergence without overloading the network allowing the realization of peer-to-peer control platforms covering larger and more complex power systems.

Bounded Path Dissemination↗

Extremum-seeking control for an Ultrasonic/Sonic Driller/Corer (USDC) driven at high-power

Future NASA exploration missions will increasingly require sampling, in-situ analysis and possibly the return of material to Earth for further tests. One of the challenges to addressing this need is the ability to drill using for low axial loading while operating from light weight platforms (e.g., lander, rover, etc.) as well as operate at planets with low gravity. For this purpose, the authors developed the Ultrasonic/Sonic Driller/Corer (USDC) jointly with Cybersonics Inc. Studies of the operation of the USDC at high power have shown there is a critical need to self-tune to maintain the operation of the piezoelectric actuator at resonance. Performing such tuning is encountered with difficulties and to address them an extremum-seeking control algorithm is being investigated. This algorithm is designed to tune the driving frequency of a time-varying resonating actuator subjected to both random and high-power impulsive noise disturbances. Using this algorithm the performance of the actuator is monitored on a time-scale that is compatible with its slowly time-varying physical characteristics. The algorithm includes a parameter estimator, which estimates the coefficients of a function that characterizes the quality factor of the USDC. Since the parameter estimator converges sufficiently faster than the time-varying drift of the USDC's physical parameters, the proposed extremum-seeking estimation and control algorithm is potentially applicable for use as a closed-loop health monitoring system. Specifically, this system may be programmed to automatically adjust the duty-cycle of the sinusoidal driver signal to guarantee that the quality factor of the USDC does not fall below a user-defined set-point. Such fault-tolerant functionality is especially important in automated drilling applications where it is essential not to inadvertently drive the piezoelectric ceramic crystals of the USDC beyond their capacities. The details of the algorithm and experimental results will be described and discussed in this paper.

Peek-seeking estimation and control↗

A Modular Robotic System with Applications to Space Exploration

Modular robotic systems offer potential advantages as versatile, fault-tolerant, cost-effective platforms for space exploration, but a sufficiently mature system is not yet available. We describe the possible applications of such a system, and present prototype hardware intended as a step in the right direction. We also present elements of an automated design and optimization framework aimed at making modular robots easier to design and use, and discuss the results of applying the system to a gait optimization problem. Finally, we discuss the potential near-term applications of modular robotics to terrestrial robotics research.

Hancher, Matthew D.↗

Empowering a qudit-based quantum processor by traversing the dual bosonic ladder

Abstract High-dimensional quantum information processing has emerged as a promising avenue to transcend hardware limitations and advance the frontiers of quantum technologies. Harnessing the untapped potential of the so-called qudits necessitates the development of quantum protocols beyond the established qubit methodologies. Here, we present a robust, hardware-efficient, and scalable approach for operating multidimensional solid-state systems using Raman-assisted two-photon interactions. We then utilize them to construct extensible multi-qubit operations, realize highly entangled multidimensional states including atomic squeezed states and Schrödinger cat states, and implement programmable entanglement distribution along a qudit array. Our work illuminates the quantum electrodynamics of strongly driven multi-qudit systems and provides the experimental foundation for the future development of high-dimensional quantum applications such as quantum sensing and fault-tolerant quantum computing.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

A Decoupled Droop Control Strategy for Cascaded Multicell Inverter with Low-Frequency Modulation

Cascaded multicell inverter (CMI), featured by its merits of modularity and fault-tolerance, is suitable for medium-voltage applications without using bulky step-up transformers. However, little research has reported grid-forming control of the CMI for the application in the power grid with high penetrations of inverter-interfaced generation. To bridge this research gap, this paper proposes a novel droop control strategy for the CMI with a low-frequency modulation to offer inertia and reactive power support to the power grid. A decoupled Q/V droop control strategy is proposed to eliminate the coupling effect from the P/ω control loop caused by the phase-angle difference between the voltages of the CMI and the grid. The output of the Q/V control loop is set as the reference voltage for each cell of the CMI, which makes the CMI naturally a voltage source to provide a grid-forming capability. Finally, the proposed control strategy shows great active and reactive power regulation and sharing capability, which is validated by simulation on two 100 kW, 2.4 kV CMIs connected in parallel to a power grid.

14 SOLAR ENERGY↗

Rule-based fault-tolerant flight control

Fault tolerance has always been a desirable characteristic of aircraft. The ability to withstand unexpected changes in aircraft configuration has a direct impact on the ability to complete a mission effectively and safely. The possible synergistic effects of combining techniques of modern control theory, statistical hypothesis testing, and artificial intelligence in the attempt to provide failure accommodation for aircraft are investigated. This effort has resulted in the definition of a theory for rule based control and a system for development of such a rule based controller. Although presented here in response to the goal of aircraft fault tolerance, the rule based control technique is applicable to a wide range of complex control problems.

Handelman, Dave↗

A model for the analysis of fault-tolerant signal processing architectures

This paper develops a new model, using matrices, for the analysis of fault-tolerant multiprocessor systems. The relationship between processors computing useful data, the output data, and the check processors is defined in terms of matrix entries. Unlike the matrix-based models proposed previously for the analysis of digital systems, this model uses only numerical computations rather than logical operations for the analysis of a system. Algorithms to evaluate the fault detection and location capability of the system are proposed which are much less complex than the existing ones. The new model is used to analyze some fault-tolerant architectures proposed for signal-processing applications.

Nair, V. S. S.↗

Towards the formal verification of the requirements and design of a processor interface unit: HOL listings

This technical report contains the Higher-Order Logic (HOL) listings of the partial verification of the requirements and design for a commercially developed processor interface unit (PIU). The PIU is an interface chip performing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault tolerant computer system. This system, the Fault Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. This report contains the actual HOL listings of the PIU verification as it currently exists. Section two of this report contains general-purpose HOL theories and definitions that support the PIU verification. These include arithmetic theories dealing with inequalities and associativity, and a collection of tactics used in the PIU proofs. Section three contains the HOL listings for the completed PIU design verification. Section 4 contains the HOL listings for the partial requirements verification of the P-Port.

Fura, David A.↗

Towards the formal specification of the requirements and design of a processor interface unit: HOL listings

This technical report contains the HOL listings of the specification of the design and major portions of the requirements for a commercially developed processor interface unit (or PIU). The PIU is an interface chip performing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. This report contains the actual HOL listings of the PIU specification as it currently exists. Section two of this report contains general-purpose HOL theories that support the PIU specification. These theories include definitions for the hardware components used in the PIU, our implementation of bit words, and our implementation of temporal logic. Section three contains the HOL listings for the PIU design specification. Aside from the PIU internal bus (I-Bus), this specification is complete. Section four contains the HOL listings for a major portion of the PIU requirements specification. Specifically, it contains most of the definition for the PIU behavior associated with memory accesses initiated by the local processor.

Fura, David A.↗

Towards the formal specification of the requirements and design of a processor interface unit

Work to formally specify the requirements and design of a Processor Interface Unit (PIU), a single-chip subsystem providing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system, is described. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance free operation, or both. The approaches that were developed for modeling the PIU requirements and for composition of the PIU subcomponents at high levels of abstraction are described. These approaches were used to specify and verify a nontrivial subset of the PIU behavior. The PIU specification in Higher Order Logic (HOL) is documented in a companion NASA contractor report entitled 'Towards the Formal Specification of the Requirements and Design of a Processor Interfacs Unit - HOL Listings.' The subsequent verification approach and HOL listings are documented in NASA contractor report entitled 'Towards the Formal Verification of the Requirements and Design of a Processor Interface Unit' and NASA contractor report entitled 'Towards the Formal Verification of the Requirements and Design of a Processor Interface Unit - HOL Listings.'

Fura, David A.↗

Failure Accommodation Tested in Magnetic Suspension Systems for Rotating Machinery

The NASA Glenn Research Center at Lewis Field and Texas A&M University are developing techniques for accommodating certain types of failures in magnetic suspension systems used in rotating machinery. In recent years, magnetic bearings have become a viable alternative to rolling element bearings for many applications. For example, industrial machinery such as machine tool spindles and turbomolecular pumps can today be bought off the shelf with magnetically supported rotating components. Nova Gas Transmission Ltd. has large gas compressors in Canada that have been running flawlessly for years on magnetic bearings. To help mature this technology and quiet concerns over the reliability of magnetic bearings, NASA researchers have been investigating ways of making the bearing system tolerant to faults. Since the potential benefits from an oil-free, actively controlled bearing system are so attractive, research that is focused on assuring system reliability and safety is justifiable. With support from the Fast Quiet Engine program, Glenn's Structural Mechanics and Dynamics Branch is working to demonstrate fault-tolerant magnetic suspension systems targeted for aerospace engine applications. The Flywheel Energy Storage Program is also helping to fund this research.

Provenza, Andy J.↗