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Miniaturized thermoelectric devices integrated into thermal management packages and low power, high voltage, electrical power source systems are of interest for a variety of space and terrestrial applications.
Low-cost, commercial-off-the-shelf- (COTS-) based science cameras are intended for lab use only and are not suitable for flight deployment as they are difficult to ruggedize and repackage into instruments. Also, COTS implementation may not be suitable since mission science objectives are tied to specific measurement requirements, and often require performance beyond that required by the commercial market. Custom camera development for each application is cost prohibitive for the International Space Station (ISS) or midrange science payloads due to nonrecurring expenses (~$2,000 K) for ground-up camera electronics design. While each new science mission has a different suite of requirements for camera performance (detector noise, speed of image acquisition, charge-coupled device (CCD) size, operation temperature, packaging, etc.), the analog-to-digital conversion, power supply, and communications can be standardized to accommodate many different applications. The low noise camera for suborbital applications is a rugged standard camera platform that can accommodate a range of detector types and science requirements for use in inexpensive to mid range payloads supporting Earth science, solar physics, robotic vision, or astronomy experiments. Cameras developed on this platform have demonstrated the performance found in custom flight cameras at a price per camera more than an order of magnitude lower.
The scientific devices designed for each of the Outer Planets Program Focuses will likely be groundbreaking not only with respect to their scientific role but also regarding the electronics required to perform such investigations. In the past, the performance of packaged electronics was limited by the components themselves, with minimal influence of the packaging technology. The rapid development of integrated circuit technology, however, has drastically increased the importance of packaging technology in the ultimate performance of devices. If not carefully considered in the overall design, the packaging may become the limiting factor in the operation of the system. Although industry is responsible for several significant accomplishments in the field of electronics packaging, deep space/outer planet missions must take into account additional requirements such as extremely low temperatures, high radiation levels, hermetic sealing, and severe size and weight limitations. Therefore, the present investigation has been designed to meet the needs of NASA's sensor intensive outer planets program by combining (using flip chip technology) an array of devices (including analog, digital, power volt-age, passives, and MEMS) into a miniaturized heterogeneous system and utilizing optical buses to enable autonomy. Additional information is contained in the original extended abstract.
The current state-of-the-art flip chip packages for space applications are the class-Y non-hermetic ceramic packages, whereas for commercial applications, organic packages have been the mainstream technology for about two decades. The high reliability of the class-Y parts suggests that the hermeticity is not critical for the reliability of flip chip devices and that organic flip chip packages could be reliable enough for space applications. The current report summarizes the result of collaboration between JPL and Cobham semiconductor space solutions to study the reliability of the organic flip chip packages.
Thermo-mechanical analysis (TMA) is typically employed for measurements of the glass transition temperature (Tg) and coefficients of thermal expansion (CTE) in molding compounds used in plastic encapsulated microcircuits (PEMs). Application of TMA measurements directly to PEMs allows anomalies to be revealed in deformation of packages with temperature, and thus indicates possible reliability concerns related to thermo-mechanical integrity and stability of the devices. In this work, temperature dependencies of package deformation were measured in several types of PEMs that failed environmental stress testing including temperature cycling, highly accelerated stress testing (HAST) in humid environments, and bum-in (BI) testing. Comparison of thermo-mechanical characteristics of packages and molding compounds in the failed parts allowed for explanation of the observed failures. The results indicate that TMA of plastic packages might be used for quality evaluation of PEMs intended for high-reliability applications.
During electrical testing of a Full Field CCD Image Senor, electrical shorts were detected on three of six devices. These failures occurred after the parts were soldered to the PCB. Failure analysis was performed to determine the cause and locations of these failures on the devices. After removing the fiber optic faceplate, optical inspection was performed on the CCDs to understand the design and package layout. Optical inspection revealed that the device had a light shield ringing the CCD array. This structure complicated the failure analysis. Alternate methods of analysis were considered, including liquid crystal, light and thermal emission, LT/A, TT/A SQUID, and MP. Of these, SQUID and MP techniques were pursued for further analysis. Also magnetoresistive current imaging technology is discussed and compared to SQUID.
High-temperature electronics and sensors are necessary for harsh-environment space and aeronautical applications, such as sensors and electronics for space missions to the inner solar system, sensors for in situ combustion and emission monitoring, and electronics for combustion control for aeronautical and automotive engines. However, these devices cannot be used until they can be packaged in appropriate forms for specific applications. Suitable packaging technology for operation temperatures up to 500 C and beyond is not commercially available. Thus, the development of a systematic high-temperature packaging technology for SiC-based microsystems is essential for both in situ testing and commercializing high-temperature SiC sensors and electronics. In response to these needs, researchers at Glenn innovatively designed, fabricated, and assembled a new prototype electronic package for high-temperature electronic microsystems using ceramic substrates (aluminum nitride and aluminum oxide) and gold (Au) thick-film metallization. Packaging components include a ceramic packaging frame, thick-film metallization-based interconnection system, and a low electrical resistance SiC die-attachment scheme. Both the materials and fabrication process of the basic packaging components have been tested with an in-house-fabricated SiC semiconductor test chip in an oxidizing environment at temperatures from room temperature to 500 C for more than 1000 hr. These test results set lifetime records for both high-temperature electronic packaging and high-temperature electronic device testing. As required, the thick-film-based interconnection system demonstrated low (2.5 times of the room-temperature resistance of the Au conductor) and stable (decreased 3 percent in 1500 hr of continuous testing) electrical resistance at 500 C in an oxidizing environment. Also as required, the electrical isolation impedance between printed wires that were not electrically joined by a wire bond remained high (greater than 0.4 GW) at 500 C in air. The attached SiC diode demonstrated low (less than 3.8 W/mm2) and relatively consistent dynamic resistance from room temperature to 500 C. These results indicate that the prototype package and the compatible die-attach scheme meet the initial design standards for high-temperature, low-power, and long-term operation. This technology will be further developed and evaluated, especially with more mechanical tests of each packaging element for operation at higher temperatures and longer lifetimes.
NEPP supports all of NASA for >20 years - 7 NASA Centers and JPL actively participate The NEPP Program focuses on the reliability aspects of electronic devices - Three prime technical areas: Parts (die), Packaging, and Radiation Alternately, reliability may be viewed as: -
We have reported SiC integrated circuits (IC's) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 C [1, 2]. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 C [3]. However, this thermal ramp was not ended until a peak temperature of 880 C (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology. Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 C. In one test, the temperature was ramped and then held at 727 C, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 C before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 C (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 C.
We have reported SiC integrated circuits (ICs) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 degrees Centigrade. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 degrees Centigrade. However, this thermal ramp was not ended until a peak temperature of 880 degrees Centigrade (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology.Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 degrees Centigrade. In one test, the temperature was ramped and then held at 727 degrees Centigrade, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 degrees Centigrade before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 degrees Centigrade (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 degrees Centigrade.
Heterodyne terahertz (0.3 - 3THz) imaging systems are currently limited to single or a low number of pixels. Drastic improvements in imaging sensitivity and speed can be achieved by replacing single pixel systems with an array of detectors. This paper presents an array topology that is being developed at the Jet Propulsion Laboratory based on the micromachining of silicon. This technique fabricates the array's package and waveguide components by plasma etching of silicon, resulting in devices with precision surpassing that of current metal machining techniques. Using silicon increases the versatility of the packaging, enabling a variety of orientations of circuitry within the device which increases circuit density and design options. The design of a two-pixel transceiver utilizing a stacked architecture is presented that achieves a pixel spacing of 10mm. By only allowing coupling from the top and bottom of the package the design can readily be arrayed in two dimensions with a spacing of 10mm x 18mm.
A proposed thermoelectric device would exploit natural temperature differences between air and soil to harvest small amounts of electric energy. Because the air/soil temperature difference fluctuates between nighttime and daytime, it is almost never zero, and so there is almost always some energy available for harvesting. Unlike photovoltaic cells, the proposed device could operate in the absence of sunlight. Unlike a Stirling engine, which could be designed to extract energy from the air/soil temperature difference, the proposed device would contain no moving parts. The main attractive feature of the proposed device would be high reliability. In a typical application, this device would be used for low-power charging of a battery that would, in turn, supply high power at brief, infrequent intervals for operating an instrumentation package containing sensors and communication circuits. The device (see figure) would include a heat exchanger buried in soil and connected to a heat pipe extending up to a short distance above the ground surface. A thermoelectric microgenerator (TEMG) would be mounted on top of the heat pipe. The TEMG could be of an advanced type, now under development, that could maintain high (relative to prior thermoelectric generators) power densities at small temperature differentials. A heat exchanger exposed to the air would be mounted on top of the TEMG. It would not matter whether the air was warmer than the soil or the soil warmer than the air: as long as there was a nonzero temperature difference, heat would flow through the device and electricity would be generated. A study of factors that could affect the design and operation of the device has been performed. These factors include the thermal conductances of the soil, the components of the device, the contacts between the components of the device, and the interfaces between the heat exchangers and their environments. The study included experiments that were performed on a model of the device to demonstrate feasibility. Because a TEMG suitable for this device was not available, a brass dummy component having a known thermal conductance of 1.68 W/K was substituted for the TEMG in the models to enable measurement of heat flows. The model included a water-based heat pipe 30 in. (76.2 cm) long and 1 in. (2.54 cm) in diameter, wrapped with polyethylene insulation to reduce radial heat flow. Several different side heat exchangers were tested. On the basis of the measurements, it was predicted that if a prototype of the device were equipped with a TEMG, daily temperature fluctuations would cause its output power to fluctuate between 0 and about 0.1 mW, peaking to 0.35 mW during early afternoon.
A Multiple Internal Seal Ring (MISR) Micro-Electro-Mechanical System (MEMS) vacuum packaging method that hermetically seals MEMS devices using MISR. The method bonds a capping plate having metal seal rings to a base plate having metal seal rings by wafer bonding the capping plate wafer to the base plate wafer. Bulk electrodes may be used to provide conductive paths between the seal rings on the base plate and the capping plate. All seals are made using only metal-to-metal seal rings deposited on the polished surfaces of the base plate and capping plate wafers. However, multiple electrical feed-through metal traces are provided by fabricating via holes through the capping plate for electrical connection from the outside of the package through the via-holes to the inside of the package. Each metal seal ring serves the dual purposes of hermetic sealing and providing the electrical feed-through metal trace.
A conventional low-noise detector requires a technique to both absorb incident power and convert it to an electrical signal at cryogenic temperatures. This innovation combines low-noise detector and readout functionality into one device while maintaining high absorption, controlled polarization sensitivity, and broadband detection capability. The resulting far-infrared detectors can be read out with a simple approach, which is compact and minimizes thermal loading. The proposed microwave kinetic inductance detector (MKID) consists of three basic elements. The first is the absorptive section in which the incident power is coupled to a superconducting resonator at far-infrared frequency above its superconducting critical frequency (where superconductor becomes normal conductor). This absorber's shape effectively absorbs signals in the desired polarization state and is resonant at the radio frequency (RF) used for readout of the device. Control over the metal film used in the absorber allows realization of structures with either a 50% broadband or 100% resonance absorptance over a 30% fractional bandwidth. The second element is a microwave resonator - which is realized from the thin metal films used to make the absorber as transmission lines - whose resonance frequency changes due to a variation in its kinetic inductance. The resonator's kinetic inductance is a function of the power absorbed by the device. A low-loss dielectric (mono-crystalline silicon) is used in a parallel-plate transmission line structure to realize the desired superconducting resonators. There is negligible coupling among the adjacent elements used to define the polarization sensitivity of each detector. The final component of the device is a microwave transmission line, which is coupled to the resonator, and allows detection of changes in resonance frequency for each detector in the focal plane array. The spiral shape of the detector's absorber allows incident power with two polarizations to couple to the detector equally. A stepped impedance resonator was used that allows the incident power absorbed in the detecting membrane area to be uniformly distributed in the detector's transmission line at the RF readout frequency. This maximizes the sensitivity of the detector. The signal is read out via a frequency multiplexing technique that requires a minimum number of interface transmission lines for readout. This reduces the packaging complexity and coupling to the device's thermal environment.
Wearable technology has the potential to revolutionize the way humans interact with one another, with information, and with the electronic systems that surround them. This change can already be seen in the dramatic increase in the availability and use of wearable health and activity monitors. These devices continuously monitor the wearer using on-‐body sensors and wireless communication. They provide feedback that can be used to improve physical health and performance. Smart watches and head mounted displays are also receiving a great deal of commercial attention, providing immediate access to information via graphical displays, as well as additional sensing features. For the purposes of the Wearable Technology CLUSTER, wearable technology is broadly defined as any electronic sensing, human interfaces, computing, or communication that is mounted on the body. Current commercially available wearable devices primarily house electronics in rigid packaging to provide protection from flexing, moisture, and other contaminants. NASA mentors are interested in this approach, but are also interested in direct integration of electronics into clothing to enable more comfortable systems. For human spaceflight, wearable technology holds a great deal of promise for significantly improving safety, efficiency, autonomy, and research capacity for the crew in space and support personnel on the ground. Specific capabilities of interest include: Continuous biomedical monitoring for research and detection of health problems. Environmental monitoring for individual exposure assessments and alarms. Activity monitoring for responsive robotics and environments. Multi-modal caution and warning using tactile, auditory, and visual alarms. Wireless, hands-free, on-demand voice communication. Mobile, on-demand access to space vehicle and robotic displays and controls. Many technical challenges must be overcome to realize these wearable technology applications. For example, to make a wearable device that is both functional and comfortable for long duration wear, developers must strive to reduce electronic mass and volume while also addressing constraints imposed by the body attachment method. Depending on the application, the device must be placed in a location that the user can see and reach, and that provides the appropriate access to air and the wearer's skin. Limited power is available from body-‐worn batteries and heat must be managed to prevent discomfort. If the clothing is to be washed, there are additional durability and washability hurdles that traditional electronics are not designed to address. Finally, each specific capability has unique technical challenges that will likely require unique solutions. In addition to the technical challenges, development of wearable devices is made more difficult by the diversity of skills required and the historic lack of collaboration across domains. Wearable technology development requires expertise in textiles engineering, apparel design, software and computer engineering, electronic design and manufacturing, human factors engineering, and application-‐specific fields such as acoustics, medical devices, and sensing. Knowledge from each of these domains must be integrated to create functional and comfortable devices. For this reason, the diversity of knowledge and experience represented in the Wearable Technology is critical to overcoming the fundamental challenges in the field.
A package of high-power switching semiconductors for the space station have been designed and fabricated. The package includes a high-voltage (600 volts) high current (50 amps) NPN Fast Switching Power Transistor and a high-voltage (1200 volts), high-current (50 amps) Fast Recovery Diode. The package features an isolated collector for the transistors and an isolated anode for the diode. Beryllia is used as the isolation material resulting in a thermal resistance for both devices of .2 degrees per watt. Additional features include a hermetical seal for long life -- greater than 10 years in a space environment. Also, the package design resulted in a low electrical energy loss with the reduction of eddy currents, stray inductances, circuit inductance, and capacitance. The required package design and device parameters have been achieved. Test results for the transistor and diode utilizing the space station package is given.
Increased fuel costs, heightened environmental protection requirements, and noise abatement continue to place drag reduction at the forefront of aerospace research priorities. Unfortunately, shortfalls still exist in the fundamental understanding of boundary-layer airflow over aerodynamic surfaces, especially regarding drag arising from skin friction. For example, there is insufficient availability of instrumentation to adequately characterize complex flows with strong pressure gradients, heat transfer, wall mass flux, three-dimensionality, separation, shock waves, and transient phenomena. One example is the acoustic liner efficacy on aircraft engine nacelle walls. Active measurement of shear stress in boundary layer airflow would enable a better understanding of how aircraft structure and flight dynamics affect skin friction. Current shear stress measurement techniques suffer from reliability, complexity, and airflow disruption, thereby compromising resultant shear stress data. The state-of-the-art for shear stress sensing uses indirect or direct measurement techniques. Indirect measurements (e.g., hot-wire, heat flux gages, oil interferometry, laser Doppler anemometry, small scale pressure drag surfaces, i.e., fences) require intricate knowledge of the studied flow, restrictive instrument arrangements, large surface areas, flow disruption, or seeding material; with smaller, higher bandwidth probes under development. Direct measurements involve strain displacement of a sensor element and require no prior knowledge of the flow. Unfortunately, conventional "floating" recessed components for direct measurements are mm to cm in size. Whispering gallery mode devices and Fiber Bragg Gratings are examples of recent additions to this type of sensor with much smaller (m) sensor components. Direct detection techniques are often single point measurements and difficult to calibrate and implement in wind tunnel experiments. In addition, the wiring, packaging, and installation of delicate micro-electromechanical devices impede the use of most direct shear sensors. Similarly, the cavity required for sensing element displacement is sensitive to particulate obstruction. This work was focused on developing a shear stress sensor for use in subsonic wind tunnel test facilities applicable to an array of test configurations. The non-displacement shear sensors described here have minimal packaging requirements resulting in minimal or no disturbance of boundary layer flow. Compared to previous concepts, device installation could be simple with reduced cost and down-time. The novelty lies in the creation of low profile (nanoscale to 100 μm) micropost arrays that stay within the viscous sub-layer of the airflow. Aerodynamic forces, which are related to the surface shear stress, cause post deflection and optical property changes. Ultimately, a reliable, accurate shear stress sensor that does not disrupt the airflow has the potential to provide high value data for flow physics researchers, aerodynamicists, and aircraft manufacturers leading to greater flight efficiency arising from more in-depth knowledge on how aircraft design impacts near surface properties.
With the rapidly increasing insertion of photonic devices, circuits and subsystems into NASA spacecraft, a variety of issues associated with reliability and radiation tolerance have arisen. In this paper, we discuss these issues from the perspective of the work currently ongoing in the NASA Electronic Parts and Packaging (NEPP) Program. This Program is focused on evaluating the reliability and radiation response of advanced and emerging microelectronics and photonics technologies of interest to NASA spacecraft system designers.