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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 163 records · Page 9
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

A 32-Channel Cryo-CMOS ASIC for SNSPD Biasing and Readout with Picosecond

Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specific integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifiers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verified using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.

Fredenburg, Jeff↗
DOE OSTI2024

A 32-Channel Cryo-CMOS ASIC for SNSPD Biasing and Readout with Picosecond Timing

Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specifc integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verifed using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.

Fredenburg, Jeff↗
DOE OSTI2022

Microfluidic Uranium Microspheres Production for TRISO and Advanced Fuel Concepts

The purpose of this project was to expand existing internal gelation sol-gel capabilities at PNNL to explore producing uranium dioxide spheres for potential use as fuel kernels in next generation Tri-isotropic (TRISO) particle fuel. This project expands on previous sol-gel efforts at PNNL by (1) increasing the size regime of sphere production from the micro-fluidic range to the milli-fluidic range, and (2) producing uranium spheres. The approach involved first scaling up the channel size of the fluidic system to the millimeter range, with radiation safety considerations in mind; testing and demonstration on non-radioactive surrogate material, cerium oxide; then transitioning to uranium production and finally optimizing system parameters. Commercially available fluidic chips in the desired size range were could not be found, therefore the project designed and fabricated a T-junction with 1mm channels for droplet production. Because the production process is temperature sensitive, prior efforts have involved performing droplet production in a lab freezer. To reduce radiological waste and footprint, two alternative chilling methods were explored using aluminum thermal beads as a chill bath and a custom aluminum block fit to reagent reservoir sizes. Both were successful in the cerium tests, however the aluminum block design outperformed the thermal bead bath and was further adapted for the radiological test and production run in the Radiochemical Processing Laboratory (RPL). Gelation trials were performed to determine an acceptable range of feed solution parameters for the uranium dioxide gels, characterized by R-values, which is determined by the ratio of uranium nitrate to Hexamethylenetetramine (HMTA)/urea in the feed solution. R-values ranging from 1.6-2 were examined in the gelation trials, with only the 1.8 condition being tested in production. The project was successful in demonstrating a proof of concept design for producing uranium dioxide spheres, however further optimization is needed to dial in production parameters and improve sphere quality and homogeneity.

11 NUCLEAR FUEL CYCLE AND FUEL MATERIALS↗
DOE OSTI2025

Ion Traps and Packaging for Heterogenous Integration - Chimera

Microfabricated surface ion traps and silicon-based photonics are critical technologies for scaling quantum systems. Current ion trap architectures face scalability and integration challenges due to limitations in optical access, fabrication techniques, and material compatibility. State-of-the-art quantum computers and atomic clocks are investigating monolithic integration, which necessitates custom traps for each ion species and has not overcome the integration hurdles presented by merging these technologies. The Chimera (Ion Traps and Packaging for Heterogeneous Integration) project proposes a novel approach utilizing heterogeneous integration (HI) of ion traps and photonic circuits. This separation of components allows for flexibility in ion trap design and reduces fabrication compromises. The Chimera project specifically designed an ion trap to interface vertically with a separately fabricated waveguide chip and demonstrates the first steps to integrating them at the packaging level. The ion trap features a large area of removed silicon, allowing the photonics chip outputs closer to the ion trap, improving alignment and packaging processes. The alignment must be accurate to < 1 µm to ensure that the light from the waveguide can overlap with the trapping region. This fine alignment must also be maintained through an ultra-high vacuum bake, a critical step in preparing an ion trap experiment. By combining separate chips, we demonstrate a new path for scaling trapped ion technology that is less reliant on monolithic integration. We successfully fabricated a trap with a large area of oxide removed, resulting in a region thinned to about 40 µm, a key milestone toward successful integration.

42 ENGINEERING↗
DOE OSTI2023

Pulse shape measurements for neutron/gamma discrimination using the TOFPET2 ASIC

Many highly pixelated organic scintillator detection systems would benefit from independent readout of each scintillator pixel. Recent advances in Silicon Photomultiplier (SiPM) technology makes this goal feasible, however the data acquisition from potentially hundreds or thousands of channels requires a low-cost and compact solution. For pixelated neutron detection with organic scintillators, the capability to distinguish between neutron and gamma interactions using Pulse Shape Discrimination (PSD) is required along with pulse charge and time of arrival. The TOFPET2 ASIC from PETsys Electronics is a 64-channel readout chip providing pulse time and charge integration measurements from SiPMs, and is specifically designed for time-of-flight positron-emission tomography. Using an 8 × 8 array of 6 mm × 6 mm J-series SiPMs from SensL/OnSemi (ArrayJ-60035-64P-PCB), we have studied the energy and PSD performance of the TOFPET2 ASIC using a 4 × 4 array of 6 mm × 6 mm × 30 mm trans -Stilbene crystals from Inrad Optics and a custom SiPM routing board from PETsys Electronics. In conclusion, using a time-over-threshold method, we measure a maximum PSD figure-of-merit of approximately 1.2 at 478 keV (the Compton edge of 662 keV) for a J-series SiPM operating at an over-voltage of 3V.

47 OTHER INSTRUMENTATION↗
NASA NTRS2025

Erosion Behavior of Ti-hBN Multifunctional Coatings in A Custom-Made Planetary Test Rig at Extreme Lunar Temperatures

Spacecraft landings and takeoffs on the lunar surface, along with extreme temperature variations between day and night (-196 to 150° C), cause high-velocity dust impacts and erosion, resulting in the premature failure of structures. Ti/2 vol% hBN coatings were deposited using atmospheric (APS) and vacuum plasma spray (VPS) using cryo-milled powder feedstock to protect the structural components. The erosion performance of coatings at extreme lunar temperature regimes (-150 to 150° C) was evaluated in a custom-made planetary erosion test rig (PETR) at low (50 mph) and high impact velocities (250 mph). The mass loss of VPS coatings was reduced by 50% compared to the APS coatings and 40% compared to the Ti6Al4V substrate. The cryogenic temperature induces brittleness in the material, rendering it susceptible to extreme conditions of material loss. The particle impact-deformation behavior was captured using a high-speed camera to study the erosion mechanism. This analysis revealed chipping in substrates and brittle APS coatings, while particles rebounding and embedding were observed in VPS coatings. Energy calculations, aided by particle trajectory tracking from the high-speed camera, have conclusively shown that VPS coatings absorb 5–10% more energy than APS coatings during erosion tests. A modified erosion index was developed incorporating the fracture toughness and temperatures. New erosion models for brittle and ductile target materials are proposed for developing erosion-resistant material systems.

Abhijith Kunneparambil Sukumaran↗
DOE OSTI2023

Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis

The Software Defined Architectures (SODA) Synthesizer is an open-source compiler-based tool able to automatically generate domain-specialized systems targeting Application-Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) starting from high-level programming. SODA is composed of a frontend, SODA-OPT, which leverages the multilevel intermediate representation (MLIR) framework to interface with productive programming tools (e.g., machine learning frame-works), identify kernels suitable for acceleration, and perform high-level optimizations, and of a state-of-the-art high-level synthesis backend, Bambu from the PandA framework, to generate custom accelerators. One specific application of the SODA Synthesizer is the generation of accelerators to enable ultra-low latency inference and control on autonomous systems for scientific discovery (e.g., electron microscopes, sensors in particle accelerators, etc.). This paper provides an overview of the flow in the context of the generation of accelerators for edge processing to be integrated in transmission electron microscopy (TEM) devices, focusing on use cases from precision material synthesis. We show the tool in action with an example of design space exploration for inference on reconfigurable devices with a conventional deep neural network model (LeNet). Finally, we discuss the research directions and opportunities enabled by SODA in the area of autonomous control for scientific experimental workflows.

Castellana, Vito G.↗
DOE OSTI2014

High density, multi-range analog output Versa Module Europa board for control system applications

A new VMEDAC64, 12-bit 64 channel digital-to-analog converter, a Versa Module Europa (VME) module, features 64 analog voltage outputs with user selectable multiple ranges, has been developed for control system applications at Inter University Accelerator Centre. The FPGA (Field Programmable Gate Array) is the module's core, i.e., it implements the DAC control logic and complexity of VMEbus slave interface logic. The VMEbus slave interface and DAC control logic are completely designed and implemented on a single FPGA chip to achieve high density of 64 channels in a single width VME module and will reduce the module count in the control system applications, and hence will reduce the power consumption and cost of overall system. One of our early design goals was to develop the VME interface such that it can be easily integrated with the peripheral devices and satisfy the timing specifications of VME standard. The modular design of this module reduces the amount of time required to develop other custom modules for control system. The VME slave interface is written as a single component inside FPGA which will be used as a basic building block for any VMEbus interface project. The module offers multiple output voltage ranges depending upon the requirement. The output voltage range can be reduced or expanded by writing range selection bits in the control register. The module has programmable refresh rate and by default hold capacitors in the sample and hold circuit for each channel are charged periodically every 7.040 ms (i.e., update frequency 284 Hz). Each channel has software controlled output switch which disconnects analog output from the field. The modularity in the firmware design on FPGA makes the debugging very easy. On-board DC/DC converters are incorporated for isolated power supply for the analog section of the board.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing, a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study, which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating, and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RNI subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a hi ch data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
DOE OSTI2019

Narrow emitting red phosphors for improving pcLED efficacy

The objective of this Solid-State Lighting Advanced Technology R&D project was the development of a narrow-band red Eu 3+ -activated phosphor for blue-pumped, on-chip LED applications to improve pcLED efficacy up to 28%. We set out to develop novel and proprietary phosphor chemistry using standard inorganic chemistry methods to create phosphor materials with an efficient absorption of blue light (445-460 nm) and emission in a narrow bandwidth (less than 10 nm full-width-at-half-maximum observed) at target wavelengths in the red spectra. Furthermore, we intended that the narrow-band phosphors developed would be drop-in replacements for existing phosphor materials and will require no additional configuration of existing customer infrastructure, thereby enabling rapid adoption of these phosphors into LED lighting applications.

36 MATERIALS SCIENCE↗
NASA NTRS2004

Space Technology 5: Pathfinder for Future Micro-Sat Constellations

The Space Technology 5 (ST-5) Project, currently in the implementation phase, is part of the National Aeronautics and Space Administration (NASA) s New Millennium Program (NMP). ST-5 will consist of a constellation of three miniature satellites, each with mass less than 25 kg and size approximately 60 cm by 30 cm. ST-5 addresses technology challenges, as well as fabrication, assembly, test and operations strategies for future micro-satellite missions. ST-5 will be deployed into a highly eccentric, geo-transfer orbit (GTO). This will expose the spacecraft to a high radiation environment as well as provide a low level magnetic background. A three-month flight demonstration phase is planned to validate the technologies and demonstrate concepts for future missions. Each ST-5 spacecraft incorporates NMP competitively-selected breakthrough technologies. These include Cold Gas Micro-Thrusters for propulsion and attitude control, miniature X-band transponder for space-ground communications, Variable Emittance Coatings for dynamic thermal control, and CULPRiT ultra low power logic chip used for Reed-Solomon encoding. The ST-5 spacecraft itself is a technology that can be infused into future missions. It is a fully functional micro-spacecraft built within tight volume and mass constraints. It is built to withstand a high radiation environment, large thermal variations, and high launch loads. The spacecraft power system is low-power and low-voltage, and is designed to turn on after separation &om the launch vehicle. Some of the innovations that are included in the ST-5 design are a custom spacecraft deployment structure, magnetometer deployment boom, nutation damper, X-band antenna, miniature spinning sun sensor, solar array with triple junction solar cells, integral card cage assembly containing single card Command and Data Handling and Power System Electronics, miniature magnetometer, and lithium ion battery. ST-5 will demonstrate the ability of a micro satellite to perform research-quality science. Each ST-5 spacecraft will deploy a precision magnetometer to be used both for attitude determination and as a representative science instrument. The spacecraft has been developed with a low magnetic signature to avoid interference with the magnetometer. The spacecraft will be able to detect and respond autonomously to science events, i.e. significant changes in the magnetic field measurements. The three spacecraft will be a pathfinder for future constellation missions. They will be deployed to demonstrate an appropriate geometry for scientific measurements as a constellation. They will be operationally managed as a constellation, demonstrating automation and communication strategies that will be useful for future missions. The technologies and future mission concepts will be validated both on the ground and in space. Technologies will be validated on the ground by a combination of component level and system level testing of the flight hardware in a thermal vacuum environment. In flight, specific validation runs are planned for each of the technologies. Each validation run consists of one or more orbits with a specific validation objective. This paper will describe the ST-5 mission, and the applicability of the NMP technologies, spacecraft, and mission concepts to future missions. It will also discuss the validation approach for the ST-5 technologies and mission concepts.

Carlisle, Candace↗
NASA NTRS2008

Integrated Circuit Chip Improves Network Efficiency

Prior to 1999 and the development of SpaceWire, a standard for high-speed links for computer networks managed by the European Space Agency (ESA), there was no high-speed communications protocol for flight electronics. Onboard computers, processing units, and other electronics had to be designed for individual projects and then redesigned for subsequent projects, which increased development periods, costs, and risks. After adopting the SpaceWire protocol in 2000, NASA implemented the standard on the Swift mission, a gamma ray burst-alert telescope launched in November 2004. Scientists and developers on the James Webb Space Telescope further developed the network version of SpaceWire. In essence, SpaceWire enables more science missions at a lower cost, because it provides a standard interface between flight electronics components; new systems need not be custom built to accommodate individual missions, so electronics can be reused. New protocols are helping to standardize higher layers of computer communication. Goddard Space Flight Center improved on the ESA-developed SpaceWire by enabling standard protocols, which included defining quality of service and supporting plug-and-play capabilities. Goddard upgraded SpaceWire to make the routers more efficient and reliable, with features including redundant cables, simultaneous discrete broadcast pulses, prevention of network blockage, and improved verification. Redundant cables simplify management because the user does not need to worry about which connection is available, and simultaneous broadcast signals allow multiple users to broadcast low-latency side-band signal pulses across the network using the same resources for data communication. Additional features have been added to the SpaceWire switch to prevent network blockage so that more robust networks can be designed. Goddard s verification environment for the link-and-switch implementation continuously randomizes and tests different parts, constantly anticipating situations, which helps improve communications reliability. It has been tested in many different implementations for compatibility.

Source record↗
DOE OSTI2014

Combining nanocalorimetry and dynamic transmission electron microscopy for in situ characterization of materials processes under rapid heating and cooling

Nanocalorimetry is a chip-based thermal analysis technique capable of analyzing endothermic and exothermic reactions at very high heating and cooling rates. Here, we couple a nanocalorimeter with an extremely fast in situ microstructural characterization tool to identify the physical origin of rapid enthalpic signals. More specifically, we describe the development of a system to enable in situ nanocalorimetry experiments in the dynamic transmission electron microscope (DTEM), a time-resolved TEM capable of generating images and electron diffraction patterns with exposure times of 30 ns–500 ns. The full experimental system consists of a modified nanocalorimeter sensor, a custom-built in situ nanocalorimetry holder, a data acquisition system, and the DTEM itself, and is capable of thermodynamic and microstructural characterization of reactions over a range of heating rates (10{sup 2} K/s–10{sup 5} K/s) accessible by conventional (DC) nanocalorimetry. To establish its ability to capture synchronized calorimetric and microstructural data during rapid transformations, this work describes measurements on the melting of an aluminum thin film. We were able to identify the phase transformation in both the nanocalorimetry traces and in electron diffraction patterns taken by the DTEM. Potential applications for the newly developed system are described and future system improvements are discussed.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

3D-printed micro ion trap technology for quantum information applications

Trapped-ion applications, such as in quantum information processing1, precision measurements, optical clocks and mass spectrometry, rely on specialized high-performance ion traps. The last three of these applications typically use traditional machining to customize macroscopic 3D Paul traps, whereas quantum information processing experiments usually rely on photolithographic techniques to miniaturize the traps and meet scalability requirements. Using photolithography, however, it is challenging to fabricate the complex 3D electrode structures required for optimal confinement. Here, in this work, we demonstrate a high-resolution 3D printing technology based on two-photon polymerization (2PP) that is capable of fabricating large arrays of high-performance miniaturized 3D traps. We show that 3D-printed ion traps combine the advantages, such as strong radial confinement, of traditionally machined 3D traps with on-chip miniaturization. We trap calcium ions in 3D-printed ion traps with radial trap frequencies ranging from 2 MHz to 24 MHz. The tight confinement eases ion cooling requirements and allows us to implement high-quality Rabi oscillations with Doppler cooling only. Also, we demonstrate a two-qubit gate with a Bell-state fidelity of 0.978 ± 0.012. With 3D printing technology, the design freedom is greatly expanded without sacrificing scalability and precision, so that ion trap geometries can be optimized for higher performance and better functionality.

quantum information↗
NASA NTRS2015

Body of Knowledge (BOK) for Copper Wire Bonds

Copper wire bonds have replaced gold wire bonds in the majority of commercial semiconductor devices for the latest technology nodes. Although economics has been the driving mechanism to lower semiconductor packaging costs for a savings of about 20% by replacing gold wire bonds with copper, copper also has materials property advantages over gold. When compared to gold, copper has approximately: 25% lower electrical resistivity, 30% higher thermal conductivity, 75% higher tensile strength and 45% higher modulus of elasticity. Copper wire bonds on aluminum bond pads are also more mechanically robust over time and elevated temperature due to the slower intermetallic formation rate - approximately 1/100th that of the gold to aluminum intermetallic formation rate. However, there are significant tradeoffs with copper wire bonding - copper has twice the hardness of gold which results in a narrower bonding manufacturing process window and requires that the semiconductor companies design more mechanically rigid bonding pads to prevent cratering to both the bond pad and underlying chip structure. Furthermore, copper is significantly more prone to corrosion issues. The semiconductor packaging industry has responded to this corrosion concern by creating a palladium coated copper bonding wire, which is more corrosion resistant than pure copper bonding wire. Also, the selection of the device molding compound is critical because use of environmentally friendly green compounds can result in internal CTE (Coefficient of Thermal Expansion) mismatches with the copper wire bonds that can eventually lead to device failures during thermal cycling. Despite the difficult problems associated with the changeover to copper bonding wire, there are billions of copper wire bonded devices delivered annually to customers. It is noteworthy that Texas Instruments announced in October of 2014 that they are shipping microcircuits containing copper wire bonds for safety critical automotive applications. An evaluation of copper wire bond technology for applicability to spaceflight hardware may be warranted along with concurrently compiling a comprehensive understanding of the failure mechanisms involved with copper wire bonded semiconductor devices.

Body of Knowledge (BOK)↗