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At least 163 records · Page 9

Engineering Trade-off Considerations Regarding Design-for-Security, Design-for-Verification, and Design-for-Test

The United States government has identified that application specific integrated circuit (ASIC) and field programmable gate array (FPGA) hardware are at risk from a variety of adversary attacks. This finding affects system security and trust. Consequently, processes are being developed for system mitigation and countermeasure application. The scope of this tutorial pertains to potential vulnerabilities and countermeasures within the ASIC/FPGA design cycle. The presentation demonstrates how design practices can affect the risk for the adversary to: change circuitry, steal intellectual property, and listen to data operations. An important portion of the design cycle is assuring the design is working as specified or as expected. This is accomplished by exhaustive testing of the target design. Alternatively, it has been shown that well established schemes for test coverage enhancement (design-for-verification (DFV) and design-for-test (DFT)) can create conduits for adversary accessibility. As a result, it is essential to perform a trade between robust test coverage versus reliable design implementation. The goal of this tutorial is to explain the evolution of design practices; review adversary accessibility points due to DFV and DFT circuitry insertion (back door circuitry); and to describe common engineering trade-off considerations for test versus adversary threats.

Design for reliability (DFR)↗

Neo – Mars Adaptive Training Integrative Knowledge System (MATRIKS) to Improve Operational Performance and its Neural Basis for Spaceflight

With prolonged mission durations, spaceflight crews will become increasingly dependent on onboard technologies for knowledge acquisition and maintenance. It is expected that not all skills and knowledge required for these missions can be retained and retrieved based on pre-mission training alone. Limited and delayed communication will significantly constrain support from Mission Control and crews will increasingly rely on autonomous onboard technologies to successfully perform post-landing operations. With the present project we will target NASA’s particular interest in developing and assessing an adaptive, just-in-time countermeasure that will consolidate and improve skills that are most relevant to space flight operations. To achieve this aim, NASA established a Virtual NASA Specialized Center of Research (VNSCOR)referred to as “Mars Adaptive Training Integrative Knowledge System (MATRIKS)”, comprising the following three projects: (1) “Trinity–Multi-Environment Virtual Training for Long Duration Exploration Missions”, PI: A. Anderson (UC Boulder); (2) “Morpheus–A Haptic Sensory Supplement to Optimize In-Flight Adaptive Training for Human Control of Spacecraft Robotic Arms”, PI: S. Robinson, UC Davis); and the present project “Neo–Adaptive Training integrative knowledge System to Improve Operational Performance and its Neural Basis for Spaceflight” (UPenn, PI: A.C. Stahn). Neo leverages a validated workstation called 6DF that simulates a rendezvous and docking maneuver using real spacecraft flight dynamics. It is designed to (1) train and improve sensorimotor skills relevant for inflight and post-landing operational tasks; (2) feature an autonomous and adaptive training approach that does not rely on feedback from flight operations on the ground; (3) maximize the transfer of mission-relevant motor skills; (4) allow the assessment of the neural circuitry underlying the task; and (5) deliver the training in a motivating and meaningful way to astronauts. Neocomprises two overarching aims: First, we will identify the neural circuitry underlying spaceflight relevant tasks by performing a subset of the 6DFtaskduring functional magnetic resonance imaging (MRI)in a total of up to N=30 subjects with varying levels of 6DF training experience. Second, as part of the above-mentioned VNSCOR MATRIKS the proposed 6DF autonomous intelligent tutor system will be integrated in an additive manner with a haptic feedback intervention (Morpheus), and a multi-environment virtual trainer(Trinity).It is expected that Neo, Morpheus and Trinity mutually complement each other to facilitate an effective countermeasure tool to acquire and retain operational skills that are critical for exploration class missions. To assess the efficacy of this combined effort, the VNSCOR MATRIKS will collect data inN=16 crew members in one HERA campaign of 45 days duration with N=16 crew members(four missions with N=4 crew member seach).The primary goal is to identify changes in operational performance as assessed by NASA’s simulator of Canadarm2 operations, i.e., Robotic On-board Trainer (ROBoT-r) in response to MATRIKS. As part of Neo we will also identify if, and to what extent MATRIKS will promote transfer to general cognitive performance (Cognition battery), distinctive visuo-spatial tasks critical for telerobotic tasks (Spatial Cognition battery), and affect brain structural changes and the neural circuitry of key brain networks expected to be relevant for spaceflight-related performance. At the conclusion of the research, we will have defined and demonstrated the use of a neuroscience-based, adaptive training integrative knowledge system to potentially mitigate visuo-spatial and sensorimotor brain changes associated with prolonged isolation and confinement to reduce the likelihood or impact of potential decrements in human performance capabilities during long-duration space missions. The expected significance of this 4-year project relates to its relevance for facilitating effective countermeasure tools to acquire and retain operational skills that are critical for exploration class missions. This will support the development of necessary countermeasures and technologies in support of human space exploration, focusing on mitigating operational performance risks.

A C Stahn↗

UltraLiM: In-Memory Boolean Logic Architecture Using UltraRAM

Conventional computing architectures encounter ‘von Neumann’ and ‘memory wall’ bottlenecks which arise due to the back-and-forth data movement between the physically separate memory and processing units and the speed mismatch between them, respectively. These bottlenecks hurt both energy efficiency and the throughput of computing systems. To address these challenges, in-memory computing architectures have emerged as a promising alternative. They reduce the need for frequent data movement by executing different computing tasks inside the memory system. Here, we present UltraLiM, a logic-in-memory architecture using the UltraRAM-based memory system. UltraRAM holds the promise of developing a ‘universal memory’, overcoming the limitations of charge-based memories thanks to their non-volatile behavior with lower operating voltage. This work presents an in-memory computing architecture that integrates an UltraRAM-based memory array with a custom-designed peripheral circuitry. With this architecture, we can perform various in-memory Boolean logic operations (such as NOT, NAND, NOR, and XOR) in a single cycle. Leveraging the separate read-write paths in the UltraRAM-based memory array, we optimize read operations without encountering design conflicts. This optimization enhances the sense margin, enabling the use of simpler peripheral circuitry for in-memory logic operations.

Alam, Shamiul [University of Tennessee, Knoxville ↗

Shaft encoder presents digital output

Circuits that include compensation circuitry time a capacitance relative to a reference voltage so that a digital presentation occurs that is representative of the positional condition of the mechanical shaft being monitored. This circuitry may be employed in multiples to furnish binary encoding of a number of rotating devices simultaneously.

Hillis, D. A.↗

Logic realization of simple majority voting connectives

Redundant circuitry is added to computer network to eliminate incorrect output obtained due to a component failure, noise, or some other disturbance. This circuitry provides majority operation. Only NAND gates are employed, and the modules used are among the most popular microelectronic or integrated circuits presently in use.

Anderson, T. O.↗

Dual current readout for precision plating

Bistable amplifier prevents damage in the low range circuitry of a dual scale ammeter. It senses the current and switches automatically to the high range circuitry as the current rises above a preset level.

Iceland, W. F.↗

ASDTIC duty-cycle control for power converters

The application of analog signal to discrete interval converter (ASDTIC), a hybrid micromodule, two loop control subsystem, to a switching, stepdown dc to dc converter is described. The power circuitry, interface and ASDTIC subsystems used in this switching regulator were developed to exhibit the improved regulation, transient performance, regulator stability and freedom from the effects of variations in parts characteristics due to environmental changes and aging. ASDTIC can be used with other types of power circuits that use duty-cycle control techniques by simple changes in the interface subsystem. The circuitry and performance characteristics of a +10V dc switching converter as well as that of the ASDTIC micromodule are described. Realization of the ASDTIC hybrid micromodule has been accomplished with a hermetically sealed, beam-lead, bonded/deposited nichrome thin film resistors, discrete capacitors and integrated circuits on dilithic, glazed alumina substrates using 22 feed through terminals in an integrated package.

Lalli, V. R.↗

High-sensitivity receiver for CO2 laser communications

Wideband heterodyne receiver provides detection and demodulation of incident frequency modulated laser signal; search and acquisition circuitry to align two stations; tracking circuitry to maintain spatial alignment; and laser frequency monitor to frequency lock the transmit and local oscillator lasers.

Peyton, B.↗

ASDTIC duty-cycle control for power converters.

The application of analog signal to discrete interval converter (ASDTIC), a hybrid micromodule, two-loop control subsystem, to a switching, stepdown dc-to-dc converter is described. The power circuitry, interface and ASDTIC subsystems used in this switching regulator were developed to exhibit the improved regulation, transient performance, regulator stability, and freedom from the effects of variations in parts characteristics due to environmental changes and aging. The circuitry and performance characteristics of a +10-V dc switching converter as well as that of the ASDTIC micromodule are described. Realization of the ASDTIC hybrid micromodule has been accomplished with hermetically sealed, beam-lead, bonded/deposited nichrome thin film resistors, discrete capacitors, and integrated circuits on dilithic, glazed alumina substrates, using 22 feed through terminals in an integrated package.

Lalli, V. R.↗

Motion software for a synergistic six-degree-of-freedom motion base

Computer software for the conversion of fixed-base simulations into moving-base simulations utilizing a synergistic six-degree-of-freedom motion simulator has been developed. This software includes an actuator extension transformation, inverse actuator extension transformation, a centroid transformation, and a washout circuit. Particular emphasis is placed upon the washout circuitry as adapted to fit the synergistic motion simulator. The description of the washout circuitry and illustration by means of a sample flight emphasize that translational cue representation may be of good fidelity, but care in the selection of parameters is very necessary, particularly in regard to anomalous rotational cues.

Parrish, R. V.↗

Inverter ratio failure detector

A failure detector which detects the failure of a dc to ac inverter is disclosed. The inverter under failureless conditions is characterized by a known linear relationship of its input and output voltages and by a known linear relationship of its input and output currents. The detector includes circuitry which is responsive to the detector's input and output voltages and which provides a failure-indicating signal only when the monitored output voltage is less by a selected factor, than the expected output voltage for the monitored input voltage, based on the known voltages' relationship. Similarly, the detector includes circuitry which is responsive to the input and output currents and provides a failure-indicating signal only when the input current exceeds by a selected factor the expected input current for the monitored output current based on the known currents' relationship.

Wagner, A. P.↗

Automatic quadrature control and measuring system

A quadrature component cancellation and measuring system comprising a detection system for detecting the quadrature component from a primary signal, including reference circuitry to define the phase of the quadrature component for detection is described. A Raysistor optical coupling control device connects an output from the detection system to a circuit driven by a signal based upon the primary signal. Combining circuitry connects the primary signal and the circuit controlled by the Raysistor device to subtract quadrature components. A known current through the optically sensitive element produces a signal defining the magnitude of the quadrature component.

Hamlet, J. F.↗

A 30-cm thruster power processor test console

The development of a high performance ion propulsion system composed of an ion thruster and its associated power processing equipment, dictates the establishment of a mutually compatible set of electrical characteristics. A 30-cm thruster power processing console has been developed which utilizes power and control circuitry applicable to flight hardware designs, incorporates interface circuitry for optional direct computer control, and has self-contained instrumentation for assessing steady-state and dynamic system behavior. This paper discusses the console's design, utility, performance, and the potential impact of this development effort on future hardware designs.

Herron, B. G.↗

Life support subsystem monitoring instrumentation

The recognition of the need for instrumentation in manned spacecraft life-support subsystems has increased significantly over the past several years. Of the required control and monitoring instrumentation, this paper will focus on the monitoring instrumentation as applied to life-support subsystems. The initial approach used independent sensors, independent sensor signal conditioning circuitry, and independent logic circuitry to provide shutdown protection only. This monitoring system was replaced with a coordinated series of printed circuit cards, each of which contains all the electronics to service one sensor and provide performance trend information, fault detection and isolation information, and shutdown protection. Finally, a review of sensor and instrumentation problems is presented, and the requirement for sensors with built-in signal conditioning and provisions for in situ calibration is discussed.

Powell, J. D.↗

Design guidelines for advanced LSI microcircuit packaging using thick film multilayer technology

Ceramic multilayer circuitry results from the sequential build-up of two or more layers of pre-determined conductive interconnections separated by dielectric layers and fired at an elevated temperature to form a solidly fused structure. The resultant ceramic interconnect matrix is used as a base to mount active and passive devices and provide the necessary electrical interconnection to accomplish the desired electrical circuit. Many methods are known for developing multilevel conductor mechanisms such as multilayer printed circuits, welded wire matrices, flexible copper tape conductors, and thin and thick-film ceramic multilayers. Each method can be considered as a specialized field with each possessing its own particular set of benefits and problems. This design guide restricts itself to the art of design, fabrication and assembly of ceramic multilayer circuitry and the reliability of the end product.

Peckinpaugh, C. J.↗

Random pulse generator

An exemplary embodiment of the present invention provides a source of random width and random spaced rectangular voltage pulses whose mean or average frequency of operation is controllable within prescribed limits of about 10 hertz to 1 megahertz. A pair of thin-film metal resistors are used to provide a differential white noise voltage pulse source. Pulse shaping and amplification circuitry provide relatively short duration pulses of constant amplitude which are applied to anti-bounce logic circuitry to prevent ringing effects. The pulse outputs from the anti-bounce circuits are then used to control two one-shot multivibrators whose output comprises the random length and random spaced rectangular pulses. Means are provided for monitoring, calibrating and evaluating the relative randomness of the generator.

Lindsey, R. S., Jr.↗