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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 163 records · Page 9
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Photonic integration for UV to IR applications

Photonic integration opens the potential to reduce size, power, and cost of applications normally relegated to table- and rack-sized systems. Today, a wide range of precision, high-end, ultra-sensitive, communication and computation, and measurement and scientific applications, including atomic clocks, quantum communications, processing, and high resolution spectroscopy, are ready to make the leap from the lab to the chip. However, many of these applications operate at wavelengths not accessible to the silicon on insulator-based silicon photonics integration platform due to absorption, power handling, unwanted nonlinearities, and other factors. Next generation photonic integration will require ultra-wideband photonic circuit platforms that scale from the ultraviolet to the infrared and that offer a rich set of linear and nonlinear circuit functions as well as low loss and high power handling capabilities. This article provides an assessment of the field in ultra-wideband photonic waveguides to bring power efficient, ultra-high performance systems to the chip-scale and enable compact transformative precision measurement, signal processing, computation, and communication techniques.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2021

Time-stamping and counting of single photons using fast camera

I will discuss fast optical cameras based on the back-illuminated silicon sensor and Timepix3 ASIC. The sensor has high quantum efficiency, and the chip provides nanosecond scale time resolution and data-driven readout with 80Mpix/sec bandwidth. The intensified version of the camera is single photon sensitive and since recently has been used for registration of single photons in a variety of quantum information science and quantum imaging experiments as well as for other applications. We briefly review the camera and describe recent experiments with a Hong-Ou-Mandel interferometer to characterize its photon counting capabilities.

79 ASTRONOMY AND ASTROPHYSICS↗
DOE OSTI2025

Integrated photonic Galton board and its application for photon counting

The Galton board is a desktop probability machine traditionally used to visualize the principles of statistical physics from classical particles. Here, we demonstrate a photonic Galton board that enables on-chip observation of statistics from single-photon interference. The photonic Galton board consists of a directional coupler matrix terminated by an array of superconducting nanowire detectors to provide spatiotemporal resolution. This design also allows for photon-number-resolving capability, making it suitable for high-speed photon counting. Our results demonstrate the compatibility between single-photon detector array and photonic integrated circuits, paving the way for implementing on-chip large-scale quantum optics experiments and photonic quantum computing.

Qin, Hezheng (ORCID:0009000139348800)↗
DOE OSTI2024

Mode-multiplexed photonic integrated vector dot-product core from inverse design

Photonic computing has the potential to harness the full degrees of freedom (DOFs) of the light field, including the wavelength, spatial mode, spatial location, phase quadrature, and polarization, to achieve a higher level of computing parallelism and scalability than digital electronic processors. While multiplexing using the wavelength and other DOFs can be readily integrated on silicon photonics platforms with compact footprints, conventional mode-division multiplexed (MDM) photonic designs occupy areas exceeding tens to hundreds of microns for a few spatial modes, significantly limiting their scalability. Here, we utilize inverse design to demonstrate an ultracompact photonic computing core that calculates vector dot products based on MDM coherent mixing. Our dot-product core integrates the functionalities of two-mode multiplexers and one multimode coherent mixer within a nominal footprint of 5 μm x 3 μm . We have experimentally demonstrated computing examples on the fabricated dot-product core, including complex number multiplication and motion estimation using optical flow. The compact dot-product core design enables large-scale on-chip integration in a parallel photonic computing primitive cluster for high-throughput scientific computing and computer vision tasks.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Coherent Wavelength Switched Co-Packaged Optics to Disrupt Datacenters/HPC (AKA "QRock") (Final Report)

This project resulted in multiple first-of-a-kind demonstrations, including two generations of transmitters, a receiver, and a complete coherent link. The transmitter architecture, based on EAMs to generate QPSK modulation was first demonstrated in InP, which has limitations for scaling up to chips with multiple channels for full WDM architectures, and implementing the densities and level of integration needed to implement co-packaging with electronics. Our work resulted in the first demonstration of this architecture on a Si platform compatible with copackaging, and our working prototypes illustrated the potential of the approach. The link demonstration was also the first coherent optical link realized in a multi-micron waveguide platform. For the transmitters, integrating efficient III-V EAM devices into the large waveguide Si platform simultaneously enables significant reduction in driver power consumption while minimizing optical losses in routing and fiber coupling. On the receiver side, optical coupling and propagation losses are also minimized in the multi-micron platform, reducing required laser optical power which improves link energy efficiency. The measurement results presented in the final report demonstrate that we achieved the speed objectives for the program (112Gb/s: 56Gbaud QPSK), albeit at a higher BER than targeted. The report provides assessments of the low-powercoherent link architecture and associated components developed under the program from both technological and commercial viewpoints.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1979

Design, processing and testing of LSI arrays, hybrid microelectronics task

Mathematical cost models previously developed for hybrid microelectronic subsystems were refined and expanded. Rework terms related to substrate fabrication, nonrecurring developmental and manufacturing operations, and prototype production are included. Sample computer programs were written to demonstrate hybrid microelectric applications of these cost models. Computer programs were generated to calculate and analyze values for the total microelectronics costs. Large scale integrated (LST) chips utilizing tape chip carrier technology were studied. The feasibility of interconnecting arrays of LSU chips utilizing tape chip carrier and semiautomatic wire bonding technology was demonstrated.

Himmel, R. P.↗
NASA NTRS1986

Systolic VLSI Reed-Solomon Decoder

Decoder for digital communications provides high-speed, pipelined ReedSolomon (RS) error-correction decoding of data streams. Principal new feature of proposed decoder is modification of Euclid greatest-common-divisor algorithm to avoid need for time-consuming computations of inverse of certain Galois-field quantities. Decoder architecture suitable for implementation on very-large-scale integrated (VLSI) chips with negative-channel metaloxide/silicon circuitry.

Shao, H. M.↗
NASA NTRS1984

VLSI Architectures for the Multiplication of Integers Modulo a Fermat Number

Multiplication is central in the implementation of Fermat number transforms and other residue number algorithms. There is need for a good multiplication algorithm that can be realized easily on a very large scale integration (VLSI) chip. The Leibowitz multiplier is modified to realize multiplication in the ring of integers modulo a Fermat number. This new algorithm requires only a sequence of cyclic shifts and additions. The designs developed for this new multiplier are regular, simple, expandable, and, therefore, suitable for VLSI implementation.

Chang, J. J.↗
NASA NTRS1986

Stanford Hardware Development Program

Architectures for high performance, digital signal processing, particularly for high resolution, wide band spectrum analysis were developed. These developments are intended to provide instrumentation for NASA's Search for Extraterrestrial Intelligence (SETI) program. The real time signal processing is both formal and experimental. The efficient organization and optimal scheduling of signal processing algorithms were investigated. The work is complemented by efforts in processor architecture design and implementation. A high resolution, multichannel spectrometer that incorporates special purpose microcoded signal processors is being tested. A general purpose signal processor for the data from the multichannel spectrometer was designed to function as the processing element in a highly concurrent machine. The processor performance required for the spectrometer is in the range of 1000 to 10,000 million instructions per second (MIPS). Multiple node processor configurations, where each node performs at 100 MIPS, are sought. The nodes are microprogrammable and are interconnected through a network with high bandwidth for neighboring nodes, and medium bandwidth for nodes at larger distance. The implementation of both the current mutlichannel spectrometer and the signal processor as Very Large Scale Integration CMOS chip sets was commenced.

Peterson, A.↗
NASA NTRS1987

Survey of current correlators and applications

With this summary an attempt is made to contact as many users as possible so as to provide summary data on correlation systems, both in use and as planned. Data on currently available very large scale integration (VLSI) chips and complete systems are included. Also, several planned correlator systems are described and summarized in tabular form. Finally, a description is given of the work being done in the Communications Systems Research Section on VLSI correlator chips and complete correlator systems.

Lahmeyer, C. R.↗
NASA NTRS1989

Wiring Viterbi decoders (splitting deBruijn graphs)

A new Viterbi decoder, capable of decoding convolutional codes with constraint lengths up to 15, is under development for the Deep Space Network (DSN). A key feature of this decoder is a two-level partitioning of the Viterbi state diagram into identical subgraphs. The larger subgraphs correspond to circuit boards, while the smaller subgraphs correspond to Very Large Scale Integration (VLSI) chips. The full decoder is built from identical boards, which in turn are built from identical chips. The resulting system is modular and hierarchical. The decoder is easy to implement, test, and repair because it uses a single VLSI chip design and a single board design. The partitioning is completely general in the sense that an appropriate number of boards or chips may be wired together to implement a Viterbi decoder of any size greater than or equal to the size of the module.

Collins, O.↗
NASA NTRS1990

A VLSI decomposition of the deBruijn graph

A new Viterbi decoder for convolutional codes with constraint lengths up to 15, called the Big Viterbi Decoder, is under development for the Deep Space Network. It will be demonstrated by decoding data from the Galileo spacecraft, which has a rate 1/4, constraint-length 15 convolutional encoder on board. Here, the mathematical theory underlying the design of the very-large-scale-integrated (VLSI) chips that are being used to build this decoder is explained. The deBruijn graph B sub n describes the topology of a fully parallel, rate 1/v, constraint length n+2 Viterbi decoder, and it is shown that B sub n can be built by appropriately wiring together (i.e., connecting together with extra edges) many isomorphic copies of a fixed graph called a B sub n building block. The efficiency of such a building block is defined as the fraction of the edges in B sub n that are present in the copies of the building block. It is shown, among other things, that for any alpha less than 1, there exists a graph G which is a B sub n building block of efficiency greater than alpha for all sufficiently large n. These results are illustrated by describing a special hierarchical family of deBruijn building blocks, which has led to the design of the gate-array chips being used in the Big Viterbi Decoder.

Collins, O.↗
NASA NTRS1991

Coding gains and error rates from the Big Viterbi Decoder

A prototype hardware Big Viterbi Decoder (BVD) was completed for an experiment with the Galileo Spacecraft. Searches for new convolutional codes, studies of Viterbi decoder hardware designs and architectures, mathematical formulations, and decompositions of the deBruijn graph into identical and hierarchical subgraphs, and very large scale integration (VLSI) chip design are just a few examples of tasks completed for this project. The BVD bit error rates (BER), measured from hardware and software simulations, are plotted as a function of bit signal to noise ratio E sub b/N sub 0 on the additive white Gaussian noise channel. Using the constraint length 15, rate 1/4, experimental convolutional code for the Galileo mission, the BVD gains 1.5 dB over the NASA standard (7,1/2) Maximum Likelihood Convolution Decoder (MCD) at a BER of 0.005. At this BER, the same gain results when the (255,233) NASA standard Reed-Solomon decoder is used, which yields a word error rate of 2.1 x 10(exp -8) and a BER of 1.4 x 10(exp -9). The (15, 1/6) code to be used by the Cometary Rendezvous Asteroid Flyby (CRAF)/Cassini Missions yields 1.7 dB of coding gain. These gains are measured with respect to symbols input to the BVD and increase with decreasing BER. Also, 8-bit input symbol quantization makes the BVD resistant to demodulated signal-level variations which may cause higher bandwidth than the NASA (7,1/2) code, these gains are offset by about 0.1 dB of expected additional receiver losses. Coding gains of several decibels are possible by compressing all spacecraft data.

Onyszchuk, I. M.↗
NASA NTRS1992

Deimos: A reddish, D-type asteroid spectrum

We have obtained high quality CCD spectra of Deimos from 0.5 to 1.0 microns at a spectral resolution of 15 A. The spectra are remarkably red, similar to the spectra of D type asteroids rather than those of carbonaceous chondrites or C type asteroids. During the 1988 opposition of Mars, we obtained new CCD spectra of its outer satellite, Deimos. The data were obtained over a 2 1/2 hour period on the night of 9 Oct., using the 1.54 meter Catalina telescope and the LPL long-slit CCD spectrometer. From 0.5 to 1.1 microns, the spectrum is dispersed across an 800 x 800 Texas Instruments CCD chip at a scale of 7.21 A per pixel for an effective lambda/delta(lambda) approximately equals 500. The primary observational difficulty in ground based spectroscopy of Deimos was its proximity to Mars. To minimize scattered light from Mars, Deimos was observed near greatest elongation. The spectrograph slit was narrowed to 2.5 arcseconds, slightly larger than the seeing disk. An apodizing mask at the re-imaged telescope primary, to remove the diffraction cross of Mars light caused by the telescope's secondary mirror mount. Residual scattered light was modeled and removed in data reduction. Solar analog stars BS560, BS2007, and BS8931 were observed to allow removal of telluric absorptions. The resulting spectrum is plotted with other data.

Grundy, William M.↗
NASA NTRS1993

Mixed voltage VLSI design

A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.

Panwar, Ramesh↗
NASA NTRS1984

LANDSAT 4 investigation of Thematic Mapper and Multispectral Scanner applications

A comparison of methods for selecting optimum TM band combinations for visual interpretation of data are examined. Two statistical methods and visual interpretation by experienced photointerpreters are compared using photographic chips of 1:250,000 scale prints and the digital equivalent of the chips. A mosaic of TM data of the Great Salt Lake area of Utah was done. The filtering process was reviewed since the results were not satisfactory.

Lauer, D. T.↗
DOE OSTI2021

SHarD: A beam dynamics simulation code for dielectric laser accelerators based on spatial harmonic field expansion

In order to demonstrate acceleration of electrons to relativistic scales by an on chip dielectric laser accelerator (DLA), a ponderomotive focusing scheme capable of capturing and transporting electrons through nanometer-scale apertures over extended interaction lengths has been proposed. Here we present a Matlab-based numerical code (SHarD) utilizing a spatial harmonic expansion of the fields within the dielectric structure to simulate the evolution of the beam phase space distribution in this scheme. The code can be used to optimize key-parameters for the accelerator performance such as the final energy, transverse spot size evolution and total number of electrons accelerated through currently fabricated structures. Eventually, the simulation model will be applied to inform the phase mask profile to be added to a pulse front tilt drive laser pulse using a liquid crystal mask in the experimental setup being assembled at UCLA Pegasus Laboratory.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

Dual-scale folding in cutting of commercially pure aluminum alloys

We examine a, hitherto, little-studied and curious machining chip morphology, with tell-tale signs of folding at two different length scales, that is common in cutting of certain ductile and highly strain-hardening metals like soft aluminum alloys, tantalum and niobium. This chip morphology does not appear in the usual catalogues of common chip types. The mechanics of formation of the “dual-scale folded chip” is studied in model material systems of commercially pure aluminum alloys (AA 1100 and AA 8040), that prominently exhibit this chip morphology. The flow, folding and associated plastic instabilities are investigated using micro/macro structure observations of the chip in a plane-strain cutting framework, with high-speed in situ imaging and image analysis of material flow; and force measurements. The smaller-scale folding is shown to develop in the primary deformation zone while the larger-scale folding occurs as the chip traverses the rake face of the tool. The resulting chip is composed of irregularly-spaced large folds, superimposed onto which are the quasi periodic small folds. The representative wavelengths of the two folds differ on average by an order of magnitude, 0.1 mm vs. 2 mm. The observations reveal a direct coupling between the material flow and chip morphology, and how specific attributes of the dual-scale folded chip arise from the flow mechanism. Plastic buckling is found to play a key role in the folding at both length scales. The small-scale folds are characteristic of a sinuous plastic flow mode, while the large-scale folding is characterized by buckling and stick-slip along the tool rake face, triggered by adhesive pinning of the chip to the tool. Important consequences of the dualscale folding are very large cutting forces, and force oscillations of large amplitude, despite the alloys being very soft, only ~ 25 HV. Here, the dual-scale folding is why many of these alloys are classified as “gummy” to machine. Since the dual-scale folded chip is associated with large cutting forces and poor surface quality, there is much to be gained by disrupting this flow type in practical machining applications. Methods for controlling the folding to improve machining performance with the gummy alloys are briefly discussed.

36 MATERIALS SCIENCE↗