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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 163 records · Page 9
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Readout for Calorimetry at Future Colliders: A Snowmass 2021 White Paper

Calorimeters will provide critical measurements at future collider detectors. As the traditional challenge of high dynamic range, high precision, and high readout rates for signal amplitudes is compounded by increasing granularity and precision timing the readout systems will become increasingly complex. This white paper reviews the challenges and opportunities in calorimeter readout at future collider detectors.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

A Cryogenic Readout IC with 100 KSPS in-Pixel ADC for Skipper CCD-in-CMOS Sensors

The Skipper CCD-in-CMOS Parallel Read-Out Circuit (SPROCKET) is a mixed-signal front-end design for the readout of Skipper CCD-in-CMOS image sensors. SPROCKET is fabricated in a 65 nm CMOS process and each pixel occupies a 50$\mu$m $\times$ 50$\mu$m footprint. SPROCKET is intended to be heterogeneously integrated with a Skipper-in-CMOS sensor array, such that one readout pixel is connected to a multiplexed array of nine Skipper-in-CMOS pixels to enable massively parallel readout. The front-end includes a variable gain preamplifier, a correlated double sampling circuit, and a 10-bit serial successive approximation register (SAR) ADC. The circuit achieves a sample rate of 100 ksps with 0.48 $\mathrm{e^-_{rms}}$ equivalent noise at the input to the ADC. SPROCKET achieves a maximum dynamic range of 9,000 $e^-$ at the lowest gain setting (or 900 $e^-$ at the lowest noise setting). The circuit operates at 100 Kelvin with a power consumption of 40 $\mu W$ per pixel. A SPROCKET test chip was submitted in September 2022, and test results will be presented at the conference.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Optimization and Performance Characterization of the Second Generation Fermilab Constant Fraction Discriminator Readout ASIC

We present the optimization and performance characterization of the second-generation Fermilab Constant Fraction Discriminator ASIC (FCFD), designed for the readout of AC-coupled low-gain avalanche detector (LGAD) strip-sensors. The FCFD is explicitly engineered to be insensitive to signal-amplitude variations, thereby removing the need for time-walk correction that is required in other LGAD time-stamping readout ASICs. This updated version, referred to as FCFD1.1, incorporates several enhancements over the first iteration to address key challenges in AC-coupled LGAD front-end design. We outline the primary readout-ASIC design considerations for these applications, describe the methodology used to evaluate critical sensor and system parameters, and summarize the additionally implemented features. Performance measurements using injected charge signals and minimum-ionizing particles in test-beams demonstrate a time resolution of approximately 40 ps and a position resolution of roughly \SI{15}{\micro\meter} when tested with beam particles uniformly over the active area of the sensor.

Apresyan, Artur [Fermilab] (ORCID:0000000261860130↗
DOE OSTI2025

SALSA: a new versatile readout chip for MPGD detectors

The SALSA chip is a future readout ASIC foreseen for the MPGD detectors, developed in the framework of the EIC collider project, to equip the MPGD trackers of the EPIC experiment. It is designed to be versatile, to be adapted to other usages of MPGD detectors like TPC or photon detectors. It integrates a frontend block and an ADC for each of the 64 channels, associated to a configurable DSP processor meant to correct data and reduce the raw data flux to limit the output bandwidth. It will be compatible with the continuous readout foreseen for the EPIC DAQ, but will also work in a triggered environment. Several prototypes are already produced in order to qualify the different blocks of the chip, in particular the frontend, the ADC and the clock generation. The next 32-channel prototype is currently under development and is planed to be produced in 2025. In conclusion, the final prototype will be produced and tested from 2026 for a production of the SALSA chip at the horizon of 2027.

Data processing↗
DOE OSTI2018

Development of a Crosstalk Suppression Algorithm for KID Readout

The GroundBIRD telescope aims to detect B-mode polarization of the cosmic microwave background radiation using the kinetic inductance detector array as a polarimeter. For the readout of the signal from detector array, we have developed a frequency division multiplexing readout system based on a digital down converter method. These techniques in general have the leakage problems caused by the crosstalks. The window function was applied in the field programmable gate arrays to mitigate the effect of these problems and tested it in algorithm level.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

Simons Observatory Microwave SQUID Multiplexing Readout: Cryogenic RF Amplifier and Coaxial Chain Design

The Simons Observatory (SO) is an upcoming polarization-sensitive cosmic microwave background experiment on the Cerro Toco Plateau (Chile) with large overlap with other optical and infrared surveys (e.g., DESI, LSST, HSC). To enable the readout of O(10,000) detectors in each of the four telescopes of SO, we will employ the microwave SQUID multiplexing technology. With a targeted multiplexing factor of O(1000), microwave SQUID multiplexing has never been deployed on the scale needed for SO. Here we present the design of the cryogenic coaxial cable and RF component chain that connects room temperature readout electronics to superconducting resonators that are coupled to transition edge sensor bolometers operating at sub-Kelvin temperatures. We describe design considerations including cryogenic RF component selection, system linearity, noise, and thermal power dissipation.

47 OTHER INSTRUMENTATION↗
DOE OSTI2019

Design of a readout circuit incorporating a 12-bit analog-to-digital converter for cooled infrared focal plane array

The infrared focal plane array (IRFPA) is gradually becoming more systematic. In order to enhance the signal processing capabilities, analog-to-digital converters (ADC) integrated into the readout integrated circuit (ROIC) is an important development trend. However, the cryogenic effects of MOSFET devices will affect the conversion accuracy of the ADC at 77 K. In this paper, the main parameters of MOSFET are extracted at 77 K in 0.18 μm CMOS process, and a cryogenic model is established. Based on this, a digital ROIC is designed, which integrates a 12-bit single-slope integral ADC in pixel unit. By applying continuous integral ramp generator and mixed-voltage comparator, a high-linearity and low-power consumption single-slope ADC is realized for the cooled readout circuit. The measured dynamic effective number of bits of the ADC at 77 K is 10.92 bits, the static no-missing code resolution reaches 11.99 bits, the maximum differential nonlinear |DNL| < 1LSB and maximum integral nonlinear |INL| < 1LSB. This paper realizes the design of a digital ROIC for IRFPA and improves the simulation accuracy at 77 K.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2018

A GEM readout with radial zigzag strips and linear charge-sharing response

Here, we study the position sensitivity of radial zigzag strips intended to read out large GEM detectors for tracking at future experiments. Zigzag strips can cover a readout area with fewer strips than regular straight strips while maintaining good spatial resolution. Consequently, they can reduce the number of required electronic channels and related cost for large-area GEM detector systems. A non-linear relation between incident particle position and hit position measured from charge sharing among zigzag strips was observed in a previous study. We significantly reduce this non-linearity by improving the interleaving of adjacent physical zigzag strips. Zigzag readout structures are implemented on PCBs and on a flexible foil and are tested using a 10 cm × 10 cm triple-GEM detector scanned with a strongly collimated X-ray gun on a 2D motorized stage. Lastly, angular resolutions of 60–84 μrad are achieved with a 1.37 mrad angular strip pitch at a radius of 784 mm. On a linear scale this corresponds to resolutions below 100 μm.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2018

Test results and prospects for RD53A, a large scale 65 nm CMOS chip for pixel readout at the HL-LHC

The CERN RD53 collaboration was founded to tackle the extraordinary challenges associated with the design of pixel readout chips for the innermost layers of particle trackers at future high energy physics experiments. Around 20 institutions are involved in the collaboration, which has the support of both ATLAS and CMS experiments. The goals of the collaboration include the comprehensive understanding of radiation effects in the 65 nm technology, the development of tools and methodology to efficiently design large complex mixed signal chips and, ultimately, the development of a full size readout chip featuring a 400 × 400 pixel array with 50μm pitch. In August 2017, the collaboration submitted the large scale chip RD53A, integrating a matrix of 400 × 192 pixels and embodying three different analog front-end designs. Here, this work discusses the characteristic of the RD53A chip, with some emphasis on the analog processors, and presents the first test results on the pixel array.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2019

Compact readout of large CLYC scintillators with silicon photomultipler arrays

Compact readout of a large (5 x 5 x 5 cm 3) CLYC scintillator was demonstrated with a 8 x 8 array of 6mm silicon photomultipliers (SiPMs, specifically, a SensL ArrayJ-60035-64P) and an optimized amplification and summing circuit. Read out by the SiPM array, the crystal yielded an energy resolution of 5.5% at 662 keV and a figure of merit of 3.5, equivalent to the performance achieved with a 3-inch Hamamatsu R6233-100 PMT. To reduce channel count and avoid individual amplification of each SiPM in the array, the standard outputs of 16 SiPMs were passively summed then amplified. A current feedback amplifier was used for each channel to provide the required fast response time. The four amplified channels were then passively summed resulting in a single signal channel. A custom laboratory setup, based on the PSD8C ASIC, was used to capture the output and provide time-gated integration for PSD computation. We conclude the compact volume, low bias voltage, and reduced mass of the SiPM array readout are desirable for space and national security applications.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2014

The electronics readout and data acquisition system of the KM3NeT neutrino telescope node

The KM3NeT neutrino telescope will be composed by tens of thousands of glass spheres, called Digital Optical Module (DOM), each of them containing 31 PMTs of small photocathode area (3'). The readout and data acquisition system of KM3NeT have to collect, treat and send to shore, in an economic way, the enormous amount of data produced by the photomultipliers and at the same time to provide time synchronization between each DOM at the level of 1 ns. It is described in the present article the Central Logic Board, that integrates the Time to Digital Converters and the White Rabbit protocol used for the DOM synchronization in a transparent way, the Power Board used in the DOM, the PMT base to readout the photomultipliers and the respective collecting boards, the so called Octopus Board.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2015

A fast and reliable readout method for quantitative analysis of surface-enhanced Raman scattering nanoprobes on chip surface

Surface-enhanced Raman scattering techniques have been widely used for bioanalysis due to its high sensitivity and multiplex capacity. However, the point-scanning method using a micro-Raman system, which is the most common method in the literature, has a disadvantage of extremely long measurement time for on-chip immunoassay adopting a large chip area of approximately 1-mm scale and confocal beam point of ca. 1-μm size. Alternative methods such as sampled spot scan with high confocality and large-area scan method with enlarged field of view and low confocality have been utilized in order to minimize the measurement time practically. In this study, we analyzed the two methods in respect of signal-to-noise ratio and sampling-led signal fluctuations to obtain insights into a fast and reliable readout strategy. On this basis, we proposed a methodology for fast and reliable quantitative measurement of the whole chip area. The proposed method adopted a raster scan covering a full area of 100 μm × 100 μm region as a proof-of-concept experiment while accumulating signals in the CCD detector for single spectrum per frame. One single scan with 10 s over 100 μm × 100 μm area yielded much higher sensitivity compared to sampled spot scanning measurements and no signal fluctuations attributed to sampled spot scan. This readout method is able to serve as one of key technologies that will bring quantitative multiplexed detection and analysis into practice.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2015

A near-infrared 64-pixel superconducting nanowire single photon detector array with integrated multiplexed readout

We demonstrate a 64-pixel free-space-coupled array of superconducting nanowire single photon detectors optimized for high detection efficiency in the near-infrared range. An integrated, readily scalable, multiplexed readout scheme is employed to reduce the number of readout lines to 16. The cryogenic, optical, and electronic packaging to read out the array as well as characterization measurements are discussed.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2016

A frequency and sensitivity tunable microresonator array for high-speed quantum processor readout

Superconducting microresonators have been successfully utilized as detection elements for a wide variety of applications. With multiplexing factors exceeding 1000 detectors per transmission line, they are the most scalable low-temperature detector technology demonstrated to date. For high-throughput applications, fewer detectors can be coupled to a single wire but utilize a larger per-detector bandwidth. For all existing designs, fluctuations in fabrication tolerances result in a non-uniform shift in resonance frequency and sensitivity, which ultimately limits the efficiency of bandwidth utilization. Here, we present the design, implementation, and initial characterization of a superconducting microresonator readout integrating two tunable inductances per detector. We demonstrate that these tuning elements provide independent control of both the detector frequency and sensitivity, allowing us to maximize the transmission line bandwidth utilization. Finally, we discuss the integration of these detectors in a multilayer fabrication stack for high-speed readout of the D-Wave quantum processor, highlighting the use of control and routing circuitry composed of single-flux-quantum loops to minimize the number of control wires at the lowest temperature stage.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2016

A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run-2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources. Together with auxiliary memories, all of these components form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for high speed input and output fiberoptic links and TTC allowed the full system of 320 input links from the 32 chambers to be processed by 6 COBs in one ATCA shelf. The full system was installed in September 2014. In conclusion, we will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning for LHC Run 2.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

An FPGA-based readout chip emulator for the CMS ETL detector upgrade

Here, we present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digital functions of four Endcap Layer Readout Chips (ETROCs). Based on the actual ETROC design, the firmware is implemented and verified. The emulator board is being used for the ETROC digital design verification and system development.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

The SparkPix-S ASIC for the sparsified readout of 1 MHz frame-rate X-ray cameras at LCLS-II: pixel design and simulation results

Exploiting the “sparse” nature of the information in XPCS (X-ray Photon Correlation Spectroscopy) and XSVS (Speckle Visibility Spectroscopy) experiments, we present the SparkPix-S, a 3-sides buttable Application Specific Integrated Circuit (ASIC) based on a sparsified readout strategy for large-format hybrid detectors. The SparkPix-S architecture, based on the successful ePix family, will be composed as follows: a front-end 2-D matrix of 384×352 square pixels with 50 µm pitch is arranged to match the dimensions of a PIN Si-sensor matrix; charge readout, signal shaping and amplitude discrimination is performed at pixel-level, by means of a low-power (<18 µW) analog processor, which, in case of an event, negotiates access to an analog bus placed every other column; on the chip periphery (balcony), the information on each bus is digitized by an array of successive approximation analog-to-digital converters (SAR-ADCs) running at 10 Msps; on the digital back-end the global logic will generate the output data stream using low-voltage differential signalling (LVDS). A first prototype of the SparkPix-S, with a reduced matrix size of 96×96 pixels, is currently under production on a 130 nm CMOS technology. Simulated performance results show an equivalent noise charge <60 el. r.m.s. at 1 MHz repetition rate, with a maximum input energy of 60 keV and capability to discriminate charge signals with equivalent energy as low as 900 eV.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Integration of EDWARD readout architecture in full-field fluorescence imaging detector

Data bandwidth, timing resolution and resource utilization in readouts of radiation detectors are a constant challenge. Event driven solutions are pushing against well-trenched framed solutions. The idea for an asynchronous readout architecture called EDWARD ( E vent- D riven W ith A ccess and R eset D ecoder) was presented at the TWEPP 2021 conference. Here we show the progress of our work which resulted in two chip prototypes. The first one, named 3FI65P1, is a full device with the analog pixel circuitry suited for full-field fluorescence imaging. It is already manufactured, and preliminary results are presented. Finally, the second chip, named EDWARD65P1, contains digital pulse generators with Poisson-exponential distribution in each pixel for extraction of the performance matrix of the EDWARD architecture alone.

47 OTHER INSTRUMENTATION↗