Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “Process design”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 163 records · Page 9

Hyperplane decision trees as piecewise linear surrogate models for chemical process design

Recent trends in chemical engineering research point towards an increasing reliance on data-driven modeling approaches. Neural networks, for instance, have proven to be accurate when data is plentiful and high-dimensional, but in many cases, they require computationally-intensive training procedures. Here, in this work, we describe hyperplane decision trees (HT) as a highly expressive and low-compute machine learning model architecture. These models are locally linear and have linear decision boundaries, resulting in a piecewise linear model of the data. This property allows them to be converted into mixed-integer linear constraints which can be globally optimized. Our open-source PyTorch implementation of this method is a fast, flexible, and accessible way to build accurate piecewise linear models of data.

Decision trees↗

Design, processing, and testing of LSI arrays for space station

The development of a low power, high performance MOS 256-bit random assess memory with beam leads is discussed. Beam lead process development on silicon-on-sapphire (SOS) is also discussed, and initial electrical results on beam lead SOS TA5388 devices are presented. A comparison of the beam leaded 256-bit RAM (TA6567) layout is made with the non-beam leaded version (TA6473).

Schneider, W. C.↗

Design, processing, and testing of LSI arrays for space station

The development of a beam-leaded low power, high performance metal-oxide-semiconductor (MOS), 256-bit random access memory (RAM) was reported. Previous success with the aluminum-gate current-sense version and a silicon-gate voltage-sense version led to the present effort to make a beam-leaded silicon-gate RAM. Some problems unique to the silicon-on-sapphire beam-lead process development are presented. Beam-leaded SOS TA5388 devices using a Si3N4 passivation layer were shown to have good electrical parameters.

Schneider, W. C.↗

Design, processing, and testing of LSI arrays for space station

At wafer probe, units of the TA6567 circuit, a beam leaded COS/MOS/SOS 256-bit RAM, were demonstrated to be functionally perfect. An aluminum gate current-sense version and a silicon-gate voltage-sense version of this memory were developed. Initial base line data for the beam lead SOS process using the TA5388 circuit show the stability of the dc device characteristics through the beam lead processing.

Schneider, W. C.↗

Design, processing, and testing of LSI arrays for space station

Data for the beam-leaded silicon-on-sapphire (SOS) process using the TA5388 dual-complementary pair plus inverted circuit show the stability of the dc device characteristics through the complete beam-lead processing and packaging steps. A more complex circuit, the TA6567 - a silicon-gate, voltage-sense BL/CMOS/SOS 256-bit RAM, has also been made that was functionally perfect at wafer probe. Efforts to increase the yield of this circuit and to obtain electrically perfect packaged units are discussed.

Schneider, W. C.↗

Design, processing, and testing of LSI arrays for space station

The work on the Process Analysis Structure was continued with the layout being completed, the 100X and 10X artwork being finalized, and the process and test sequences being prepared. Test programs were written for computer-controlled integrated-circuit testing and data reduction.

Ipri, A. C.↗

Design, processing and testing of LSI arrays: Hybrid microelectronics task

Mathematical cost factors were generated for both hybrid microcircuit and printed wiring board packaging methods. A mathematical cost model was created for analysis of microcircuit fabrication costs. The costing factors were refined and reduced to formulae for computerization. Efficient methods were investigated for low cost packaging of LSI devices as a function of density and reliability. Technical problem areas such as wafer bumping, inner/outer leading bonding, testing on tape, and tape processing, were investigated.

Himmel, R. P.↗