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Single-event effect (SEE) and total ionizing dose (TID) test results are presented for various hardened and commercial power metal-oxide-semiconductor field effect transistors (MOSFETs), including vertical planar, trench, superjunction, and lateral process designs.
Silicon-Carbide device technology has generated much interest in recent years. With superior thermal performance, power ratings and potential switching frequencies over its Silicon counterpart, Silicon-Carbide offers a greater possibility for high powered switching applications in extreme environment. In particular, Silicon-Carbide Metal-Oxide- Semiconductor Field-Effect Transistors' (MOSFETs) maturing process technology has produced a plethora of commercially available power dense, low on-state resistance devices capable of switching at high frequencies. A novel hard-switched power processing unit (PPU) is implemented utilizing Silicon-Carbide power devices. Accelerated life data is captured and assessed in conjunction with a damage accumulation model of gate oxide and drain-source junction lifetime to evaluate potential system performance at high temperature environments.
Single-event effect (SEE) test results are presented for commercial grade, automotive grade, and radiation-hardened trench power MOSFETs.
This study was being undertaken to determine the single event effect susceptibility of the commercial Vishay 60-V TrenchFET power MOSFET. Heavy-ion testing was conducted at the Texas AM University Cyclotron Single Event Effects Test Facility (TAMU) and the Lawrence Berkeley National Laboratory BASE Cyclotron Facility (LBNL). In addition, initial 200-MeV proton testing was conducted at Massachusetts General Hospital (MGH) Francis H. Burr Proton Beam Therapy Center. Testing was performed to evaluate this device for single-event effects from lower-LET, lighter ions relevant to higher risk tolerant space missions.
Single-event gate rupture (SEGR) is a potentially catastrophic failure mechanism of power MOSFETs biased in the off-state. In part due to the severity of-SEGR consequences and in part due to the difficulty of accurated SEGR rate estimation, SEGR mitigation me1hodologies emphasize risk avoidance, using heavy-ion accelerator testing to define safe operating conditions for a surface-incident linear energy transfer {LET). This "safe-operating area" (SOA) within which the device may be biased without experiencing SEGR is then often derated by a prescribed factor to ensure low risk of SEGR. Although research in 1996 indicated that such LET-based SEGR hardness requiremen1s could provide false assurance of safe operation unless one also considered· ion energy], most mission SEGR requirements are still specified in terms of surface-incident LET. Moreover, terrestrial SEGR tests at a given surface-incident LET are limited by the small number of ion species and energies available at heavy-ion accelerators. In comparison, the on-orbit radiation environment is composed of all of the naturally-occurring elements with peak fluxes at nearly GeV/nucleon energies. The primary objective of this study is to examine whether typical derating of high-energy heavy-ion accelerator test data bounds the risk for SEGR from higher-energy on-orbit ions with the mission LET requirement.
Investigation into mesoplasma formation from heavy ion strike in 4H-SiC power MOSFETs. Simulations involving the time evolution of several parameters have determined that the formation of a mesoplasma occurs deep within the epi of the device. Various physical parameters were investigated, and only thermal conductivity affected mesoplasma formation.
The purpose of this document is two-fold. First, the document lists and discusses many of the issues important to understand when testing power MOSFETs. Second, the recommended approach for using radiation test data to define the device application requirements is presented. These include SEE rate calculation, data analysis, and derating guidelines. A significant amount of work has been done on the basic effects of SEB and SEGR. References are supplied where seminal work has been done on the topic at hand. The reader is urged to review the references if the testing issues or mission application at hand are complex.
Several newly available Hi-Rel total dose hardened power MOSFETs manufactured by Fuji Electric Device Technology Co. Ltd (FDT) in conjunction with the Japan Aerospace Exploration Agency (JAXA) were tested for single-event gate rupture (SEGR) and single-event burnout (SEB). The safe-operating area (SOA) of the 2SK4217 (a 100 V rated device), 2SK4152 (130 V), 2SK4155 (200 V), and the 2SK4158 (250 V) were tested with silver (Ag) and xenon (Xe) ions having incident LETs of 42.2 and 53.1 MeV cm2/mg, respectively. Test results show these devices are comparable to currently available total dose hardened technology.
This study was undertaken to determine the single event effect (SEE) susceptibility of two different MOSFET components. Heavy-ion testing was conducted at the Lawrence Berkeley National Laboratory (LBNL) Berkeley Accelerator Space Effects (BASE) Facility 88” Cyclotron. Its purpose was to evaluate these devices as candidates for use on Goddard Modular SmallSat Architecture (GMSA) adapter board for the GTOSat project.
This study was undertaken to determine the single-event effect susceptibility of the IRF5NJ9540 p-channel power MOSFET from Infineon. Heavy-ion testing was conducted at the Texas A&M University (TAMU) Cyclotron.
This study was undertaken to determine the single-event effect susceptibility of the radiation-hardened MRH25N12U3 (JANSR2N7593) power MOSFET recently developed by Microchip Technology, Inc.
This irradiation campaign was performed to evaluate the destructive single event effect (SEE) susceptibility of a n-channel power MOSFET from SSDI for space-based instrumentation. Testing was performed at Michigan State University’s (MSU) Facility for Rate Isotope Beams (FRIB) using an LET of 50.5 MeV·cm 2 /mg
The most common metalized substrates used in high-power switching packages consist of a ceramic layer such as Aluminum Nitride (AlN) sandwiched between two copper layers. Ceramic substrates are used because it has the key characteristic of having high dielectric strength while being thermally conductive. A large drawback to ceramic substrates is that they do not allow for a multi-layered circuit design. By replacing the traditional ceramic substrate with organic direct bonded copper (ODBC) we can open a wide range of possibilities when it comes to power module layout such as multi-layered circuits and double-sided cooling. Both benefits are critical while packaging high-performance Gallium Oxide (Ga2O3) MOSFETs. Because of Ga2O3's relatively poor thermal conductivity, a double-sided cooled package becomes necessary. Therefore, the use of ODBC provides the flexibility to fabricate copper traces carrying much higher currents, and by creating a multi-layered package, we can drastically reduce the parasitic inductance inside the power module. Achieving lower parasitic inductance is critical for an ultra-fast Ga2O3 package to avoid excessive voltage overshoot and ringing. Using ODBC, we have designed novel packages capable of handling the challenges presented by fast Ga2O3 switching. Using multi-physics modeling software, we can validate our design before building the prototype. Due to the simple process parameters needed to work with ODBC, we can rapidly create prototypes without using external vendors. This flexibility allows us to quickly design, build, and validate highly complex switching power modules to accommodate next generation, Ga2O3 switching devices.
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This compendium of SEGR and SEB data organizes results from several laboratories comparing failure thresholds for several different manufacturers and technologies. The results of this compendium are aimed at the designer to show the possible variations between manufacturers and processes.