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OpenSHMEM Reference Implementation using UCCS-uGNI Transport Layer. In: PGAS '14 Proceedings of the 8th International Conference on Partitioned Global Address Space Programming Models, Article No. 18

OpenSHMEM is a library interface implementation and specification that enables the implementation of the Partitioned Global Address Space (PGAS) model. It exports modern RDMA network functionality and communication semantics to applications very efficiently. There are many closed source implementations of OpenSHMEM for modern RDMA interconnects such as InfiniBand and Cray's Gemini and Aries. Given the important role that Cray systems play in HPC, in this paper, we present an open source implementation of OpenSHMEM for Cray XE/XK/XC systems. To implement OpenSHMEM, we use the uGNI interface. uGNI is a generic interface that is designed for multiple programming models. The interface fits well the goal of UCCS. Having OpenSHMEM with UCCS-uGNI allows usage of the same implementation over multiple interconnects. This also translates into many advantages that come with common code such as resource sharing, increasing productivity because of less code maintenance, etc. Preliminary results show that OpenSHMEM-UCCS performs comparable to state-of-the-art Cray SHMEM for Put, Get, and AMO operations.

Janjusic, Tomislav↗

ZFP Hardware Implementation

ZFP is a floating-point compression format gaining traction in high-performance computing applications. A software implementation has demonstrated the ability to reduce data movement across communication channels and to reduce the footprint of floating-point arrays in memory. Nevertheless, any benefit in performance is limited to the spare compute cycles available before reaching bandwidth limitations. A hardware implementation of ZFP has the potential to substantially improve HPC application performance. Hardware compression speedup over software alone on a single CPU core ranges from 15x for 1-D arrays to over 200x for 3-D arrays. The implementation of ZFP is sourced in SystemC to facilitate its evaluation in various architectures. The encode pipeline consists of several modules. Uncompressed blocks of floating-point numbers in IEEE format flow into the pipeline in a stream and a compressed bitstream flows out from the pipeline. The decode pipeline is the inverse of the encode pipeline. A modular design enables formats other than IEEE (such as posits) to be considered with minor adaptations. Best performance will be realized from the hardware ZFP unit when batches of blocks are processed at a time. The implementation supports 1-D, 2- D and 3-D blocks of floating-point numbers. The hardware implementation of ZFP has been validated with the software implementation of ZFP. C++ template parameters are used to specify the bit width of floating-point numbers and the array dimension of the encoder. A test bench program has been created with several test cases, some with continuous data that is ideal for ZFP, and others with extreme cases containing numbers near or at the maximum or minimum values supported by the number format.

Lloyd, GS↗

Formulation and Experimental Validation of an Agricultural Implement-Only MPR System for Maximum Compatibility with Existing Agricultural Tractors

Tightening emissions regulations and rising fuel costs have driven a desire across many industries for more efficient actuation systems. This is particularly true of the agricultural sector. An extremely common arrangement in this sector is the tractor and implement pairing, in which actuators on an implement are powered by a hydraulic supply system on the towing tractor. This arrangement complicates the development of energy efficient hydraulic systems, as many new system designs require modification of both machines to reap efficiency benefits. Past work by the authors’ team has demonstrated great potentials for Multi-Pressure-Rail (MPR) technology involving both the tractor and implement subsystems. However, applicability of this MPR technology in a more realistic scenario where only one vehicle is equipped with such technology was not addressed. This work proposes an implementation of the MPR technology to an agricultural planter that allows significant savings, while only modifying the implement machine. This is done by manipulating the load sense network of a stock tractor to set system pressures to those required by the MPR system. This greatly reduces the barrier to implementation of MPR technology in agriculture. The work begins by outlining the reference machine for the system, then reviews the MPR system working principle. After this, the proposed expansion to the MPR concept is laid out and applied to the reference system. Finally, experimental validation is carried out, demonstrating up to a 35% reduction in system power consumption when paired with a state of the art, double-LS System tractor, and 15% with a single-LS System tractor.

24 POWER TRANSMISSION AND DISTRIBUTION↗

Using Generative AI to implement the discrepancy checker for a Nearly Autonomous Management and Control System for Advanced Reactors

Developments related to generative artificial intelligence (AI) have brought a major breakthrough in AI. These developments are rapidly accelerating developments in different science and engineering applications. Nearly Autonomous Management and Control (NAMAC) system provides recommendations to the operator for maintaining the safety and performance of the reactor. The discrepancy checker (DC) is an important component of the NAMAC) system, whose goal is to determine if the plant is moving towards the expected system state after the control actions are injected. In this work, we explore generative AI methods, particularly, a generative pretrained transformer (GPT) for implementing the DC function in NAMAC. The GPT-based DC aims to alert the operator in situations outside NAMAC’s scope and act as a chatbot the operator can use to retrieve relevant information. This study involves two versions of GPT developed by OpenAI: GPT-3.5 and GPT-4. These GPTs are trained on huge amounts of undisclosed general domain datasets. We explored two methods to adapt GPTs for DC implementation in NAMAC: fine-tuning and retrieval augmented generation. A small knowledge base (information file) that encompasses rules for DC implementation and some general information related to NAMAC has been created to support DC implementation using GPT. In this work, the GPT-based DC implementations have been tested for their reasoning abilities, comprehension, information retrieval, and extraction abilities. It should be noted that this paper only presents a preliminary study to test the feasibility of DC implementation using generative AI technology. Given the potential risks and severe consequences associated with nuclear reactor applications, combined with the black-box nature of AI, extensive offline and online testing and reliability analyses of GPT-based DCs are needed for further developing such capabilities.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

International Review of the Development and Implementation of Energy Efficiency Standards and Labeling Programs

Appliance energy efficiency standards and labeling (S&L) programs have been important policy tools for regulating the efficiency of energy-using products for over 40 years and continue to expand in terms of geographic and product coverage. The most common S&L programs include mandatory minimum energy performance standards (MEPS) that seek to push the market for efficient products, and energy information and endorsement labels that seek to pull the market. This study seeks to review and compare some of the earliest and most well-developed S&L programs in three countries and one region: the U.S. MEPS and ENERGY STAR, Australia MEPS and Energy Label, European Union MEPS and Ecodesign requirements and Energy Label and Japanese Top Runner programs. For each program, key elements of S&L programs are evaluated and comparative analyses across the programs undertaken to identify best practice examples of individual elements as well as cross-cutting factors for success and lessons learned in international S&L program development and implementation. The international review and comparative analysis identified several overarching themes and highlighted some common factors behind successful program elements. First, standard-setting and programmatic implementation can benefit significantly from a legal framework that stipulates a specific timeline or schedule for standard-setting and revision, product coverage and legal sanctions for non-compliance. Second, the different MEPS programs revealed similarities in targeting efficiency gains that are technically feasible and economically justified as the principle for choosing a standard level, in many cases at a level that no product on the current market could reach. Third, detailed survey data such as the U.S. Residential Energy Consumption Survey (RECS) and rigorous analyses provide a strong foundation for standard-setting while incorporating the participation of different groups of stakeholders further strengthen the process. Fourth, sufficient program resources for program implementation and evaluation are critical to the effectiveness of standards and labeling programs and cost-sharing between national and local governments can help ensure adequate resources and uniform implementation. Lastly, check-testing and punitive measures are important forms of enforcement while the cancellation of registration or product sales-based fines have also proven effective in reducing non-compliance. The international comparative analysis also revealed the differing degree to which the level of government decentralization has influenced S&L programs and while no single country has best practices in all elements of standards and labeling development and implementation, national examples of best practices for specific elements do exist. For example, the U.S. has exemplified the use of rigorous analyses for standard-setting and robust data source with the RECS database while Japan's Top Runner standard-setting principle has motivated manufacturers to exceed targets. In terms of standards implementation and enforcement, Australia has demonstrated success with enforcement given its long history of check-testing and enforcement initiatives while mandatory information-sharing between EU jurisdictions on compliance results is another important enforcement mechanism. These examples show that it is important to evaluate not only the drivers of different paths of standards and labeling development, but also the country-specific context for best practice examples in order to understand how and why certain elements of specific S&L programs have been effective.

29 ENERGY PLANNING, POLICY, AND ECONOMY↗

Evaluation of Two CEDA Weatherization Pilot Implementations of an Exterior Insulation and Over-Clad Retrofit Strategy for Residential Masonry Buildings in Chicago

This project examines the implementation of an exterior insulation and over-clad strategy for brick masonry buildings in Chicago. The strategy was implemented at a free-standing two story two-family dwelling and a larger free-standing multifamily building. The test homes selected for this research represent predominant housing types for the Chicago area. High heating energy use typical in these buildings threaten housing affordability. Uninsulated mass masonry wall assemblies also have a strongly detrimental impact on comfort. Significant changes to the performance of masonry wall assemblies is generally beyond the reach of typical weatherization (Wx) program resources. The Community and Economic Development Association of Cook County, Inc. (CEDA) has secured a Sustainable Energy Resources for Consumers (SERC) innovation grant sponsored by the United States Department of Energy (DOE). This grant provides CEDA the opportunity to pursue a pilot implementation of innovative approaches to retrofit in masonry wall enclosures. The exterior insulation and over-clad strategy implemented through this project was designed to allow implementation by contractors active in CEDA weatherization programs and using materials and methods familiar to these contractors. The retrofit measures are evaluated in terms of feasibility, cost and performance. Through observations of the strategies implemented, the research described in this report identifies measures critical to performance as well as conditions for wider adoption. The research also identifies common factors that must be considered in determining whether the exterior insulation and over-clad strategy is appropriate for the building.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗

Implementation and Rejection of Industrial Steam System Energy Efficiency Measures

Steam systems consume approximately one third of energy applied at U.S. industrial facilities. To reduce energy consumption, steam system energy assessments have been conducted on a wide range of industry types over the course of five years through the Energy Savings Assessment (ESA) program administered by the U.S. Department of Energy (U.S. DOE). ESA energy assessments result in energy efficiency measure recommendations that are given potential energy and energy cost savings and potential implementation cost values. Saving and cost metrics that measure the impact recommended measures will have at facilities, described as percentages of facility baseline energy and energy cost, are developed from ESA data and used in analyses. Developed savings and cost metrics are examined along with implementation and rejection rates of recommended steam system energy efficiency measures. Based on analyses, implementation of steam system energy efficiency measures is driven primarily by cost metrics: payback period and measure implementation cost as a percentage of facility baseline energy cost (implementation cost percentage). Stated reasons for rejecting recommended measures are primarily based upon economic concerns. Additionally, implementation rates of measures are not only functions of savings and cost metrics, but time as well.

29 ENERGY PLANNING, POLICY, AND ECONOMY↗

Foundational Report Series: Advanced Distribution Management Systems for Grid Modernization, Implementation Strategy for a Distribution Management System

Electric distribution utilities encounter many challenges to successful deployment of Distribution Management Systems (DMSs). The key challenges are documented in this report, along with suggestions for overcoming them. This report offers a recommended list of activities for implementing a DMS. It takes a strategic approach to implementing DMS from a project management perspective. The project management strategy covers DMS planning, procurement, design, building, testing, Installation, commissioning, and system integration issues and solutions. It identifies the risks that are associated with implementation and suggests strategies for utilities to use to mitigate them or avoid them altogether. Attention is given to common barriers to successful DMS implementation. This report begins with an overview of the implementation strategy for a DMS and proceeds to put forward a basic approach for procuring hardware and software for a DMS; designing the interfaces with external corporate computing systems such as EMS, GIS, OMS, and AMI; and implementing a complete solution.

24 POWER TRANSMISSION AND DISTRIBUTION↗

Validation environment for AIPS/ALS: Implementation and results

The work is presented which was performed in porting the Fault Injection-based Automated Testing (FIAT) and Programming and Instrumentation Environments (PIE) validation tools, to the Advanced Information Processing System (AIPS) in the context of the Ada Language System (ALS) application, as well as an initial fault free validation of the available AIPS system. The PIE components implemented on AIPS provide the monitoring mechanisms required for validation. These mechanisms represent a substantial portion of the FIAT system. Moreover, these are required for the implementation of the FIAT environment on AIPS. Using these components, an initial fault free validation of the AIPS system was performed. The implementation is described of the FIAT/PIE system, configured for fault free validation of the AIPS fault tolerant computer system. The PIE components were modified to support the Ada language. A special purpose AIPS/Ada runtime monitoring and data collection was implemented. A number of initial Ada programs running on the PIE/AIPS system were implemented. The instrumentation of the Ada programs was accomplished automatically inside the PIE programming environment. PIE's on-line graphical views show vividly and accurately the performance characteristics of Ada programs, AIPS kernel and the application's interaction with the AIPS kernel. The data collection mechanisms were written in a high level language, Ada, and provide a high degree of flexibility for implementation under various system conditions.

Segall, Zary↗

Ames Research Center FY 2000 Implementation Plan: Leading Technology into the New Millennium

This document presents the implementation plan for Ames Research Center (ARC) within the overall framework of the NASA Strategic Plan. It describes how ARC intends to implement its Center of Excellence responsibilities, Agency assigned missions, Agency and Enterprise lead programs, and other roles in support of NASA's vision and mission. All Federal agencies are required by the 1993 Government Performance and Results Act to implement a long-term strategic planning process that includes measurable outcomes and strict accountability. At NASA, this planning process is shaped by the Space Act of 1958, annual appropriations, and other external mandates, as well as by customer requirements. The resulting Strategic Plan sets the overall architecture for what we do, identifies who our customers are, and directs where we are going and why. The Strategic Plan is the basis upon which decisions regarding program implementation and resource deployment are made. Whereas the strategic planning process examines the long-term direction of the organization and identifies a specific set of goals, the implementation planning process examines the detailed performance of the organization and allocates resources toward meeting these goals. It is the purpose of this implementation document to provide the connection between the NASA Strategic Plan and the specific programs and support functions that ARC employees perform. This connection flows from the NASA Strategic Plan, through the various Strategic Enterprise plans to the ARC Center of Excellence, primary missions, Lead Center programs, program support responsibilities, and ultimately, to the role of the individual ARC employee.

Source record↗

Improved Equivalent Linearization Implementations Using Nonlinear Stiffness Evaluation

This report documents two new implementations of equivalent linearization for solving geometrically nonlinear random vibration problems of complicated structures. The implementations are given the acronym ELSTEP, for "Equivalent Linearization using a STiffness Evaluation Procedure." Both implementations of ELSTEP are fundamentally the same in that they use a novel nonlinear stiffness evaluation procedure to numerically compute otherwise inaccessible nonlinear stiffness terms from commercial finite element programs. The commercial finite element program MSC/NASTRAN (NASTRAN) was chosen as the core of ELSTEP. The FORTRAN implementation calculates the nonlinear stiffness terms and performs the equivalent linearization analysis outside of NASTRAN. The Direct Matrix Abstraction Program (DMAP) implementation performs these operations within NASTRAN. Both provide nearly identical results. Within each implementation, two error minimization approaches for the equivalent linearization procedure are available - force and strain energy error minimization. Sample results for a simply supported rectangular plate are included to illustrate the analysis procedure.

Rizzi, Stephen A.↗

Pre-Hardware Optimization of Spacecraft Image Processing Software Algorithms and Hardware Implementation

Spacecraft telemetry rates have steadily increased over the last decade presenting a problem for real-time processing by ground facilities. This paper proposes a solution to a related problem for the Geostationary Operational Environmental Spacecraft (GOES-8) image processing application. Although large super-computer facilities are the obvious heritage solution, they are very costly, making it imperative to seek a feasible alternative engineering solution at a fraction of the cost. The solution is based on a Personal Computer (PC) platform and synergy of optimized software algorithms and re-configurable computing hardware technologies, such as Field Programmable Gate Arrays (FPGA) and Digital Signal Processing (DSP). It has been shown in [1] and [2] that this configuration can provide superior inexpensive performance for a chosen application on the ground station or on-board a spacecraft. However, since this technology is still maturing, intensive pre-hardware steps are necessary to achieve the benefits of hardware implementation. This paper describes these steps for the GOES-8 application, a software project developed using Interactive Data Language (IDL) (Trademark of Research Systems, Inc.) on a Workstation/UNIX platform. The solution involves converting the application to a PC/Windows/RC platform, selected mainly by the availability of low cost, adaptable high-speed RC hardware. In order for the hybrid system to run, the IDL software was modified to account for platform differences. It was interesting to examine the gains and losses in performance on the new platform, as well as unexpected observations before implementing hardware. After substantial pre-hardware optimization steps, the necessity of hardware implementation for bottleneck code in the PC environment became evident and solvable beginning with the methodology described in [1], [2], and implementing a novel methodology for this specific application [6]. The PC-RC interface bandwidth problem for the class of applications with moderate input-output data rates but large intermediate multi-thread data streams has been addressed and mitigated. This opens a new class of satellite image processing applications for bottleneck problems solution using RC technologies. The issue of a science algorithm level of abstraction necessary for RC hardware implementation is also described. Selected Matlab functions already implemented in hardware were investigated for their direct applicability to the GOES-8 application with the intent to create a library of Matlab and IDL RC functions for ongoing work. A complete class of spacecraft image processing applications using embedded re-configurable computing technology to meet real-time requirements, including performance results and comparison with the existing system, is described in this paper.

Kizhner, Semion↗

Implementing Scientific Simulation Codes Highly Tailored for Vector Architectures Using Custom Configurable Computing Machines

The motivation for this work comes from an observation that amidst the push for Massively Parallel (MP) solutions to high-end computing problems such as numerical physical simulations, large amounts of legacy code exist that are highly optimized for vector supercomputers. Because re-hosting legacy code often requires a complete re-write of the original code, which can be a very long and expensive effort, this work examines the potential to exploit reconfigurable computing machines in place of a vector supercomputer to implement an essentially unmodified legacy source code. Custom and reconfigurable computing resources could be used to emulate an original application's target platform to the extent required to achieve high performance. To arrive at an architecture that delivers the desired performance subject to limited resources involves solving a multi-variable optimization problem with constraints. Prior research in the area of reconfigurable computing has demonstrated that designing an optimum hardware implementation of a given application under hardware resource constraints is an NP-complete problem. The premise of the approach is that the general issue of applying reconfigurable computing resources to the implementation of an application, maximizing the performance of the computation subject to physical resource constraints, can be made a tractable problem by assuming a computational paradigm, such as vector processing. This research contributes a formulation of the problem and a methodology to design a reconfigurable vector processing implementation of a given application that satisfies a performance metric. A generic, parametric, architectural framework for vector processing implemented in reconfigurable logic is developed as a target for a scheduling/mapping algorithm that maps an input computation to a given instance of the architecture. This algorithm is integrated with an optimization framework to arrive at a specification of the architecture parameters that attempts to minimize execution time, while staying within resource constraints. The flexibility of using a custom reconfigurable implementation is exploited in a unique manner to leverage the lessons learned in vector supercomputer development. The vector processing framework is tailored to the application, with variable parameters that are fixed in traditional vector processing. Benchmark data that demonstrates the functionality and utility of the approach is presented. The benchmark data includes an identified bottleneck in a real case study example vector code, the NASA Langley Terminal Area Simulation System (TASS) application.

Rutishauser, David↗

Integrated System Health Management (ISHM): Systematic Capability Implementation

This paper provides a credible approach for implementation of ISHM capability in any system. The requirements and processes to implement ISHM capability are unique in that a credible capability is initially implemented at a low level, and it evolves to achieve higher levels by incremental augmentation. In contrast, typical capabilities, such as thrust of an engine, are implemented once at full Functional Capability Level (FCL), which is not designed to change during the life of the product. The approach will describe core ingredients (e.g. technologies, architectures, etc.) and when and how ISHM capabilities may be implemented. A specific architecture/taxonomy/ontology will be described, as well as a prototype software environment that supports development of ISHM capability. This paper will address implementation of system-wide ISHM as a core capability, and ISHM for specific subsystems as expansions and evolution, but always focusing on achieving an integrated capability.

Figueroa, Fernando↗

Economical Implementation of a Filter Engine in an FPGA

A logic design has been conceived for a field-programmable gate array (FPGA) that would implement a complex system of multiple digital state-space filters. The main innovative aspect of this design lies in providing for reuse of parts of the FPGA hardware to perform different parts of the filter computations at different times, in such a manner as to enable the timely performance of all required computations in the face of limitations on available FPGA hardware resources. The implementation of the digital state-space filter involves matrix vector multiplications, which, in the absence of the present innovation, would ordinarily necessitate some multiplexing of vector elements and/or routing of data flows along multiple paths. The design concept calls for implementing vector registers as shift registers to simplify operand access to multipliers and accumulators, obviating both multiplexing and routing of data along multiple paths. Each vector register would be reused for different parts of a calculation. Outputs would always be drawn from the same register, and inputs would always be loaded into the same register. A simple state machine would control each filter. The output of a given filter would be passed to the next filter, accompanied by a "valid" signal, which would start the state machine of the next filter. Multiple filter modules would share a multiplication/accumulation arithmetic unit. The filter computations would be timed by use of a clock having a frequency high enough, relative to the input and output data rate, to provide enough cycles for matrix and vector arithmetic operations. This design concept could prove beneficial in numerous applications in which digital filters are used and/or vectors are multiplied by coefficient matrices. Examples of such applications include general signal processing, filtering of signals in control systems, processing of geophysical measurements, and medical imaging. For these and other applications, it could be advantageous to combine compact FPGA digital filter implementations with other application-specific logic implementations on single integrated-circuit chips. An FPGA could readily be tailored to implement a variety of filters because the filter coefficients would be loaded into memory at startup.

Kowalski, James E.↗

Integrated System Health Management: Foundational Concepts, Approach, and Implementation.

Implementation of integrated system health management (ISHM) capability is fundamentally linked to the management of data, information, and knowledge (DIaK) with the purposeful objective of determining the health of a system. It is akin to having a team of experts who are all individually and collectively observing and analyzing a complex system, and communicating effectively with each other in order to arrive to an accurate and reliable assessment of its health. We present concepts, procedures, and a specific approach as a foundation for implementing a credible ISHM capability. The capability stresses integration of DIaK from all elements of a system. The intent is also to make possible implementation of on-board ISHM capability, in contrast to a remote capability. The information presented is the result of many years of research, development, and maturation of technologies, and of prototype implementations in operational systems (rocket engine test facilities). The paper will address the following topics: 1. ISHM Model of a system 2. Detection of anomaly indicators. 3. Determination and confirmation of anomalies. 4. Diagnostic of causes and determination of effects. 5. Consistency checking cycle. 6. Management of health information 7. User Interfaces 8. Example implementation ISHM has been defined from many perspectives. We define it as a capability that might be achieved by various approaches. We describe a specific approach that has been matured throughout many years of development, and pilot implementations. ISHM is a capability that is achieved by integrating data, information, and knowledge (DIaK) that might be distributed throughout the system elements (which inherently implies capability to manage DIaK associated with distributed sub-systems). DIaK must be available to any element of a system at the right time and in accordance with a meaningful context. ISHM Functional Capability Level (FCL) is measured by how well a system performs the following functions: (1) detect anomalies, (2) diagnose causes, (3) predict future anomalies/failures, and (4) provide the user with an integrated awareness about the condition of every element in the system and guide user decisions.

Figueroa, Fernando↗

Hardware Implementation of a Bilateral Subtraction Filter

A bilateral subtraction filter has been implemented as a hardware module in the form of a field-programmable gate array (FPGA). In general, a bilateral subtraction filter is a key subsystem of a high-quality stereoscopic machine vision system that utilizes images that are large and/or dense. Bilateral subtraction filters have been implemented in software on general-purpose computers, but the processing speeds attainable in this way even on computers containing the fastest processors are insufficient for real-time applications. The present FPGA bilateral subtraction filter is intended to accelerate processing to real-time speed and to be a prototype of a link in a stereoscopic-machine- vision processing chain, now under development, that would process large and/or dense images in real time and would be implemented in an FPGA. In terms that are necessarily oversimplified for the sake of brevity, a bilateral subtraction filter is a smoothing, edge-preserving filter for suppressing low-frequency noise. The filter operation amounts to replacing the value for each pixel with a weighted average of the values of that pixel and the neighboring pixels in a predefined neighborhood or window (e.g., a 9 9 window). The filter weights depend partly on pixel values and partly on the window size. The present FPGA implementation of a bilateral subtraction filter utilizes a 9 9 window. This implementation was designed to take advantage of the ability to do many of the component computations in parallel pipelines to enable processing of image data at the rate at which they are generated. The filter can be considered to be divided into the following parts (see figure): a) An image pixel pipeline with a 9 9- pixel window generator, b) An array of processing elements; c) An adder tree; d) A smoothing-and-delaying unit; and e) A subtraction unit. After each 9 9 window is created, the affected pixel data are fed to the processing elements. Each processing element is fed the pixel value for its position in the window as well as the pixel value for the central pixel of the window. The absolute difference between these two pixel values is calculated and used as an address in a lookup table. Each processing element has a lookup table, unique for its position in the window, containing the weight coefficients for the Gaussian function for that position. The pixel value is multiplied by the weight, and the outputs of the processing element are the weight and pixel-value weight product. The products and weights are fed to the adder tree. The sum of the products and the sum of the weights are fed to the divider, which computes the sum of products the sum of weights. The output of the divider is denoted the bilateral smoothed image. The smoothing function is a simple weighted average computed over a 3 3 subwindow centered in the 9 9 window. After smoothing, the image is delayed by an additional amount of time needed to match the processing time for computing the bilateral smoothed image. The bilateral smoothed image is then subtracted from the 3 3 smoothed image to produce the final output. The prototype filter as implemented in a commercially available FPGA processes one pixel per clock cycle. Operation at a clock speed of 66 MHz has been demonstrated, and results of a static timing analysis have been interpreted as suggesting that the clock speed could be increased to as much as 100 MHz.

Huertas, Andres↗

Optimized FPGA Implementation of Multi-Rate FIR Filters Through Thread Decomposition

Multi-rate finite impulse response (MRFIR) filters are among the essential signal-processing components in spaceborne instruments where finite impulse response filters are often used to minimize nonlinear group delay and finite precision effects. Cascaded (multistage) designs of MRFIR filters are further used for large rate change ratio in order to lower the required throughput, while simultaneously achieving comparable or better performance than single-stage designs. Traditional representation and implementation of MRFIR employ polyphase decomposition of the original filter structure, whose main purpose is to compute only the needed output at the lowest possible sampling rate. In this innovation, an alternative representation and implementation technique called TD-MRFIR (Thread Decomposition MRFIR) is presented. The basic idea is to decompose MRFIR into output computational threads, in contrast to a structural decomposition of the original filter as done in the polyphase decomposition. A naive implementation of a decimation filter consisting of a full FIR followed by a downsampling stage is very inefficient, as most of the computations performed by the FIR state are discarded through downsampling. In fact, only 1/M of the total computations are useful (M being the decimation factor). Polyphase decomposition provides an alternative view of decimation filters, where the downsampling occurs before the FIR stage, and the outputs are viewed as the sum of M sub-filters with length of N/M taps. Although this approach leads to more efficient filter designs, in general the implementation is not straightforward if the numbers of multipliers need to be minimized. In TD-MRFIR, each thread represents an instance of the finite convolution required to produce a single output of the MRFIR. The filter is thus viewed as a finite collection of concurrent threads. Each of the threads completes when a convolution result (filter output value) is computed, and activated when the first input of the convolution becomes available. Thus, the new threads get spawned at exactly the rate of N/M, where N is the total number of taps, and M is the decimation factor. Existing threads retire at the same rate of N/M. The implementation of an MRFIR is thus transformed into a problem to statically schedule the minimum number of multipliers such that all threads can be completed on time. Solving the static scheduling problem is rather straightforward if one examines the Thread Decomposition Diagram, which is a table-like diagram that has rows representing computation threads and columns representing time. The control logic of the MRFIR can be implemented using simple counters. Instead of decomposing MRFIRs into subfilters as suggested by polyphase decomposition, the thread decomposition diagrams transform the problem into a familiar one of static scheduling, which can be easily solved as the input rate is constant.

Kobayashi, Kayla N.↗