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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 163 records · Page 9
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Investigation of Superluminescent Diodes for Smart Lighting Systems. Final Report

The solid-state lighting ecosystem has evolved very rapidly over the last few years, with significant improvements in the technical performance of light-emitting diodes (LEDs) and the commoditization of LED-based lighting fixtures. As the performance of conventional lighting products begins to saturate, there is growing market interest in “Lighting as a Service” applications that will leverage advanced systems to impart new functionalities to lighting and improve energy efficiency, human health, and productivity. These “Smart Lighting” systems will include high-performance light sources, specialized sensors, and dynamic controls to deliver high quality, energy efficient, color tunable lighting with customized spatial light delivery and integrated visible light communication capability. To achieve these capabilities, smart lighting systems will place greater demands on the performance of light sources. Highly efficient sources with additional functionalities compared to conventional LEDs, such as small form factor, large modulation bandwidth, and spatially coherent output beams, will be required. While laser diodes have been proposed as potential sources for smart lighting systems, they also exhibit several properties that pose challenges, such as temporal coherence, extremely high spatial coherence, and ultra-narrow linewidths. To address these issues, we propose an investigation of an alternative device architecture known as a superluminescent diode (SLD). SLDs are similar in form to ridge laser diodes and share many of the same characteristics, such as stimulated emission operation, spatially coherent output, small form factor, and the potential for large modulation bandwidth. However, the operating principle for SLDs is distinct from laser diodes in that SLDs lack a strong cavity feedback mechanism, resulting in spatially coherent but temporally incoherent light output. Thus, SLDs may address the issues with laser diodes for lighting, while simultaneously maintaining some of the desirable characteristics of both laser diodes and LEDs. The objectives of this proposal are to design, grow, and fabricate blue (450 nm) SLDs on polar c-plane and nonpolar m-plane free-standing GaN substrates, and to evaluate their potential as sources in smart lighting systems through basic device characterization and detailed investigations of their efficiency droop and modulation bandwidth. The primary scientific aims of this work are to understand the fundamental role of optical gain in the superluminescent (non-lasing) regime on efficiency droop and modulation bandwidth in III-nitride emitters and to understand the effects of higher optical gain on SLD performance by comparing polar c-plane and nonpolar m-plane SLDs. The University of New Mexico (UNM) will collaborate with Sandia National Laboratories (SNL) and the Center for Integrated Nanotechnologies to design, fabricate, grow, and characterize the SLDs. UNM will perform the design and epitaxial growth, while SNL will focus on the fabrication and device characterization. The novelty of the proposed work includes the first comprehensive theoretical and experimental investigations of efficiency droop and the first investigation of modulation bandwidth in GaN-based emitters operating in the superluminescent regime. Moreover, the comparison of c-plane and m-plane SLDs will enable the first analysis of the effects of higher optical gain on the device performance. The development of high-performance GaN-based SLDs may enable efficiency gains and improved functionality in next-generation smart lighting systems.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2023

Suppressing Carbon Incorporation in Metal–Organic Chemical Vapor Deposition GaN Using High‐Offcut‐Angled Substrates

Carbon (C) is a common impurity that acts as a compensator within GaN grown via metal–organic chemical vapor deposition (MOCVD). Reducing C in GaN will help reduce the compensation level and provide a route to achieve GaN with reliably low effective doping for high-power device applications. GaN grown with fast growth rates on bulk GaN with various offcut angles via conventional-MOCVD (C-MOCVD) and laser-assisted MOCVD (LA-MOCVD) is compared and analyzed. C-incorporation effects are compared through quantitative secondary-ion mass spectroscopy analysis in GaN grown on GaN substrate with offcut angles of 4° and 0.3° toward m-plane over a wide range of growth rates by C-MOCVD and LA-MOCVD. For both growth techniques investigated, a significant reduction in C-incorporation is observed when a high-offcut-angle (4°) substrate is used as compared to a lower-offcut-angle (0.3°) substrate. Furthermore, with C-MOCVD, at the fastest growth condition investigated (17.26 μm h −1 at 0.3°-offcut, 15.25 μm h −1 at 4°-offcut), a reduction in [C] by 21.2X is observed with an increase in the offcut angle from 0.3° to 4°. A 82.6X reduction in [C] is observed with the similar fast growth condition via LA-MOCVD on GaN with 4° offcut angle (9.78 μm h −1 ) as compared to C-MOCVD at 0.3° offcut angle (17.26 μm h −1 ).

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2022

ICP etching of GaN microstructures in a Cl 2 –Ar plasma with subnanometer-scale sidewall surface roughness

In this work, substrate temperature, RF power, and ICP power were investigated for their effects on GaN micropillar sidewall roughness and etch characteristics. Elevated substrate temperature was shown to improve the sidewall etch morphology at low RF powers (reduced physical bombardment) and low ICP powers (lower plasma densities). Increased lateral etching is observed with both increased ICP power and substrate temperature, which both act to increase the chemical component of the etch. Etch conditions with a high chemical driving force resulted in faceting along the a-plane on the sidewalls. This faceting produced extremely smooth surfaces with root-meansquare roughness (R q ) as low as 0.20 nm which is comparable to typical epitaxy-ready surfaces and smaller than the a-plane lattice spacing of 0.3186 nm. The smooth surfaces produced in this study enable possibilities for laser facets or for new device structures that require high quality surfaces for GaN regrowth.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Efficiency cliff in scaling InGaN light-emitting diodes down to submicron

The top-down submicron fabrication of blue-emitting light-emitting diodes on Qromis Substrate Technology substrates is reported. Light-emitting diodes with mesa sizes as small as 250 × 250 nm 2 show ideal forward voltage and low leakage current density. It is observed that sidewall treatment and passivation methods used in micro-light-emitting diodes (2–20 μ m) do not lead to the same level of sidewall recombination suppression for submicron ones (< 1 μ m), as evidenced by a ∼70% decrease in peak external quantum efficiencies when mesa sizes are scaled from 2 μ m down to 250 nm. This is attributed to the lateral carrier diffusion being comparable to the mesa size, regardless of the sidewall passivation and recovery. The results call for rethinking the impact of sidewalls in emerging top-down fabricated (sub)micrometer-light-emitting diodes.

42 ENGINEERING↗
DOE OSTI2021

Thermal and Mechanical Design of a High-Voltage Power Electronics Package

This paper presents the thermal and mechanical design aspects of a power electronics package with 5-kV GaN devices. Through finite element analyses, we investigated the impact of different cooling configurations and device locations on the thermal performance and reliability of the package. We found that placing the devices closer to the direct bond copper substrate as opposed to a centered approach in the proposed double-sided cooling configuration resulted in improved heat dissipation. This approach also reduced the total number of attachment layers, thereby likely improving the reliability of the package. Furthermore, simulations revealed that the device location had a negligible impact on the thermomechanical behavior of the attachment layers, as they are more prone to the local coefficient of thermal expansion mismatch.

electronic packaging↗
DOE OSTI2020

Experimental Demonstration of Charge-Balanced GaN Super-Heterojunction Schottky Barrier Diode Capable of 2.8 kV Switching

This letter reports an experimental demonstration of charge-balanced GaN super-heterojunction Schottky barrier diodes (SHJ-SBDs). Charge balance between the n-type delta-doping and the p-type doping was achieved by adjusting the thickness of the pGaN. Furthermore, this device structure enabled scaling of breakdown voltage to over 3 kV, and dynamic switching up to 2.8 kV without using any field-plate.

42 ENGINEERING↗
DOE OSTI2023

1 kV GaN-on-Si Quasi-Vertical Schottky Rectifier

Here, this work demonstrates quasi-vertical GaN Schottky barrier diodes (SBDs) on 6-inch Si substrate with a breakdown voltage (BV) over 1 kV, the highest BV reported in vertical GaN-on-Si SBDs to date. The deep mesa inherently in quasi-vertical devices is leveraged to form a self-aligned edge termination, and the mesa sidewall is covered by the p-type nickel oxide (NiO) as a reduced surface field (RESURF) structure. This novel termination enables a parallel-plane junction electric field of 2.8 MV/cm. The device also shows low turn-on voltage of 0.5 V, and low specific on-resistance of 1.1 mΩ∙ cm 2 . Moreover, the device exhibits excellent overvoltage robustness under the continuous 800 V stress in the unclamped inductive switching test. These results show the good promise of the low-cost vertical GaN-on-Si power diodes.

42 ENGINEERING↗
DOE OSTI2023

1 kV Self-Aligned Vertical GaN Superjunction Diode

This work demonstrates vertical GaN superjunction (SJ) diodes fabricated via a novel self-aligned process. The SJ comprises n-GaN pillars wrapped by the charge-balanced p-type nickel oxide (NiO). After the NiO sputtering around GaN pillars, the self-aligned process exposes the top pillar surfaces without the need for additional lithography or a patterned NiO etching which is usually difficult. The GaN SJ diode shows a breakdown voltage (B V) of 1100 V, a specific on-resistance (R ON ) of 0.4 mΩ· cm2, and a SJ drift-region resistance ( R dr ) of 0.13 mΩ· cm2. Further, the device also exhibits good thermal stability with B V retained over 1 kV and R ON dropped to 0.3 mΩ· cm2 at 125°C. The trade-off between B V and R dr is superior to the 1D GaN limit. These results show the promise of vertical GaN SJ power devices. The self-aligned process is applicable for fabricating the heterogeneous SJ based on various wide- and ultra-wide bandgap semiconductors.

42 ENGINEERING↗
DOE OSTI2025

Robust Avalanche (1.5 kV, 2 kA/cm²) in Vertical GaN Diodes on Patterned Sapphire Substrate

The lack of avalanche capability is a key limitation of current lateral GaN devices. Despite the report of avalanche in vertical GaN-on-GaN devices, the high wafer cost hinders device commercialization. Here, in this work, we demonstrate a circuit-level avalanche in vertical GaN diodes on low-cost patterned sapphire substrate (PSS), with the avalanche voltage (1.57 kV) and avalanche current density (>2 kA/cm 2 ) both being the highest reported in GaN devices on foreign substrates. The PSS enables a lower dislocation density than conventional sapphire substrate and is employed in high-voltage GaN devices for the first time. The avalanche voltage in the circuit test reaches 98% of the parallel-plane limit, further affirming that near-ideal avalanche breakdown can be realized on GaN devices on foreign substrates. These results show the promise of the GaN-on-PSS platform for low-cost, robust power devices.

42 ENGINEERING↗
DOE OSTI2020

High-Speed Nonpolar InGaN/GaN Superluminescent Diode With 2.5 GHz Modulation Bandwidth

We demonstrate a superluminescent diode fabricated on a nonpolar m-plane GaN substrate by employing a linearly tapered waveguide design. A high electrical -3dB modulation bandwidth ( f\n 3dB \n) of 2.5 GHz at a current density of 30 kA/cm\n 2 \n is achieved. The high modulation bandwidth is attributed to the shorter carrier recombination lifetime, the linear gain curve in the nonpolar m-plane quantum wells, and the ability to operate at high current densities while effectively suppressing lasing. We derive a general expression for the -3dB bandwidth as a function of current density for SLDs using a similar approach to that for laser diodes. The -3dB bandwidth of a nonpolar superluminescent diode increases exponentially with current density. The experimental results are consistent with the derived expression for f\n 3dB \n vs. current density.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2021

12.5 kV GaN Super-Heterojunction Schottky Barrier Diodes

In this work, we report GaN super-heterojunction Schottky barrier diodes (SHJ-SBDs) with substantially improved performance. Metal-2DEG sidewall n-ohmic contacts were deployed to achieve low contact resistance of 0.75 Ω · mm, avoiding the risk of abnormally high contact resistance caused by inaccurate etch depth control. A pGaN notch formed near the cathode successfully eliminated excessive hole conduction caused by the sidewall n-ohmic contact. Isolation was improved by a high-energy Al implantation step. The resulting SHJ-SBD exhibited a breakdown voltage (BV) of 12.5 kV and a specific ON-resistance of 100.8 mΩ · cm 2 .

42 ENGINEERING↗
DOE OSTI2023

Implanted Guard Ring Edge Termination With Avalanche Capability for Vertical GaN Devices

Edge termination is the key building block in power devices to enable near-ideal, avalanche breakdown voltage (BV). Here, this work presents the design, fabrication, and physics of a GaN guard ring (GR) edge termination formed by selective-area nitrogen implantation through an epitaxial p-GaN layer. The fabrication of this termination only includes a single implantation step that does not require precise control of implant depth, rendering a large process latitude. The selective-area implantation produces p-GaN rings that are separated by the implanted, semi-insulating regions. The number and spacing of the p-type rings are found to determine the BV of the vertical GaN p-n diode. The 16-ring structure enables a BV of 1800 V, being 88% of the theoretical 1-D parallel-plane limit. Avalanche characteristics are observed in devices with a large variety of GR designs. Finally, we present a comprehensive survey on the efficiency, fabrication complexity, real estate, and avalanche capability of various edge termination techniques that have been reported in vertical GaN devices. The high efficiency (among the highest reported in avalanche-capable GaN terminations), simple and robust fabrication process, and uniform avalanche capability make this implanted GR a promising edge termination for high-voltage GaN devices.

42 ENGINEERING↗
DOE OSTI2026

Effect of Illumination Area on the Ultrafast Temporal Response of MSM GaN Photodiodes

We investigate the influence of spatial illumination profiles on the temporal response of metal–semiconductor–metal GaN photodiodes. Using both simulation and experimental measurements, we compare the response curves under two scenarios: illumination confined to the active area between electrodes and extended illumination beyond the contacts. The results show that limiting the beam illumination to the active region significantly sharpens the response, reducing the long decay tails associated with slow carrier drift from peripheral regions. As a result, the experimental data closely match simulation predictions, confirming that illumination geometry plays a critical role in optimizing photodiode performance for ultrafast detection applications.

Carrier drift time↗
DOE OSTI2020

Surge-Energy and Overvoltage Ruggedness of P-Gate GaN HEMTs

An essential ruggedness of power devices is the capability of safely withstanding the surge energy. The surge ruggedness of the GaN high-electron-mobility transistor (HEMT), a power transistor with no or minimal avalanche capability, has not been fully understood. This article unveils the comprehensive physics associated with the surge-energy withstand process and the failure mechanisms of p-gate GaN HEMTs. Two commercial p-gate GaN HEMTs with Ohmic- and Schottky-type gate contacts are studied. Two circuits are developed to study the device surge ruggedness: an unclamped inductive switching circuit is first used to identify the withstand dynamics and failure mechanisms, and a clamped inductive switching circuit with a controllable parasitic inductance is then designed to mimic the surge energy in converter-like switching events. The p-gate GaN HEMT is found to withstand the surge energy through a resonant energy transfer between the device capacitance and the load/parasitic inductance rather than a resistive energy dissipation as occurred in the avalanche. If the device resonant voltage goes below zero, the device reversely turns on and the inductor is discharged. The device failure occurs at the transient of peak resonant voltage and is limited by the device overvoltage capability rather than the surge energy, dV/dt , or overvoltage duration. Almost no energy is dissipated in the resonant withstand process and the device failure is dominated by an electric field rather than a thermal runaway. Furthermore, these results provide critical understandings on the ruggedness of GaN HEMTs and important references for their qualifications and applications.

42 ENGINEERING↗
DOE OSTI2020

Factors and Considerations for Modeling Loss of a GaN-based Inverter

The article investigates the impacts of four often-neglected factors on the loss model of a GaN-based full-bridge inverter: parasitic capacitance of the devices, dynamics of junction temperature (Tj) under time-varying power dissipation (Ploss), case temperature estimation, and detailed considerations of the passive components. Procedures to calculate the converter loss considering the above factors are proposed and implemented. A 4.5-kW hard-switching inverter prototype using gallium nitrite (GaN) high-electron-mobility transistors is used to experimentally demonstrate the impact of each factor on the converter loss model. Furthermore, it is found that the accuracy of a converter loss model is mainly affected by the passive components at the light load condition, whereas the thermal and loss models of the active components become the major factors as the output power increases. The results show that after considering the above factors, the converter loss discrepancy between calculation and measurement can be reduced from 30.6 W (28%) to 2.5 W (less than 3%) at heavy load (Po = 4.5 kW), while at the light load condition (Po = 500 W), it is reduced from 3.9 W (28%) to 2.6 W (16%). Furthermore, the difference between simulated and measured case temperature of the GaN devices is within 6 °C.

42 ENGINEERING↗
DOE OSTI2024

Output Capacitance Loss of GaN HEMTs in Steady-State Switching

The output capacitance (C OSS ) loss, a loss produced when the device’s output capacitor is charged and discharged, has become a concern for GaN high electron mobility transistors (HEMTs) in high-frequency applications. This work presents a new, easy-to-implement method for the C OSS loss characterization based on the unclamped inductive switching (UIS) setup. As compared to prior approaches, this method involves the device’s ON-state conduction and could measure the C OSS loss in a single pulse and the steady-state switching. The C OSS loss of three types of mainstream commercial GaN HEMTs is characterized, which exhibit some common dependencies including a non-monotonic relation with the dv/dt (or resonance frequency), a linear relation with the ON-state current, a power-law relation with the peak blocking voltage, and little temperature dependence. In addition, their C OSS losses all show minimal distinctions in a single pulse and the steady-state switching, despite the increased on-resistance in the steady-state switching. Furthermore, this suggests that the traps accounting for the C OSS loss possess different de-trapping time constants as compared to the traps governing the dynamic on-resistance. Finally, a unified model is established to describe the C OSS loss of all three types of GaN HEMTs. These results provide important references for the high-frequency application of GaN HEMTs and new insights into the physical origin of their C OSS loss.1

42 ENGINEERING↗