Digital Frequency-Differencing Circuit
Circuit measures both sign and magnitude of difference in frequency.
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Circuit measures both sign and magnitude of difference in frequency.
Digital data handling circuits for pulse amplifiers
A circuit generates an analog voltage proportional to an angle, in response to two sinusoidal input voltages having magnitudes proportional to the sine and cosine of the angle, respectively. That is to say, given input voltages proportional to sin(Omega(t))sin(Theta) and sin(Omega(t))cos(Theta) [where Theta denotes the angle, mega denotes 2(pi) x a carrier frequency, and t denotes time], the circuit generates a steady voltage proportional to Theta. The output voltage varies continuously from its minimum to its maximum value as Theta varies from -180deg to 180deg. While the circuit could accept input modulated sine and cosine signals from any source, it must be noted that such signals are typical of the outputs of shaft-angle resolvers in electromagnetic actuators used to measure and control shaft angles for diverse purposes like aiming scientific instruments and adjusting valve openings. In effect, the circuit is an analog computer that calculates the arctangent of the ratio between the sine and cosine signals. The full-circle angular range of this arctangent circuit stands in contrast to the range of prior analog arctangent circuits, which is from slightly greater than -90deg to slightly less than +90deg. Moreover, for applications in which continuous variation of output is preferred to discrete increments of output, this circuit offers a clear advantage over resolver- to-digital integrated circuits.
A family of standard, high-reliability hardware used for packaging digital integrated circuits is described. The design transition from early prototypes to production hardware is covered and future plans are discussed. Interconnections techniques are described as well as connectors and related hardware available at both the microcircuit packaging and main-frame level. General applications information is also provided.
The project utilizes design automation software tools to design, simulate, and fabricate a pH meter integrated circuit (IC) system including a successive approximation type seven-bit analog to digital converter circuits using a 1.25 micron N-Well CMOS MOSIS process. The input voltage ranges from 0.5 to 1.0 V derived from a special type pH sensor, and the output is a three-digit decimal number display of pH with one decimal point.
Digital data processor, circuit design and fabrication, digital word readout, and interfaces for IMP D and IMP E pulse frequency modulation encoding system
Innovative circuit derives sidereal seconds from precise 60-Hz source. Sidereal-rate generator puts out sidereal clock signals with error of only about 1.8 seconds per year. Output pulse periods uniform, solar and sidereal outputs available from single source, circuit compatible with normal digital clocks, and circuit driven by readily available reference frequency. Applications in stellar tracking, celestial navigation, and celestial photography.
Thick film hybrid techniques are used to develop circuitry for a brushless dc motor commutator. The power commutator contains the driving circuit and an amplifier that controls the armature current. A position decoder contains digital integrated circuits which receive the signals from the armature position sensors and generate the driving signals for the power commutator in the proper sequence. These units drive motors with stall currents up to about 400 mA.
Design and testing of majority logic redundancy for spaceborne and GSE digital systems
Feedback system employing a digital logic comparator to detect and correct amplifier drift provides stable gain characteristics for nanosecond amplifiers used in counting applications. Additional anticoincidence logic enables application of the regulation circuit to the amplifier and discriminator while they are mounted in an operable circuit.
Circuit for remote digital control of frequency synthesizers, giving schematic diagram
Improvement in genlock subsystem consists in incorporation of controllable delay circuit into path of composite synchronization signal obtained from external video source. Delay circuit helps to eliminate potential jitter in video display and ensures setup requirements for digital timing circuits of video camera satisfied.
This poster describes a first attempt to demonstrate a multi-chip prototype lander control and sensor signal digitization electronics circuit board comprised of ten NASA Glenn IC Generation 11 SiC JFET-R IC chips in 460 °C, 9.4 MPa harsh Venus surface conditions. The lander circuit ceased electrical operation prematurely at 107 °C as the Venus chamber heated up. Optical and SEM post-test inspections indicate fatal dielectric cracks occurred on only one of the ten SiC chips.
Circuitry has been developed for digital control of the Canopus tracker. A feasibility and demonstration breadboard has been constructed using microelectronic integrated circuits. The breadboard contains the digital circuits necessary for closed-digital logic necessary for star acquisition, particle rejection, programmable gate selection, cone angle selection, and routing of the digital roll error signal.
A phase shift key (PSK) to BiO-L demodulator which uses standard digital integrated circuits is discussed. The demodulator produces NRZ-L, bit clock, and BiO-L outputs from digital PSK input signals for which the carrier is a 2 to the Nth multiple of the bit rate. Various bit and carrier rates which are accommodated by changing various component values within the demodulator are described. The use of the unit for sinusoidal inputs as well as digital inputs is discussed.
The GEO-CAPE mission described in NASA's Earth Science and Applications Decadal Survey requires high spatial, temporal, and spectral resolution measurements to monitor and characterize the rapidly changing chemistry of the troposphere over North and South Americas. High-frame-rate focal plane arrays (FPAs) with many pixels are needed to enable such measurements. A high-throughput digital detector readout integrated circuit (ROIC) that meets the GEO-CAPE FPA needs has been developed, fabricated, and tested. The ROIC is based on an innovative charge integrating, fast, high-precision analog-to-digital circuit that is built into each pixel. The 128×128-pixel ROIC digitizes all 16,384 pixels simultaneously at frame rates up to 16 kHz to provide a completely digital output on a single integrated circuit at an unprecedented rate of 262 million pixels per second. The approach eliminates the need for off focal plane electronics, greatly reducing volume, mass, and power compared to conventional FPA implementations. A focal plane based on this ROIC will require less than 2 W of power on a 1×1-cm integrated circuit. The ROIC is fabricated of silicon using CMOS technology. It is designed to be indium bump bonded to a variety of detector materials including silicon PIN diodes, indium antimonide (InSb), indium gallium arsenide (In- GaAs), and mercury cadmium telluride (HgCdTe) detector arrays to provide coverage over a broad spectral range in the infrared, visible, and ultraviolet spectral ranges.
Recent developments in liquid encapsulated Czochralski techniques for the growth of semiinsulating GaAs for integrated circuit applications have resulted in significant improvements in the quality and quantity of GaAs material suitable for device processing. The emergence of high performance GaAs integrated circuit technologies has accelerated the demand for high quality, large diameter semiinsulating GaAs substrates. The new device technologies, including digital integrated circuits, monolithic microwave integrated circuits and charge coupled devices have largely adopted direct ion implantation for the formation of doped layers. Ion implantation lends itself to good uniformity and reproducibility, high yield and low cost; however, this technique also places stringent demands on the quality of the semiinsulating GaAs substrates. Although significant progress was made in developing a viable planar ion implantation technology, the variability and poor quality of GaAs substrates have hindered progress in process development.
Circuit for processing output of charge-coupled device (CCD) imager provides increased time for analog-to-digital conversion, thereby reducing bandwidth required for video processing. Instead of one sampleand-hold circuit of conventional processor, improved processor includes two sample-and-hold circuits alternated with each other. Dual-sampler processor operates with lower bandwidth and with timing requirements less stringent than those of single-sample processor.