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At least 163 records · Page 9

All sources NASA NTRS DOE OSTI

NASA NTRS2007

Assessment of SOI Devices and Circuits at Extreme Temperatures

Electronics designed for use in future NASA space exploration missions are expected to encounter extreme temperatures and wide thermal swings. Such missions include planetary surface exploration, bases, rovers, landers, orbiters, and satellites. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of mission. The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical devices, circuits, and systems suitable for applications in deep space exploration missions and aerospace environment. Silicon-On-Insulator (SOI) technology has been under active consideration in the electronics industry for many years due to the advantages that it can provide in integrated circuit (IC) chips and computer processors. Faster switching, less power, radiationtolerance, reduced leakage, and high temp-erature capability are some of the benefits that are offered by using SOI-based devices. A few SOI circuits are available commercially. However, there is a noticeable interest in SOI technology for different applications. Very little data, however, exist on the performance of such circuits under cryogenic temperatures. In this work, the performance of SOI integrated circuits, evaluated under low temperature and thermal cycling, are reported. In particular, three examples of SOI circuits that have been tested for operation at low at temperatures are given. These circuits are SOI operational amplifiers, timers and power MOSFET drivers. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these circuits for use in space exploration missions at cryogenic temperatures. The findings are useful to mission planners and circuit designers so that proper selection of electronic parts can be made, and risk assessment can be established for such circuits for use in space missions.

Elbuluk, Malik↗

NASA NTRS2010

Documentation of Stainless Steel Lithium Circuit Test Section Design

The Early Flight Fission-Test Facilities (EFF-TF) team was tasked by Naval Reactors Prime Contract Team (NRPCT) to design, fabricate, and test an actively pumped lithium (Li) flow circuit. This Li circuit takes advantage of work in progress at the EFF TF on a stainless steel sodium/potassium (NaK) circuit. The effort involved modifying the original stainless steel NaK circuit such that it could be operated with Li in place of NaK. This new design considered freeze/thaw issues and required the addition of an expansion tank and expansion/extrusion volumes in the circuit plumbing. Instrumentation has been specified for Li and circuit heaters have been placed throughout the design to ensure adequate operational temperatures and no uncontrolled freezing of the Li. All major components have been designed and fabricated prior to circuit redesign for Li and were not modified. Basic circuit components include: reactor segment, Li to gas heat exchanger, electromagnetic liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. The reactor segment, based on a Los Alamos National Laboratory 100-kW design study with 120 fuel pins, is the only prototypic component in the circuit. However, due to earlier funding constraints, a 37-pin partial-array of the core, including the central three rings of fuel pins (pin and flow path dimensions are the same as those in the full design), was selected for fabrication and test. This Technical Publication summarizes the design and integration of the pumped liquid metal Li flow circuit as of May 1, 2005.

Godfroy, T. J.↗

NASA NTRS2010

Documentation of Stainless Steel Lithium Circuit Test Section Design

Godfroy, Thomas J.↗

NASA NTRS2011

Fingerprinted circuits and methods of making and identifying the same

A circuit having a fingerprint for identification of a particular instantiation of the circuit is disclosed. The circuit may include a plurality of digital circuits or gates. Each of the digital circuits or gates is responsive to a configuration voltage applied to its analog input for controlling whether or not the digital circuit or gate performs its intended digital function and each of the digital circuits or gates transitioning between its functional state and its at least one other state when the configuration voltage equals a boundary voltage. The boundary voltage varies between different instantiations of the circuit for a majority of the digital circuits or gates and these differing boundary voltages serving to identify (or fingerprint) different instantiations of the same circuit.

Ferguson, Michael Ian↗

NASA NTRS2012

Fingerprinted circuits and methods of making and identifying the same

Ferguson, Michael Ian↗

NASA NTRS1999

Experiments on Evolving Software Models of Analog Circuits

Analog circuits are of great importance in electronic system design since the world is fundamentally analog in nature. While the amount of digital design activity far outpaces that of analog design, most digital systems require analog modules for interfacing with the external world. It was recently estimated that approximately 60% of digital application- specific integrated circuit designs incorporated analog circuits. With challenging analog circuit design problems and few analog design engineers, there are economic reasons for automating the analog design process, especially time-to-market considerations. Techniques for analog circuit design automation began appearing about two decades ago. These methods incorporated heuristics [6], knowledge bases [1], simulated annealing [5], and other algorithms. Efforts using techniques from evolutionary computation began appearing over the last few years. These include the use of genetic algorithms to select electronic component values (for example, the resistance value of a resistor), to select circuit topologies, and to design amplifiers using a limited set of canned topologies [4]. A genetic programming-based analog circuit design system has been demonstrated in which the circuit sizes, component values, and the circuit topologies are determined automatically [3]. The genetic-algorithm systems typically represent circuit structures as vectors of parameters encoded in binary strings, while the genetic programming system manipulates tree data structures.

Lohn, Jason D.↗

DOE OSTI2017

Low latency asynchronous interface circuits

In one form, a logic circuit includes an asynchronous logic circuit, a synchronous logic circuit, and an interface circuit coupled between the asynchronous logic circuit and the synchronous logic circuit. The asynchronous logic circuit has a plurality of asynchronous outputs for providing a corresponding plurality of asynchronous signals. The synchronous logic circuit has a plurality of synchronous inputs corresponding to the plurality of asynchronous outputs, a stretch input for receiving a stretch signal, and a clock output for providing a clock signal. The synchronous logic circuit provides the clock signal as a periodic signal but prolongs a predetermined state of the clock signal while the stretch signal is active. The asynchronous interface detects whether metastability could occur when latching any of the plurality of the asynchronous outputs of the asynchronous logic circuit using said clock signal, and activates the stretch signal while the metastability could occur.

42 ENGINEERING↗

DOE OSTI2017

Current limiter circuit system

An apparatus comprising a steady state sensing circuit, a switching circuit, and a detection circuit. The steady state sensing circuit is connected to a first, a second and a third node. The first node is connected to a first device, the second node is connected to a second device, and the steady state sensing circuit causes a scaled current to flow at the third node. The scaled current is proportional to a voltage difference between the first and second node. The switching circuit limits an amount of current that flows between the first and second device. The detection circuit is connected to the third node and the switching circuit. The detection circuit monitors the scaled current at the third node and controls the switching circuit to limit the amount of the current that flows between the first and second device when the scaled current is greater than a desired level.

42 ENGINEERING↗

DOE OSTI2014

Superior model for fault tolerance computation in designing nano-sized circuit systems

As CMOS technology scales nano-metrically, reliability turns out to be a decisive subject in the design methodology of nano-sized circuit systems. As a result, several computational approaches have been developed to compute and evaluate reliability of desired nano-electronic circuits. The process of computing reliability becomes very troublesome and time consuming as the computational complexity build ups with the desired circuit size. Therefore, being able to measure reliability instantly and superiorly is fast becoming necessary in designing modern logic integrated circuits. For this purpose, the paper firstly looks into the development of an automated reliability evaluation tool based on the generalization of Probabilistic Gate Model (PGM) and Boolean Difference-based Error Calculator (BDEC) models. The Matlab-based tool allows users to significantly speed-up the task of reliability analysis for very large number of nano-electronic circuits. Secondly, by using the developed automated tool, the paper explores into a comparative study involving reliability computation and evaluation by PGM and, BDEC models for different implementations of same functionality circuits. Based on the reliability analysis, BDEC gives exact and transparent reliability measures, but as the complexity of the same functionality circuits with respect to gate error increases, reliability measure by BDEC tends to be lower than the reliability measure by PGM. The lesser reliability measure by BDEC is well explained in this paper using distribution of different signal input patterns overtime for same functionality circuits. Simulation results conclude that the reliability measure by BDEC depends not only on faulty gates but it also depends on circuit topology, probability of input signals being one or zero and also probability of error on signal lines.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2022

Characterizing the Reproducibility of Noisy Quantum Circuits

The ability of a quantum computer to reproduce or replicate the results of a quantum circuit is a key concern for verifying and validating applications of quantum computing. Statistical variations in circuit outcomes that arise from ill-characterized fluctuations in device noise may lead to computational errors and irreproducible results. While device characterization offers a direct assessment of noise, an outstanding concern is how such metrics bound the reproducibility of a given quantum circuit. Here, we first directly assess the reproducibility of a noisy quantum circuit, in terms of the Hellinger distance between the computational results, and then we show that device characterization offers an analytic bound on the observed variability. We validate the method using an ensemble of single qubit test circuits, executed on a superconducting transmon processor with well-characterized readout and gate error rates. The resulting description for circuit reproducibility, in terms of a composite device parameter, is confirmed to define an upper bound on the observed Hellinger distance, across the variable test circuits. This predictive correlation between circuit outcomes and device characterization offers an efficient method for assessing the reproducibility of noisy quantum circuits.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS1995

Circuit for high resolution decoding of multi-anode microchannel array detectors

A circuit for high resolution decoding of multi-anode microchannel array detectors consisting of input registers accepting transient inputs from the anode array; anode encoding logic circuits connected to the input registers; midpoint pipeline registers connected to the anode encoding logic circuits; and pixel decoding logic circuits connected to the midpoint pipeline registers is described. A high resolution algorithm circuit operates in parallel with the pixel decoding logic circuit and computes a high resolution least significant bit to enhance the multianode microchannel array detector's spatial resolution by halving the pixel size and doubling the number of pixels in each axis of the anode array. A multiplexer is connected to the pixel decoding logic circuit and allows a user selectable pixel address output according to the actual multi-anode microchannel array detector anode array size. An output register concatenates the high resolution least significant bit onto the standard ten bit pixel address location to provide an eleven bit pixel address, and also stores the full eleven bit pixel address. A timing and control state machine is connected to the input registers, the anode encoding logic circuits, and the output register for managing the overall operation of the circuit.

Kasle, David B.↗

NASA NTRS2007

Analog Nonvolatile Computer Memory Circuits

In nonvolatile random-access memory (RAM) circuits of a proposed type, digital data would be stored in analog form in ferroelectric field-effect transistors (FFETs). This type of memory circuit would offer advantages over prior volatile and nonvolatile types: In a conventional complementary metal oxide/semiconductor static RAM, six transistors must be used to store one bit, and storage is volatile in that data are lost when power is turned off. In a conventional dynamic RAM, three transistors must be used to store one bit, and the stored bit must be refreshed every few milliseconds. In contrast, in a RAM according to the proposal, data would be retained when power was turned off, each memory cell would contain only two FFETs, and the cell could store multiple bits (the exact number of bits depending on the specific design). Conventional flash memory circuits afford nonvolatile storage, but they operate at reading and writing times of the order of thousands of conventional computer memory reading and writing times and, hence, are suitable for use only as off-line storage devices. In addition, flash memories cease to function after limited numbers of writing cycles. The proposed memory circuits would not be subject to either of these limitations. Prior developmental nonvolatile ferroelectric memories are limited to one bit per cell, whereas, as stated above, the proposed memories would not be so limited. The design of a memory circuit according to the proposal must reflect the fact that FFET storage is only partly nonvolatile, in that the signal stored in an FFET decays gradually over time. (Retention times of some advanced FFETs exceed ten years.) Instead of storing a single bit of data as either a positively or negatively saturated state in a ferroelectric device, each memory cell according to the proposal would store two values. The two FFETs in each cell would be denoted the storage FFET and the control FFET. The storage FFET would store an analog signal value, between the positive and negative FFET saturation values. This signal value would represent a numerical value of interest corresponding to multiple bits: for example, if the memory circuit were designed to distinguish among 16 different analog values, then each cell could store 4 bits. Simultaneously with writing the signal value in the storage FFET, a negative saturation signal value would be stored in the control FFET. The decay of this control-FFET signal from the saturation value would serve as a model of the decay, for use in regenerating the numerical value of interest from its decaying analog signal value. The memory circuit would include addressing, reading, and writing circuitry that would have features in common with the corresponding parts of other memory circuits, but would also have several distinctive features. The writing circuitry would include a digital-to-analog converter (DAC); the reading circuitry would include an analog-to-digital converter (ADC). For writing a numerical value of interest in a given cell, that cell would be addressed, the saturation value would be written in the control FFET in that cell, and the non-saturation analog value representing the numerical value of interest would be generated by use of the DAC and stored in the storage FFET in that cell. For reading the numerical value of interest stored in a given cell, the cell would be addressed, the ADC would convert the decaying control and storage analog signal values to digital values, and an associated fast digital processing circuit would regenerate the numerical value from digital values.

MacLeod, Todd↗

NASA NTRS2010

Integral Battery Power Limiting Circuit for Intrinsically Safe Applications

A circuit topology has been designed to guarantee the output of intrinsically safe power for the operation of electrical devices in a hazardous environment. This design uses a MOSFET (metal oxide semiconductor field-effect transistor) as a switch to connect and disconnect power to a load. A test current is provided through a separate path to the load for monitoring by a comparator against a preset threshold level. The circuit is configured so that the test current will detect a fault in the load and open the switch before the main current can respond. The main current passes through the switch and then an inductor. When a fault occurs in the load, the current through the inductor cannot change immediately, but the voltage drops immediately to safe levels. The comparator detects this drop and opens the switch before the current in the inductor has a chance to respond. This circuit protects both the current and voltage from exceeding safe levels. Typically, this type of protection is accomplished by a fuse or a circuit breaker, but in order for a fuse or a circuit breaker to blow or trip, the current must exceed the safe levels momentarily, which may be just enough time to ignite anything in a hazardous environment. To prevent this from happening, a fuse is typically current-limited by the addition of the resistor to keep the current within safe levels while the fuse reacts. The use of a resistor is acceptable for non-battery applications where the wasted energy and voltage drop across the resistor can be tolerated. The use of the switch and inductor minimizes the wasted energy. For example, a circuit runs from a 3.6-V battery that must be current-limited to 200 mA. If the circuit normally draws 10 mA, then an 18-ohm resistor would drop 180 mV during normal operation, while a typical switch (0.02 ohm) and inductor (0.97 ohm) would only drop 9.9 mV. From a power standpoint, the current-limiting resistor protection circuit wastes about 18 times more power than the switch and the inductor configuration. In the fault condition, both the resistor and the inductor react immediately. The resistor reacts by allowing more current to flow and dropping the voltage. Initially, the inductor reacts by dropping the voltage, and then by not allowing the current to change. When the comparator detects the drop in voltage, it opens the switch, thus preventing any further current flow. The inductor alone is not sufficient protection, because after the voltage drop has settled, the inductor would then allow the current to change, in this example, the current would be 3.7 A. In the fault condition, the resistor is flowing 200 mA until the fuse blows (anywhere from 1 ms to 100 s), while the switch and inductor combination is flowing about 2 A test current while monitoring for the fault to be corrected. Finally, as an additional safety feature, the circuit can be configured to hold the switch opened until both the load and source are disconnected.

Burns, Bradley M.↗

DOE OSTI2022

Power supply circuit with multiple stages for converting high voltage to low voltage and power train having the same

A power supply circuit for converting a first voltage to a second voltage where the first voltage is greater than the second voltage, and a power train having the same, are provided. The power supply circuit may have multiple stages and each stage of the power supply circuit may include a first circuit block configured to provide a start-up power to a second circuit block; a second circuit block configured to generate a Pulse-Width-Modulation (PWM) signal that controls a pulse duration of a transistor; a third circuit block configured to activate or deactivate the transistor based on the PWM signal; a fourth circuit block configured to reset a magnetic flux in a transformer to a zero state when the transistor is deactivated; and a fifth circuit block configured to maintain an output of a stage below a predetermined value by adjusting a voltage across the transformer.

Singh, Brij N.↗

DOE OSTI2023

Direct current momentary circuit interrupter

A momentary circuit interrupter in series connection with a mechanical switch to provide protection against short circuit faults in a DC power circuit. The momentary circuit interrupter injects a transient voltage pulse via a pulse transformer to reduce a DC fault current to near zero in a DC circuit branch, thus allowing the mechanical switch to disconnect the faulty branch under a near zero-current condition. The power electronic circuit on the primary side of the transformer controls the discharge of a plurality of pre-charged capacitors to generate the transient voltage pulse during the fault interruption process, but otherwise does not incur any power loss during normal operation. The secondary winding of the pulse transformer conducts the main DC current, and is highly conductive to minimize the conduction power loss. The invention provides ultrafast response to a short circuit fault (even faster than solid-state circuit breakers and much faster than hybrid circuit breakers), significantly reduced overcurrent stress in the power system, and/or ultralow conduction power losses.

Shen, Zheng John↗

DOE OSTI2023

Quantum circuit fidelity estimation using machine learning

The computational power of real-world quantum computers is limited by errors. When using quantum computers to perform algorithms which cannot be efficiently simulated classically, it is important to quantify the accuracy with which the computation has been performed. In this work, we introduce a machine learning-based technique to estimate the fidelity between the state produced by a noisy quantum circuit and the target state corresponding to ideal noise-free computation. Our machine learning model is trained in a supervised manner, using smaller or simpler circuits for which the fidelity can be estimated using other techniques like direct fidelity estimation and quantum state tomography. Here we demonstrate that, for simulated random quantum circuits with a realistic noise model, the trained model can predict the fidelities of more complicated circuits for which such methods are infeasible. In particular, we show that the trained model may make predictions for circuits with higher degrees of entanglement than were available in the training set and that the model may make predictions for non-Clifford circuits even when the training set included only Clifford-reducible circuits. This empirical demonstration suggests classical machine learning may be useful for making predictions about beyond-classical quantum circuits for some non-trivial problems.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2018

Design and dynamic modeling of printed circuit heat exchangers for supercritical carbon dioxide Brayton power cycles

Due to the unique geometries and hydraulics of printed circuit heat exchangers and rapidly changing properties of supercritical carbon dioxide, the effective design and rating of printed circuit heat exchangers is an essential requirement for their use in supercritical carbon dioxide power cycles. In this study, one-dimensional design and dynamic models have been developed in Aspen Custom Modeler for printed circuit heat exchangers utilized in printed circuit heat exchangers Brayton power cycles. The design model is used to determine the optimal geometry parameters by minimizing the metal mass. The dynamic model is used to predict transient behavior and can be easily implemented into system-level models developed in Aspen Plus Dynamics for cycle performance evaluations. In these models, the heat transfer coefficient and friction factor are calculated using data reported by Heatric, a prominent printed circuit heat exchanger manufacturer. Both models are validated by comparing with the data from a small-scale exchanger used in the 100 kWe facility operated by the Naval Nuclear Laboratory, and then applied to design and simulate low- and high-temperature recuperators for a 10 MWe supercritical carbon dioxide indirect recompression closed Brayton cycle, which is of interest to the U.S. Department of Energy. The designs and dynamic responses of the printed circuit heat exchangers are compared with conventional shell-and-tube exchangers and microtube shell-and-tube exchangers for the same applications. Here, the simulation results indicate that the proposed printed circuit heat exchangers have fast dynamic responses due to their small metal masses and high heat transfer coefficients compared with the conventional shell-and-tube exchangers. Even though the metal masses of the designed PCHEs are slightly higher than those of the microtube shell-and-tube exchangers, the printed circuit heat exchangers are still promising candidates for heat recuperation because of their mature manufacturing procedures and abundant laboratory and industrial operating experience.

42 ENGINEERING↗

DOE OSTI2021

Model Reduction by Generalized Falk Method for Efficient Field-Circuit Simulations

The Generalized Falk Method (GFM) for coordinate transformation, together with two model-reduction strategies based on this method, are presented for efficient coupled field-circuit simulations. Each model-reduction strategy is based on a decision to retain specific linearly-independent vectors, called trial vectors, to construct a vector basis for coordinate transformation. The reduced-order models are guaranteed to be stable and passive since the GFM is a congruence transformation of originally symmetric positive definite systems. We also show that, unlike the Pad´e-via-Lanczos (PVL) method, the GFM does not generate unstable positive poles while reducing the order of circuit problems. Further, the proposed GFM is also faster when compared to methods of the type Lanczos (or Krylov) that are already widely used in circuit simulations for electrothermal and electromagnetic problems. The concept of response participation factors is introduced for the selection of the trial vectors in the proposed model-reduction methods. Further, we present methods to develop simple equivalent circuit networks for the field component of the overall field-circuit system. The implementation of these equivalent circuit networks in circuit simulators is discussed. With the proposed model-reduction strategies, significant improvement on the efficiency of the generalized Falk method is illustrated for coupled field-circuit problems.

42 ENGINEERING↗