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At least 1,585 records · Page 88

MPP disk subsystem

A disk subsystem for the Massively Parallel processor (MPP) is designed to the block diagram level. The subsystem is capable of storing 4,992 megabytes of data, expandable to 39,936 megabytes. The subsystem is capable of transferring data to the MPP Staging Memory at a rate of 25 megabytes/second, expandable to 100 megabytes/second. A lower cost disk subsystem is also presented. This alternate subsystem is capable of storing 3,744 megabytes with a transfer rate of 10.6 megabyte/second.

Hudgins, W. A.↗

Registration of a synthetic aperture radar image to Thematic Mapper imagery for remote sensing applications

Multiple Thematic Mapper multitemporal acquisitions from Landsat and one synthetic-aperture radar acquisition from Seasat have been precisely registered using Johnson Space Center registration processors. The registered images have been output in the Universal Transverse Mercator projection. The procedure to accomplish such disparate data processing tasks and the registration accuracy evaluation are discussed.

Yao, S. S.↗

Designing systems to satisfy their users - The coming changes in aviation weather and the development of a central weather processor

Attention is given to the development history of the Central Weather Processor (CWP) program of the Federal Aviation Administration. The CWP will interface with high speed digital communications links, accept data and information products from new sources, generate data processing products, and provide meteorologists with the capability to automate data retrieval and dissemination. The CWP's users are operational (air traffic controllers, meteorologists and pilots), institutional (logistics, maintenance, testing and evaluation personnel), and administrative.

Bush, M. W.↗

Program for Experimentation With Expert Systems

CERBERUS is forward-chaining, knowledge-based system program useful for experimentation with expert systems. Inference-engine mechanism performs deductions according to user-supplied rule set. Information stored in intermediate area, and user interrogated only when no applicable data found in storage. Each assertion posed by CERBERUS answered with certainty ranging from 0 to 100 percent. Rule processor stops investigating applicable rules when goal reaches certainty of 95 percent or higher. Capable of operating for wide variety of domains. Sample rule files included for animal identification, pixel classification in image processing, and rudimentary car repair for novice mechanic. User supplies set of end goals or actions. System complexity decided by user's rule file. CERBERUS written in FORTRAN 77.

Engle, S. W.↗

Computer Sciences and Data Systems, volume 2

Topics addressed include: data storage; information network architecture; VHSIC technology; fiber optics; laser applications; distributed processing; spaceborne optical disk controller; massively parallel processors; and advanced digital SAR processors.

Source record↗

Parallel discrete-event simulation of FCFS stochastic queueing networks

Physical systems are inherently parallel. Intuition suggests that simulations of these systems may be amenable to parallel execution. The parallel execution of a discrete-event simulation requires careful synchronization of processes in order to ensure the execution's correctness; this synchronization can degrade performance. Largely negative results were recently reported in a study which used a well-known synchronization method on queueing network simulations. Discussed here is a synchronization method (appointments), which has proven itself to be effective on simulations of FCFS queueing networks. The key concept behind appointments is the provision of lookahead. Lookahead is a prediction on a processor's future behavior, based on an analysis of the processor's simulation state. It is shown how lookahead can be computed for FCFS queueing network simulations, give performance data that demonstrates the method's effectiveness under moderate to heavy loads, and discuss performance tradeoffs between the quality of lookahead, and the cost of computing lookahead.

Nicol, David M.↗

XPQ/GCOS-8 SYSOUT Interface Software

Slave user program can obtain SYSOUT records and transfer them to remote device. XPQ/GCOS-8 SYSOUT interface software consists of modifications of GCOS-8 operating system. Includes application subroutine that enables XPQ remote-print software package as modified by LSOC to gain access to, read, and release data from GCOS-8 system output (SYSOUT) files. Contains slave subroutine RSYOT, site-unique Master Mode Entry (MME) processor, and alterations to GEOT, INIT, and System Macro modules for GCOS-8 SR3002/3003. RSYOT written in GCOS-8 Assembler.

Flohr, Franklin A.↗

Computation and parallel implementation for early vision

The problem of early vision is to transform one or more retinal illuminance images-pixel arrays-to image representations built out of such primitive visual features such as edges, regions, disparities, and clusters. These transformed representations form the input to later vision stages that perform higher level vision tasks including matching and recognition. Researchers developed algorithms for: (1) edge finding in the scale space formulation; (2) correlation methods for computing matches between pairs of images; and (3) clustering of data by neural networks. These algorithms are formulated for parallel implementation of SIMD machines, such as the Massively Parallel Processor, a 128 x 128 array processor with 1024 bits of local memory per processor. For some cases, researchers can show speedups of three orders of magnitude over serial implementations.

Gualtieri, J. Anthony↗

A mass storage system for supercomputers based on Unix

The authors present the design, implementation, and utilization of a large mass storage subsystem (MSS) for the numerical aerodynamics simulation. The MSS supports a large networked, multivendor Unix-based supercomputing facility. The MSS at Ames Research Center provides all processors on the numerical aerodynamics system processing network, from workstations to supercomputers, the ability to store large amounts of data in a highly accessible, long-term repository. The MSS uses Unix System V and is capable of storing hundreds of thousands of files ranging from a few bytes to 2 Gb in size.

Richards, J.↗

A new multirate sampled-data control law structure and synthesis algorithm

A new multirate sampled-data control law structure is defined and a new parameter-optimization-based synthesis algorithm for that structure is introduced. The synthesis algorithm can be applied to multirate, multiple-input multiple-output, sampled-data control laws having a prescribed dynamic order and structure, and a priori specified sampling/update rates for all sensors, processor states, and control inputs. The synthesis algorithm is applied to design two-input, two-output tip position controllers of various dynamic orders for a sixth-order, two-link robot arm model.

Berg, Martin C.↗

New multirate sampled-data control law structure and synthesis algorithm

A new multirate sampled-data control law structure is defined and a new parameter-optimization-based synthesis algorithm for that structure is introduced. The synthesis algorithm can be applied to multirate, multiple-input/multiple-output, sampled-data control laws having a prescribed dynamic order and structure, and a priori specified sampling/update rates for all sensors, processor states, and control inputs. The synthesis algorithm is applied to design two-input, two-output tip position controllers of various dynamic orders for a sixth-order, two-link robot arm model.

Berg, Martin C.↗

On-board packet switch architectures for communication satellites

NASA Lewis Research Center is developing an on-board information switching processor for a multichannel communications signal processing satellite. The information switching processor is a flexible, high-throughput, fault tolerant, on-board baseband packet switch used to route user data among user ground terminals. Through industry study contracts and in-house investigations, several packet switching architectures were examined for possible implementation. Three contention-free switching architectures were studied in detail, namely the shared memory approach, the shared bus approach, and the shared memory per beam approach. These three switching architectures are discussed and the advantages and disadvantages of each approach are examined.

Shalkhauser, Mary JO↗

A three dimensional multigrid Reynolds-averaged Navier-Stokes solver for unstructured meshes

A three-dimensional unstructured mesh Reynolds averaged Navier-Stokes solver is described. Turbulence is simulated using a single field-equation model. Computational overheads are minimized through the use of a single edge-based data-structure, and efficient multigrid solution technique, and the use of multi-tasking on shared memory multi-processors. The accuracy and efficiency of the code are evaluated by computing two-dimensional flows in three dimensions and comparing with results from a previously validated two-dimensional code which employs the same solution algorithm. The feasibility of computing three-dimensional flows on grids of several million points in less than two hours of wall clock time is demonstrated.

Mavriplis, D. J.↗

Active Rack Isolation System Program and Technical Status

The Boeing Active Rack Isolation System (ARIS) is one of the means used to isolate acceleration-sensitive scientific experiments from structurally transmitted disturbances aboard the International Space Station. The presentation provides an overview of ARIS and technical issues associated with the development of the active control system. An overview of ARIS analytical models is presented along with recent isolation performance predictions made using these models. Issues associated with commanding and capturing ARIS data are discussed and possible future options based on the ARIS ISS Characterization Experiment (ICE) Payload On-orbit Processor (POP) are outlined. An overview of the ARIS-ICE experiment scheduled to fly on ISS Flight 6A is presented. The presentation concludes with a discussion of recent- developmental work that includes passive rack damping, umbilical redesigns and advanced multivariable control design methods.

Bushnell, Glenn↗

Platform for Post-Processing Waveform-Based NDE

Signal- and image-processing methods are commonly needed to extract information from the waves, improve resolution of, and highlight defects in an image. Since some similarity exists for all waveform-based nondestructive evaluation (NDE) methods, it would seem that a common software platform containing multiple signal- and image-processing techniques to process the waveforms and images makes sense where multiple techniques, scientists, engineers, and organizations are involved. NDE Wave & Image Processor Version 2.0 software provides a single, integrated signal- and image-processing and analysis environment for total NDE data processing and analysis. It brings some of the most useful algorithms developed for NDE over the past 20 years into a commercial-grade product. The software can import signal/spectroscopic data, image data, and image series data. This software offers the user hundreds of basic and advanced signal- and image-processing capabilities including esoteric 1D and 2D wavelet-based de-noising, de-trending, and filtering. Batch processing is included for signal- and image-processing capability so that an optimized sequence of processing operations can be applied to entire folders of signals, spectra, and images. Additionally, an extensive interactive model-based curve-fitting facility has been included to allow fitting of spectroscopy data such as from Raman spectroscopy. An extensive joint-time frequency module is included for analysis of non-stationary or transient data such as that from acoustic emission, vibration, or earthquake data.

Roth, Don J.↗

Symbolic Analysis of Concurrent Programs with Polymorphism

The current trend of multi-core and multi-processor computing is causing a paradigm shift from inherently sequential to highly concurrent and parallel applications. Certain thread interleavings, data input values, or combinations of both often cause errors in the system. Systematic verification techniques such as explicit state model checking and symbolic execution are extensively used to detect errors in such systems [7, 9]. Explicit state model checking enumerates possible thread schedules and input data values of a program in order to check for errors [3, 9]. To partially mitigate the state space explosion from data input values, symbolic execution techniques substitute data input values with symbolic values [5, 7, 6]. Explicit state model checking and symbolic execution techniques used in conjunction with exhaustive search techniques such as depth-first search are unable to detect errors in medium to large-sized concurrent programs because the number of behaviors caused by data and thread non-determinism is extremely large. We present an overview of abstraction-guided symbolic execution for concurrent programs that detects errors manifested by a combination of thread schedules and data values [8]. The technique generates a set of key program locations relevant in testing the reachability of the target locations. The symbolic execution is then guided along these locations in an attempt to generate a feasible execution path to the error state. This allows the execution to focus in parts of the behavior space more likely to contain an error.

Rungta, Neha Shyam↗

Processor Emulator with Benchmark Applications

A processor emulator and a suite of benchmark applications have been developed to assist in characterizing the performance of data-centric workloads on current and future computer architectures. Some of the applications have been collected from other open source projects. For more details on the emulator and an example of its usage, see reference [1].

Lloyd, G. Scott↗