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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,567 records · Page 87

All sources NASA NTRS DOE OSTI

NASA NTRS2021

SEE Test Results for SAMA5D3

ARM processors power a class of high-performance, lower power system on a chip devices. In the absence of radiation effects, these devices are highly desirable for space use. The processor core architecture for ARM devices is licensed to provide computing on multiple hardware platforms. The A5 processor is in a unique pioneering space for providing detailed radiation response data to explore the baseline performance of these devices. These data can help set options for ARM processors and possibly impact design choices for the next generation of ARM fault tolerance capabilities. The SAMA5D3 was tested to establish general SEE performance for a relatively simple implementation of the ARM A5 core. This testing observed SRAM sensitivity starting at an LET of about 3 MeV-cm2/mg, with a saturated cross section of about 2x10-8cm2/bit, and this was determined by both active write and read of the caches, in addition to the use of a debugger to provide test results. Crash/SEFI data was collected using both Linux and bare metal C-code. The onset LET for crashes was about LET 1.5 MeV-cm2/mg, with saturated cross sections of about 2x10-5 cm2 for bare metal (low utilization), and 2x10-4cm2 for Linux (high utilization) tests.

Daniel, Andrew C.↗

DOE OSTI2015

Particle Communication and Domain Neighbor Coupling: Scalable Domain Decomposed Algorithms for Monte Carlo Particle Transport

In order to run Monte Carlo particle transport calculations on new supercomputers with hundreds of thousands or millions of processors, care must be taken to implement scalable algorithms. This means that the algorithms must continue to perform well as the processor count increases. In this paper, we examine the scalability of:(1) globally resolving the particle locations on the correct processor, (2) deciding that particle streaming communication has finished, and (3) efficiently coupling neighbor domains together with different replication levels. We have run domain decomposed Monte Carlo particle transport on up to 2 21 = 2,097,152 MPI processes on the IBM BG/Q Sequoia supercomputer and observed scalable results that agree with our theoretical predictions. These calculations were carefully constructed to have the same amount of work on every processor, i.e. the calculation is already load balanced. We also examine load imbalanced calculations where each domain’s replication level is proportional to its particle workload. In this case we show how to efficiently couple together adjacent domains to maintain within workgroup load balance and minimize memory usage.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗

DOE OSTI2015

Methods for synchronizing a countdown routine of a timer key and electronic device

A timer key relating to monitoring a countdown time of a countdown routine of an electronic device is disclosed. The timer key comprises a processor configured to respond to a countdown time associated with operation of the electronic device, a display operably coupled with the processor, and a housing configured to house at least the processor. The housing has an associated structure configured to engage with the electronic device to share the countdown time between the electronic device and the timer key. The processor is configured to begin a countdown routine based at least in part on the countdown time, wherein the countdown routine is at least substantially synchronized with a countdown routine of the electronic device when the timer key is removed from the electronic device. A system and method for synchronizing countdown routines of a timer key and an electronic device are also disclosed.

47 OTHER INSTRUMENTATION↗

DOE OSTI2015

EGR distribution and fluctuation probe based on CO2 measurements

A diagnostic system having a laser, an EGR probe, a detector and a processor. The laser may be a swept-.lamda. laser having a sweep range including a significant CO.sub.2 feature and substantially zero absorption regions. The sweep range may extend from about 2.708 .mu.m to about 2.7085 .mu.m. The processor may determine CO.sub.2 concentration as a function of the detector output signal. The processor may normalize the output signal as a function of the zero absorption regions. The system may include a plurality of EGR probes receiving light from a single laser. The system may include a separate detector for each probe. Alternatively, the system may combine the light returning from the different probes into a composite beam that is measured by a single detector. A unique modulation characteristic may be introduced into each light beam before combination so that the processor can discriminate between them in the composite beam.

33 ADVANCED PROPULSION SYSTEMS↗

DOE OSTI2015

Multi-petascale highly efficient parallel supercomputer

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗

DOE OSTI2017

Efficient packet forwarding using cyber-security aware policies

For balancing load, a forwarder can selectively direct data from the forwarder to a processor according to a loading parameter. The selective direction includes forwarding the data to the processor for processing, transforming and/or forwarding the data to another node, and dropping the data. The forwarder can also adjust the loading parameter based on, at least in part, feedback received from the processor. One or more processing elements can store values associated with one or more flows into a structure without locking the structure. The stored values can be used to determine how to direct the flows, e.g., whether to process a flow or to drop it. The structure can be used within an information channel providing feedback to a processor.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2017

Efficient packet forwarding using cyber-security aware policies

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2015

Ground-referenced single-ended system-on-package

A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a system function chip, and an MCM package configured to include the first processor chip and the system function chip. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. The system function chip is configured to include a second GRS interface circuit. A first set of electrical traces are fabricated within the MCM package and coupled to the first GRS interface circuit and to the second GRS interface circuit. The first GRS interface circuit and second GRS interface circuit together provide a communication channel between the first processor chip and the system function chip.

Dally, William J.↗

DOE OSTI2019

System and method for instantaneous power decomposition and estimation

A system disaggregates and estimates power consumption of electric loads powered by a single electrical outlet. The system includes a processor having a routine; a current sensor cooperating with the processor to measure samples for one line cycle of an aggregated current waveform for the electric loads powered by the single electrical outlet; and a voltage sensor cooperating with the processor to measure samples for the one line cycle of a voltage waveform for the electric loads powered by the single electrical outlet. The processor routine transfers the measured samples for the one line cycle of the aggregated current waveform and the voltage waveform into an aggregated voltage-current trajectory for the single electrical outlet, and provides an instantaneous decomposition of power consumption for a plurality of different categories of the electric loads from the aggregated voltage-current trajectory for the one line cycle.

Yang, Yi↗

DOE OSTI2019

Network-aware cache coherence protocol enhancement

A non-uniform memory access system includes several nodes that each have one or more processors, caches, local main memory, and a local bus that connects a node's processor(s) to its memory. The nodes are coupled to one another over a collection of point-to-point interconnects, thereby permitting processors in one node to access data stored in another node. Memory access time for remote memory takes longer than local memory because remote memory accesses have to travel across a communications network to arrive at the requesting processor. In some embodiments, inter-cache and main-memory-to-cache latencies are measured to determine whether it would be more efficient to satisfy memory access requests using cached copies stored in caches of owning nodes or from main memory of home nodes.

Roberts, David A.↗

DOE OSTI2020

Methods and apparatus to modify a binary file for scalable dependency loading on distributed computing systems

Methods and apparatus to modify a binary file for scalable loading on distributed computing systems are disclosed. An example method to modify a binary file for scalable loading on a distributed computing system includes identifying, by executing an instruction with a processor, in the binary file a file name for a shared file, determining, by executing an instruction with the processor, whether the shared file can be loaded based on a path name specified in the binary file, and, responsive to a determination that the shared file can be loaded, generating, by executing an instruction with the processor, an identifier that can be used to access a local file scalably copied from a global file system, and modifying, by executing an instruction with the processor, the binary file by replacing, in the binary file, the file name with the generated identifier.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2020

Redirecting data to improve page locality in a scalable data fabric

A data processing system includes a host processor, a local memory coupled to the host processor, a plurality of remote memory media, and a scalable data fabric coupled to the host processor and to the plurality of remote memory media. The scalable data fabric includes a filter for storing information indicating a location of data that is stored by the data processing system. The host processor includes a hardware sequencer coupled to the filter for selectively moving data stored by the filter to the local memory.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2020

System and method to characterize and identify operating modes of electric loads

A system characterizes and identifies one of a plurality of different operating modes of a number of electric loads. The system includes a processor; a voltage sensor providing a voltage signal for one of the electric loads to the processor; a current sensor providing a current signal for the one electric load to the processor; and a routine executed by the processor and structured to characterize the different operating modes using steady state and voltage-current trajectory features determined from the voltage and current signals, and to identify a particular one of the different operating modes based on a plurality of operating mode membership functions of the steady state and voltage-current trajectory features.

Yang, Yi↗

DOE OSTI2021

Interconnect architecture for three-dimensional processing systems

A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.

Jayasena, Nuwan S.↗

DOE OSTI2022

Systems and methods for plane-wave and fan-beam ultrasound-waveform tomography

A method for plane-wave or fan-beam ultrasound tomography includes: controlling, by a processor, a multi-channel ultrasound array controller to control a linear ultrasound transducer array to emit plane-wave or fan-beam ultrasound into a biological tissue, the linear ultrasound transducer array including a plurality of transducers; receiving, by the processor, plane-wave or fan-beam ultrasound waveform data from the transducers, the plane-wave or fan-beam ultrasound waveform data including reflections of the plane-wave or fan-beam ultrasound from the biological tissue; computing, by the processor, a synthetic ultrasound-waveform inversion from the received plane-wave or fan-beam ultrasound waveform data; and computing, by the processor, an image of the biological tissue from the synthetic ultrasound-waveform inversion.

Huang, Lianjie↗

DOE OSTI2023

Last-level collective hardware prefetching

A last-level collective hardware prefetcher (LLCHP) is described. The LLCHP is to detect a first off-chip memory access request by a first processor core of a plurality of processor cores. The LLCHP is further to determine, based on the first off-chip memory access request, that first data associated with the first off-chip memory access request is associated with second data of a second processor core of the plurality of processor cores. The LLCHP is further to prefetch the first data and the second data based on the determination.

Michelogiannakis, Georgios↗

DOE OSTI2023

System and method for predicting the presence of rare earth elements

A system for predicting rare earth elements (REEs) in a feedstock sample includes a measurement instrument that records a measurement for a sample, a processor communicatively coupled to the measuring instrument, and a memory communicatively coupled to the processor and containing machine readable instructions that, when executed by the processor, cause the processor to correlate the measurement series using a model; and predict a presence of one or more rare earth element based at least in part on the correlation. A method for predicting rare earth elements includes measuring feedstock samples via XRF or PGNAA, to generate a measurements of elements of interest with a lower atomic weight than REEs; correlating the measurements with a model; and predicting a presence of one or more rare earth elements based at least in part on the correlation.

Fuka, Matthew↗

DOE OSTI2017

An automatic input/output test experience of FPGA-based logic controller with I/O stimulator - 282

This paper describes an automatic testing approach instead of a traditional manual test for an FPGA-based Logic Controller (FLC). It mainly describes an automatic testing of FLC using an I/O stimulator with the initiated manual action. The FLC was developed by Doosan Heavy Industry and KAERI in S. Korea. We also developed a test-bed like I/O stimulator for a burning test based on the operational scenario. Signal sources from the I/O stimulator contain an analog input, an analog output, a digital input and a digital output, a programmable power supply, an RS232C serial interface, and a dual port Ethernet interface. LabVIEW Programming was used for the automatic testing. The FLC consists of a general processor module (FPM-01), a complex processor module (FPM-02), analog input modules (FAI-01), analog output modules (FAO-01), digital input modules (FDI-01), digital output modules (FDO-01), a data link module (FDL-01), and a network module (FNW-01). Among these, in this paper, automatic digital I/O testing and automatic analog I/O testing are described. In addition, for the accuracy of the automatic testing, two graphic recorders are used. One is the output results of general processor based testing, and the other is the output results of complex processor based testing. These are different company products. Redundancy recording was found in the test results. The test results were synchronized internally with the existing I/O stimulator and externally with two graphic recorders. Calibrations of all of the equipment were made before the system testing. Before the testing started, a test plan and the test procedure were set up in advance, and we performed test scenario-based automatic functional testing for the FLC as the qualification process. It can be several executed depending on the scenario and conditional parameters of the test. For validation of the accuracy and reliability in our automated test, manual testing was also performed. Manual tests were conducted in two ways. The first one was a manual test using Fluke 754 and Fluke 715. The other one was using embedded manual features of the I/O stimulator. By performing the automatic input and output testing using the I/O stimulator, the time and expense of FLC testing can be reduced significantly compared with a conventional manual test. We rechecked the automatic test results using Fluke754 manually. (authors)

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗