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The conceptual design and specifications are developed for an onboard experiment data support facility (OEDSF) to provide end to end processing of data from various payloads on board space shuttles. Classical data processing requirements are defined and modeled. Onboard processing requirements are analyzed. Specifications are included for an onboard processor.
Investigations have been conducted regarding the techniques required for Loran-C navigation with application to the general-aviation pilot. The goal has been to produce prototype equipment for flight evaluation which will provide enroute navigation in both latitude-longitude and rho-theta coordinates and to evaluate the nonprecision approach capabilities of such equipment. In connection with the considered project, a prototype Loran-C receiver has been flight-tested using a variety of flight paths, with and without simultaneous ground radar position data collection. Attention is given to a receiver overview, an antenna preamplifier/coupler, the Loran-C receiver RF processor, the tracking loop hardware, tracking loop programming, video output, the laboratory and flight evaluation, and work currently in progress.
Reference is made to a study by Casasent et al. (1983), which gave a description of a frequency-multiplexed acoustooptic processor and showed how it was capable of performing all the individual operations required in Kalman filtering. The data flow and organization of all required operations however, were not detailed in that study. Consideration is given here to a simpler Kalman filter state estimation problem. Equally spaced time-sampled intervals (k times T sub s, with k the iterative time index) are assumed. It is further assumed that the system noise vector w and the measurement noise vector v are uncorrelated and Gaussian distributed and that the noise statistics (Q and R) and the system model (Phi, Gamma, H) are known. The error covariance matrix P and the extrapolated error covariance matrix M can thus be precomputed and the Kalman gain matrix K sub k can be precomputed and stored for each input time sample.
A major problem in employing networks of microcomputers for the real-time simulation of complex systems is to allocate computational tasks to the various microcomputers in such a way that idle time and time lost in interprocess communication is minimized. The research reported in this paper is directed to the development of a software interface between a higher-level simulation language and a network of microcomputers. A CSSL-IV source program is translated to a data flow graph. This graph is then analyzed automatically so as to allocate computing tasks to the various processors.
In pursuit of real time animation of computer simulated space plasma phenomena, the code was rewritten for the Massively Parallel Processor (MPP). The program creates a dynamic representation of the global bowshock which is based on actual spacecraft data and designed for three dimensional graphic output. This output consists of time slice sequences which make up the frames of the animation. With the MPP, 16384, 512 or 4 frames can be calculated simultaneously depending upon which characteristic is being computed. The run time was greatly reduced which promotes the rapid sequence of images and makes real time animation a foreseeable goal. The addition of more complex phenomenology in the constructed computer images is now possible and work proceeds to generate these images.
The Numerical Aerodynamic Simulation (NAS) Systems Division received an Intel Touchstone Sigma prototype model Paragon XP/S- 15 in February, 1993. The i860 XP microprocessor with an integrated floating point unit and operating in dual -instruction mode gives peak performance of 75 million floating point operations (NIFLOPS) per second for 64 bit floating point arithmetic. It is used in the Paragon XP/S-15 which has been installed at NAS, NASA Ames Research Center. The NAS Paragon has 208 nodes and its peak performance is 15.6 GFLOPS. Here, we will report on early experience using the Paragon XP/S- 15. We have tested its performance using both kernels and applications of interest to NAS. We have measured the performance of BLAS 1, 2 and 3 both assembly-coded and Fortran coded on NAS Paragon XP/S- 15. Furthermore, we have investigated the performance of a single node one-dimensional FFT, a distributed two-dimensional FFT and a distributed three-dimensional FFT Finally, we measured the performance of NAS Parallel Benchmarks (NPB) on the Paragon and compare it with the performance obtained on other highly parallel machines, such as CM-5, CRAY T3D, IBM SP I, etc. In particular, we investigated the following issues, which can strongly affect the performance of the Paragon: a. Impact of the operating system: Intel currently uses as a default an operating system OSF/1 AD from the Open Software Foundation. The paging of Open Software Foundation (OSF) server at 22 MB to make more memory available for the application degrades the performance. We found that when the limit of 26 NIB per node out of 32 MB available is reached, the application is paged out of main memory using virtual memory. When the application starts paging, the performance is considerably reduced. We found that dynamic memory allocation can help applications performance under certain circumstances. b. Impact of data cache on the i860/XP: We measured the performance of the BLAS both assembly coded and Fortran coded. We found that the measured performance of assembly-coded BLAS is much less than what memory bandwidth limitation would predict. The influence of data cache on different sizes of vectors is also investigated using one-dimensional FFTs. c. Impact of processor layout: There are several different ways processors can be laid out within the two-dimensional grid of processors on the Paragon. We have used the FFT example to investigate performance differences based on processors layout.
The NASA Solar Electric Propulsion Technology Applications Readiness (NSTAR) Program has provided a single-string primary propulsion system to NASA's Deep Space 1 spacecraft. This spacecraft will carry about 81 kg of xenon propellant for the ion thruster, which can be throttled down from 2.3 to 0.5 kW as the spacecraft moves away from the Sun. The propellant load will provide about 20 months of propulsion at the one-half power throttle setpoint of 1.2 kW. This mission will validate the 2.5-kW ion propulsion system and will fly by the asteroid 1992 KD in 1999. If funding permits, Deep Space 1 also will encounter comets Wilson-Harrington and Borrelly in 2001. NASA Lewis Research Center's On-Board Propulsion Branch was responsible for the development of the 30-cm-diameter ion thruster, the 2.5-kW power processor unit (PPU), and the Digital Control and Interface Unit (DCIU) that controls the PPU/thruster/feed system and provides data and recovery from fault conditions. Lewis transferred the thruster and PPU technologies to the Hughes Electron Dynamics Division, which was selected to build two sets of flight thrusters, as well as the PPU's and DCIU's. Hughes subcontracted the DCIU development to Spectrum Astro Incorporated. The Jet Propulsion Laboratory (JPL) was primarily responsible for the NSTAR project management, thruster lifetests, the feed system, diagnostics, and the propulsion subsystem integration. A total of four engineering model thrusters and three breadboard PPU's were built, integrated, and tested. More than 50 development tests were conducted along with thruster design verification tests of 2000 and 1000 hours. In addition, an 8000-hr life demonstration test was successfully completed and demonstrated wear-rates consistent with full-power lifetimes in excess of 12,000 hours.
Several issues makes the processing of ultra wide band (UWB) SAR data acquired from an airborne platform difficult. The character of UWB data invalidates many of the usual SAR batch processing techniques, leading to the application of wavenumber domain type processors...This paper will suggest and evaluate an algorithm which combines a wavenumber domain processing algorithm with a motion compensation procedure which enables motion compensation to be applied as a function of target range and the azimuth angle.
Distributed Objects Protocol Layer, or DOPL, Provides a simple and general data communication abstraction that can support the distribution of C++ applications software functionality among an arbitrary collection of processors. The purposed of the abstraction is to minimize the cost of revising processing distribution decisions throughout the software development cycle, including after software has beed delivered to users.
This paper compares two waveform implementations generating the same RF signal using the same SDR development system. Both waveforms implement a satellite modem using QPSK modulation at 1M BPS data rates with one half rate convolutional encoding. Both waveforms are partitioned the same across the general purpose processor (GPP) and the field programmable gate array (FPGA). Both waveforms implement the same equivalent set of radio functions on the GPP and FPGA. The GPP implements the majority of the radio functions and the FPGA implements the final digital RF modulator stage. One waveform is implemented directly on the SDR development system and the second waveform is implemented using the JTRS/SCA model. This paper contrasts the amount of resources to implement both waveforms and demonstrates the importance of waveform partitioning across the SDR development system.
The Heat Melt Compactor (HMC) is designed to sterilize and process wastes produced during space missions. Benefits of the HMC include reduction of biohazards to the crew, reduction in volume of wastes that would otherwise require storage, production of radiation shielding tiles, and recovery of water and other resources. Water reuse is critical onboard spacecrafts; it reduces the need for resupply missions and saves valuable storage space. The main sources of water in HMC batches are food, beverages, shampoo, disinfecting wipes, toothpaste, and diapers. Water reclaimed by the HMC was analyzed for concentrations of Na+, NH4+, K+, Mg2+, Ca2+, Cl-‐, NO2-‐, Br-‐, NO3-‐, PO43-‐, SO42-‐, total organic carbon (TOC), total inorganic carbon (TIC), % total solids, and pH. The data are discussed in relation to the current water input characteristics established for the International Space Station Water Processor Assembly system. Batches with higher than average amounts of food produced HMC product water with higher sulfate content, and batches with higher proportions of disinfectant wipes and food yielded HMC product water with higher ammonium concentration. We also compared theoretical chemical composition of HMC product water based on food labels and literature values to experimental results.
A method for predicting failure parameters of semiconductor devices can include receiving a set of data that includes (i) characteristics of a sample semiconductor device, and (ii) parameters characterizing a stress condition. The method further includes extracting a plurality of feature values from the set of data and inputting the plurality of feature values into a trained model executing on the one or more processors, wherein the trained model is configured according to an artificial intelligence (AI) algorithm based on a previous plurality of feature values, and wherein the trained model is operable to output a failure prediction based on the plurality of feature values. Further, the method includes generating, via the trained model, a predicted failure parameter of the sample semiconductor device due to the stress condition.
Although a filesystem may be migratable, for a period of time the data blocks are on disk only. When performing system dumps, these data blocks are backed up to tape. If the data blocks are offline or dual resident, then only the inode is backed up. If all online files are made dual resident prior to performing system dumps, the dump time and the amount of resources required can be significantly reduced. The High Speed Processors group at the Numerical Aerodynamics Simulation (NAS) Facility at NASA Ames Research Center developed a tool to make all online files dual resident. The result is that a file whose data blocks are on DMF tape and still assigned to the original inode. Our 150GB filesystem used to take 8 to 12 hours to backup and used 50 to 60 tapes. Now the backup is typically under 10 tapes and completes in under 2 hours. This paper discusses this new tool and advantages gained by using it.
Efficient parallel implementations of scientific applications on multi-core CPUs with accelerators such as GPUs and Xeon Phis is challenging. This requires - exploiting the data parallel architecture of the accelerator along with the vector pipelines of modern x86 CPU architectures, load balancing, and efficient memory transfer between different devices. It is relatively easy to meet these requirements for highly structured scientific applications. In contrast, a number of scientific and engineering applications are unstructured. Getting performance on accelerators for these applications is extremely challenging because many of these applications employ irregular algorithms which exhibit data-dependent control-ow and irregular memory accesses. Furthermore, these applications are often iterative with dependency between steps, and thus making it hard to parallelize across steps. As a result, parallelism in these applications is often limited to a single step. Numerical simulation of charged particles beam dynamics is one such application where the distribution of work and memory access pattern at each time step is irregular. Applications with these properties tend to present significant branch and memory divergence, load imbalance between different processor cores, and poor compute and memory utilization. Prior research on parallelizing such irregular applications have been focused around optimizing the irregular, data-dependent memory accesses and control-ow during a single step of the application independent of the other steps, with the assumption that these patterns are completely unpredictable. We observed that the structure of computation leading to control-ow divergence and irregular memory accesses in one step is similar to that in the next step. It is possible to predict this structure in the current step by observing the computation structure of previous steps. In this dissertation, we present novel machine learning based optimization techniques to address the parallel implementation challenges of such irregular applications on different HPC architectures. In particular, we use supervised learning to predict the computation structure and use it to address the control-ow and memory access irregularities in the parallel implementation of such applications on GPUs, Xeon Phis, and heterogeneous architectures composed of multi-core CPUs with GPUs or Xeon Phis. We use numerical simulation of charged particles beam dynamics simulation as a motivating example throughout the dissertation to present our new approach, though they should be equally applicable to a wide range of irregular applications. The machine learning approach presented here use predictive analytics and forecasting techniques to adaptively model and track the irregular memory access pattern at each time step of the simulation to anticipate the future memory access pattern. Access pattern forecasts can then be used to formulate optimization decisions during application execution which improves the performance of the application at a future time step based on the observations from earlier time steps. In heterogeneous architectures, forecasts can also be used to improve the memory performance and resource utilization of all the processing units to deliver a good aggregate performance. We used these optimization techniques and anticipation strategy to design a cache-aware, memory efficient parallel algorithm to address the irregularities in the parallel implementation of charged particles beam dynamics simulation on different HPC architectures. Experimental result using a diverse mix of HPC architectures shows that our approach in using anticipation strategy is effective in maximizing data reuse, ensuring workload balance, minimizing branch and memory divergence, and in improving resource utilization.
The MULTIPAC is a central data system developed for deep-space probes with the distinctive feature that it may be repaired during flight via command and telemetry links by reprogramming around the failed unit. The computer organization uses pools of identical modules which the program organizes into one or more computers called processors. The interaction of these modules is dynamically controlled by the program rather than hardware. In the event of a failure, new programs are entered which reorganize the central data system with a somewhat reduced total processing capability aboard the spacecraft. Emphasis is placed on the evolution of the system architecture and the final overall system design rather than the specific logic design.
Emerging data-intensive applications, such as graph analytics and data mining, exhibit irregular memory access patterns. Research has shown that with these memory-bound applications, traditional cache-based processor architectures, which exploit locality and regular patterns to mitigate the memory-wall issue, are inefficient. Meantime, novel 3D-stacked memory devices, such as Hybrid Mem- ory Cube (HMC) and High Bandwidth Memory (HBM), promise significant increases in bandwidth that appear extremely appealing for memory-bound applications. However, conventional memory interfaces designed for cache-based architectures and JEDEC DDR devices fit poorly with the 3D-stacked memory, which leads to significant under-utilization of the promised high bandwidth. As a response to these issues, in this paper we propose MAC (Memory Access Coalescer), a coalescing unit for the 3D-stacked memory. We discuss the design and implementation of MAC, in the context of a custom designed cache-less architecture targeted at data-intensive, irregular applications. Through a custom simulation infrastructure based on the RISC-V toolchain, we show that MAC achieves a coalescing efficiency of 52.85% on average. It improves the performance of the memory system by 60.73% on average for a large set of irregular workloads.
This paper presents a study of the direction angle sensitivity of radar backscatter from agricultural fields. The direction angle is defined as the angle between the incident plane and the perpendicular to the field row direction. Previous studies have concentrated on comparing the backscatter of agricultural fields imaged with 0, 45, and 90 degree direction angles. In contrast, this study concentrates on the backscatter changes occurring when the direction angle is modified by a few degrees or even by fractions of a degree. This is possible by using the output of the NASA/JPL AIRSAR processor, in which sixteen independent frames are formed, each one corresponding to the same radar scene imaged with a slightly different squint angle. The studied data set is an agricultural area in La Mancha, Spain acquired in June and July 1991 during the EFEDA experiment. This paper describes the observed backscatter variations of the agricultural fields with direction angle measured at P, L, and C bands. As expected, the backscatter is maximum for a 0 degree direction angle. For several fields, the backscatter at P and L bands drops by more than 10 dB for a 5 degree change in direction angle. Furthermore, the sensitivity to the direction angle decreases with increasing vegetation. The variations in backscatter are compared with model predictions. One model, which agrees with scatterometer data, underestimates the observed backscatter variations with direction angle by more than 10 dB. It does not take into account the possible coherent component of the radar signal. We believe the strong direction sensitivity of agricultural field backscatter obtained with SAR data is due to a Bragg resonant effect, resulting in a strong coherent return when the direction angle is zero. The observations are then projected to the case of spaceborne SAR data.
Proving a propellant production plant that can process the Martian atmosphere (and soil) will provide engineers with performance and operational control data that can be used for designing next generation and flight systems for future missions.