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At least 1,513 records · Page 84

Controller and interface module for the High-Speed Data Acquisition System correlator/accumulator

One complex channel of the High-Speed Data Acquisition System (a subsystem used in the Goldstone solar system radar), consisting of two correlator modules and one accumulator module, is operated by the controller and interface module interfaces are provided to the VAX UNIBUS for computer control, monitor, and test of the controller and correlator/accumulator. The correlator and accumulator modules controlled by this module are the key digital signal processing elements of the Goldstone High-Speed Data Acquisition System. This fully programmable unit provides for a wide variety of correlation and filtering functions operating on a three megaword/second data flow. Data flow is to the VAX by way of the I/O port of a FPS 5210 array processor.

Brokl, S. S.↗

Spacecraft on-board SAR processing technology

This paper provides an assessment of the on-board SAR processing technology for Eos-type missions. The proposed Eos SAR sensor and flight data system are introduced, and the SAR processing requirements are described. The SAR on-board SAR processor architecture selection is discussed, and a baseline processor architecture using a frequency-domain processor for range correlation and a modular fault-tolerant VLSI time-domain parallel array for azimuth correlation are described. The mass storage and VLSI technologies needed for implementing the proposed SAR processing are assessed. It is shown that acceptable processor power and mass characteristics should be feasible for Eos-type applications. A proposed development strategy for the on-board SAR processor is presented.

Liu, K. Y.↗

Computational Controls Workstation: Algorithms and hardware

The Computational Controls Workstation provides an integrated environment for the modeling, simulation, and analysis of Space Station dynamics and control. Using highly efficient computational algorithms combined with a fast parallel processing architecture, the workstation makes real-time simulation of flexible body models of the Space Station possible. A consistent, user-friendly interface and state-of-the-art post-processing options are combined with powerful analysis tools and model databases to provide users with a complete environment for Space Station dynamics and control analysis. The software tools available include a solid modeler, graphical data entry tool, O(n) algorithm-based multi-flexible body simulation, and 2D/3D post-processors. This paper describes the architecture of the workstation while a companion paper describes performance and user perspectives.

Venugopal, R.↗

A parallel data management system for large-scale NASA datasets

The past decade has experienced a phenomenal growth in the amount of data and resultant information generated by NASA's operations and research projects. A key application is the reprocessing problem which has been identified to require data management capabilities beyond those available today (PRAT93). The Intelligent Information Fusion (IIF) system (ROEL91) is an ongoing NASA project which has similar requirements. Deriving our understanding of NASA's future data management needs based on the above, this paper describes an approach to using parallel computer systems (processor and I/O architectures) to develop an efficient parallel database management system to address the needs. Specifically, we propose to investigate issues in low-level record organizations and management, complex query processing, and query compilation and scheduling.

Srivastava, Jaideep↗

Issues in ATM Support of High-Performance, Geographically Distributed Computing

This report experimentally assesses the effect of the underlying network in a cluster-based computing environment. The assessment is quantified by application-level benchmarking, process-level communication, and network file input/output. Two testbeds were considered, one small cluster of Sun workstations and another large cluster composed of 32 high-end IBM RS/6000 platforms. The clusters had Ethernet, fiber distributed data interface (FDDI), Fibre Channel, and asynchronous transfer mode (ATM) network interface cards installed, providing the same processors and operating system for the entire suite of experiments. The primary goal of this report is to assess the suitability of an ATM-based, local-area network to support interprocess communication and remote file input/output systems for distributed computing.

Claus, Russell W.↗

Concurrent Probabilistic Simulation of High Temperature Composite Structural Response

A computational structural/material analysis and design tool which would meet industry's future demand for expedience and reduced cost is presented. This unique software 'GENOA' is dedicated to parallel and high speed analysis to perform probabilistic evaluation of high temperature composite response of aerospace systems. The development is based on detailed integration and modification of diverse fields of specialized analysis techniques and mathematical models to combine their latest innovative capabilities into a commercially viable software package. The technique is specifically designed to exploit the availability of processors to perform computationally intense probabilistic analysis assessing uncertainties in structural reliability analysis and composite micromechanics. The primary objectives which were achieved in performing the development were: (1) Utilization of the power of parallel processing and static/dynamic load balancing optimization to make the complex simulation of structure, material and processing of high temperature composite affordable; (2) Computational integration and synchronization of probabilistic mathematics, structural/material mechanics and parallel computing; (3) Implementation of an innovative multi-level domain decomposition technique to identify the inherent parallelism, and increasing convergence rates through high- and low-level processor assignment; (4) Creating the framework for Portable Paralleled architecture for the machine independent Multi Instruction Multi Data, (MIMD), Single Instruction Multi Data (SIMD), hybrid and distributed workstation type of computers; and (5) Market evaluation. The results of Phase-2 effort provides a good basis for continuation and warrants Phase-3 government, and industry partnership.

Abdi, Frank↗

Second International Workshop on Software Engineering and Code Design in Parallel Meteorological and Oceanographic Applications

This report contains the abstracts and technical papers from the Second International Workshop on Software Engineering and Code Design in Parallel Meteorological and Oceanographic Applications, held June 15-18, 1998, in Scottsdale, Arizona. The purpose of the workshop is to bring together software developers in meteorology and oceanography to discuss software engineering and code design issues for parallel architectures, including Massively Parallel Processors (MPP's), Parallel Vector Processors (PVP's), Symmetric Multi-Processors (SMP's), Distributed Shared Memory (DSM) multi-processors, and clusters. Issues to be discussed include: (1) code architectures for current parallel models, including basic data structures, storage allocation, variable naming conventions, coding rules and styles, i/o and pre/post-processing of data; (2) designing modular code; (3) load balancing and domain decomposition; (4) techniques that exploit parallelism efficiently yet hide the machine-related details from the programmer; (5) tools for making the programmer more productive; and (6) the proliferation of programming models (F--, OpenMP, MPI, and HPF).

OKeefe, Matthew↗

3D Navier-Stokes Time Accurate Solutions Using Multipartitioning Parallel Computation Methodology

A parallel CFD code solving 3D time accurate Navier-Stokes equations with multipartitioning parallel Methodology is being developed in collaboration with Ohio State University within the Air Vehicle Directorate, at Wright Patterson Air Force Base. The advantage of the multipartitioning parallel method is that the domain decomposition will not introduce domain boundaries for the implicit operators. A ring structure data communication is employed so that the implicit time accurate method can be implemented for multi-processors with the same accuracy as for the single processor. No sub-iteration is needed at the domain boundaries. The code has been validated for some typical unsteady flows, which include Coutte Flow, flow passing a cylinder. The code now is being employed for a large scale time accurate wall jet transient flow computation. 'ne preliminary results are promising. The mesh has been refined to capture more details of the flow field. The mesh refinement computation is in progress and would be difficult to successfully implement without the parallel computation techniques used. A modified version of the code with more efficient inversion of the diagonalized block matrix is currently being tested.

Zha, Ge-Cheng↗

Step-oriented pipeline data processing system

Architecture for step-oriented pipeline data processing is disclosed utilizing a plurality of cascaded modules, each module including a programmable general purpose processor and a read/write random access memory. The memory of each module, shared with the next module in cascade serves as an output memory for the processor and the input memory for the next processor. An additional memory is provided to serve as the input memory of the first module, and each module is provided with a memory, which may be a read-out memory, to store a program for the processor. Each module is further provided with a logic network for resolving a potential memory sharing conflict by awarding priority to the processor of the module.

Castleman, Kenneth R.↗

Compute Element and Interface Box for the Hazard Detection System

The Autonomous Landing and Hazard Avoidance Technology (ALHAT) program is building a sensor that enables a spacecraft to evaluate autonomously a potential landing area to generate a list of hazardous and safe landing sites. It will also provide navigation inputs relative to those safe sites. The Hazard Detection System Compute Element (HDS-CE) box combines a field-programmable gate array (FPGA) board for sensor integration and timing, with a multicore computer board for processing. The FPGA does system-level timing and data aggregation, and acts as a go-between, removing the real-time requirements from the processor and labeling events with a high resolution time. The processor manages the behavior of the system, controls the instruments connected to the HDS-CE, and services the "heavy lifting" computational requirements for analyzing the potential landing spots.

Villalpando, Carlos Y.↗

TES-8: Advanced Exo-Brake, VR and COM Experiments

The TES-8 was jettisoned from the International Space Station on January 31, 2019. As an orbital laboratory and 8th in on-going series, the design makes use of a standard set of interfaces and safety features that permit rapid re-flight. On this flight, an advanced Exo-Brake is flown with de-orbit targeting capability that will engender sample return capability from LEO platforms. A Virtual Reality data recording system uses stereo imaging and efficient data-compression with an NVIDIA GPU (Graphics Processing Unit) to permit compression and transmission of very large data files. An SDR (Software Defined Radio) will download data to the NEN (Near Earth Network) for the first time - demonstrating potential use in cis-lunar space using S-band. For the first time, a comparison will be made regarding the functionality of the Iridium and Globalstar short burst data modems - as essential communication tools for future nano-sat projects. Lastly, the 7 micro-processors and 4 cameras provide an excellent learning platform for university students and NASA young professionals.

Exo-Brake↗

Unattended Multiplicity Shift Register

The Unattended Multiplicity Shift Register (UMSR) is a specialized pulse counter used primarily to count neutron events originating in neutron detection instruments. While the counter can be used to count any TTL input pulses, its unique ability to record time correlated events and the multiplicity distributions of these events makes it an ideal instrument for counting neutron events in the nuclear fields of material safeguards, waste assay and process monitoring and control. The UMSR combines the Los Alamos National Laboratory (LANL) simple and robust shift register design with a Commercial-Off-The-Shelf (COTS) processor and Ethernet communications. The UMSR is fully compatible with existing International Atomic Energy Agency (IAEA) neutron data acquisition instruments such as the Advance Multiplicity Shift Register (AMSR) and JSR-15. The UMSR has three input channels: a multiplicity shift register input and two auxiliary inputs. The UMSR provides 0V to 2kV of programmable High Voltage (HV) bias and both a 12V and a 5V detector power supply output. A serial over USB communication line to the UMSR allows the use of existing versions of INCC or MIC software while the Ethernet port is compatible with the new IAEA RAINSTORM communication protocol.

Newell, Matt↗

Method of processing an image

A non-transitory computer-readable medium encoded with a computer-readable program, which when executed by a processor, will cause a computer to execute a computational method, the computational method including collecting an image data, wherein the collecting the image data comprises collecting a first plurality of RGB images and a second plurality of hyperspectral images. The method further includes orthorectifying the image data to produce an RGB based orthophoto and a partially rectified hyperspectral orthophoto. The method further includes selecting tie features from each of the RGB based orthophoto and the partially rectified hyperspectral orthophoto. Lastly, the method includes registering the features of the partially rectified hyperspectral orthophoto into the tie features of the RGB based orthophoto.

97 MATHEMATICS AND COMPUTING↗

Method of processing an image

A non-transitory computer-readable medium encoded with a computer-readable program, which when executed by a processor, will cause a computer to execute a computational method, the computational method including collecting an image data, wherein the collecting the image data comprises collecting a first plurality of RGB images and a second plurality of hyperspectral images. The method further includes orthorectifying the image data to produce an RGB based orthophoto and a partially rectified hyperspectral orthophoto. The method further includes selecting tie features from each of the RGB based orthophoto and the partially rectified hyperspectral orthophoto. Lastly, the method includes registering the features of the partially rectified hyperspectral orthophoto into the tie features of the RGB based orthophoto.

97 MATHEMATICS AND COMPUTING↗

Method of processing an image

A non-transitory computer-readable medium encoded with a computer-readable program, which when executed by a processor, will cause a computer to execute a computational method, the computational method including collecting an image data, wherein the collecting the image data comprises collecting a first plurality of RGB images and a second plurality of hyperspectral images. The method further includes orthorectifying the image data to produce an RGB based orthophoto and a partially rectified hyperspectral orthophoto. The method further includes selecting tie features from each of the RGB based orthophoto and the partially rectified hyperspectral orthophoto. Lastly, the method includes registering the features of the partially rectified hyperspectral orthophoto into the tie features of the RGB based orthophoto.

97 MATHEMATICS AND COMPUTING↗

In situ data acquisition and real-time analysis system

A testing system for evaluating the performance of an electrical/electronic UUT under dynamic operating conditions. The testing system includes a dynamic testing component (e.g., a centrifuge) for applying a stimulus to the UUT, and an iDAQ system configured to perform in situ data acquisition and real-time data analysis. The iDAQ system may also be subject to the stimulus. The iDAQ system includes a processor (e.g., an SoC) component, a power supply, a CR/I component, an IR component, and a single enclosure. The processor component may control the dynamic testing component, including varying in real-time the stimulus applied to the UUT. The processor component may include multiple input channels, and a high current/voltage subcomponent of the power supply may be configured to supply up to five hundred volts.

Benyhesan, Mohammad K.↗

Memory instruction for memory tiers

Various embodiments provide for one or more processor instructions and memory instructions that enable a memory sub-system to copy, move, or swap data across (e.g., between) different memory tiers of the memory sub-system, where each of the memory tiers is associated with different memory locations (e.g., different physical memory locations) on one or more memory devices of the memory sub-system.

Roberts, David Andrew↗

A Pervasive Parallel Processing Framework for Data Visualization and Analysis at Extreme Scale

The evolution of the computing world from teraflop to petaflop has been relatively effortless, with several of the existing programming models scaling effectively to the petascale. The migration to exascale, however, poses considerable challenges. All industry trends infer that the exascale machine will be built using processors containing hundreds to thousands of cores per chip. It can be inferred that efficient concurrency on exascale machines requires a massive amount of concurrent threads, each performing many operations on a localized piece of data. Currently, visualization libraries and applications are based off what is known as the visualization pipeline. In the pipeline model, algorithms are encapsulated as filters with inputs and outputs. These filters are connected by setting the output of one component to the input of another. Parallelism in the visualization pipeline is achieved by replicating the pipeline for each processing thread. This works well for today’s distributed memory parallel computers but cannot be sustained when operating on processors with thousands of cores. Our project investigates a new visualization framework designed to exhibit the pervasive parallelism necessary for extreme scale machines. Our framework achieves this by defining algorithms in terms of worklets, which are localized stateless operations. Worklets are atomic operations that execute when invoked unlike filters, which execute when a pipeline request occurs. The worklet design allows execution on a massive amount of lightweight threads with minimal overhead. Only with such fine-grained parallelism can we hope to fill the billions of threads we expect will be necessary for efficient computation on an exascale machine.

97 MATHEMATICS AND COMPUTING↗