Thermoelectric power factor enhancement with gate-all-around silicon nanowires
The thermoelectric properties of gate-all-around silicon nanowires (Si NWs) are calculated to determine the potential for significant power factor enhancement. The Boltzmann transport equation and relaxation time approximation are employed to develop an electron transport model used to determine the field-effect mobility, electrical conductivity, Seebeck coefficient, and power factor for Si NWs with cross-sectional areas between 4 nm × 4 nm and 12 nm × 12 nm and a range of gate biases. Electrical conductivity for the gated Si NWs was much higher than that of doped Si due to the lack of ionized impurities and correspondingly greater carrier mobility. A significant increase in electrical conductivity with decreasing Si NW cross-sectional area was also observed due to a large increase in the average carrier density. For all Si NWs, the Seebeck coefficient was lower than that of doped bulk Si due to the different energy dependence between ionized impurity and phonon-mediated scattering processes. This decrease was also confirmed with Seebeck coefficient measurements of multigated Si NWs and n-type Si thin-films. Quantum confinement was also found to increase the Seebeck coefficient for <8 nm × 8 nm Si NWs and also at high charge densities. A maximum power factor of 6.8 × 10{sup −3} W m{sup −1} K{sup −2} was calculated for the 6 nm × 6 nm Si NWs with typical Si/SiO{sub 2} interface roughness, which is 2–3 × those obtained experimentally for bulk Si. The power factor was also found to greatly depend on surface roughness, with a root-mean-square roughness of <0.8 nm necessary for power factor enhancement. An increase in ZT may also be possible if a low thermal conductivity can be obtained with minimal surface roughness.