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At least 1,459 records · Page 81

Towards Superior Software Portability with SHAD and HPX C++ Libraries

As hardware architectures and software stacks complexity grows, development productivity, performance and software portability, quickly evolve from desirable features to actual needs. SHAD, the Scalable High-performance Algorithms and Data-structures C++ library is designed to mitigate these issues: it provides general purpose building blocks as well as high-level custom utilities, and offers a shared-memory programming abstraction which facilitates the programming of complex systems, scaling up to High Performance Computing clusters. SHAD’s portability is achieved through an abstract runtime interface, which decouples the upper layers of the library and hides the low level details of the underlying architecture. This layer enables SHAD to interface with different runtime/threading systems, e.g. Intel TBB and Global Memory and Threading (GMT). However, current backends targeting distributed systems, rely on a centralized controller which may possibly limit scalability up to hundreds of nodes and creates a network hot spot due to all to one communication for synchronization, and possibly resulting in degraded performance at high process counts. In this research, we explore HPX, the C++ standard library for parallelism and concurrency, as an additional backend in support of the SHAD library, and present the methodologies in support of local and remote task executions in SHAD with respect to HPX. Finally, we evaluate the proposed system by comparing against existing backends of SHAD and analyzing their performance on C++ Standard Template Library algorithms.

Wu, Nanmiao↗

Graph-Based Dynamic Assignment Of Multiple Processors

Algorithm-to-architecture mapping model (ATAMM) is strategy minimizing time needed to periodically execute graphically described, data-driven application algorithm on multiple data processors. Implemented as operating system managing flow of data and dynamically assigns nodes of graph to processors. Predicts throughput versus number of processors available to execute given application algorithm. Includes rules ensuring application algorithm represented by graph executed periodically without deadlock and in shortest possible repetition time. ATAMM proves useful in maximizing effectiveness of parallel computing systems.

Hayes, Paul J.↗

VLSI architectures for geometrical mapping problems in high-definition image processing

This paper explores a VLSI architecture for geometrical mapping address computation. The geometric transformation is discussed in the context of plane projective geometry, which invokes a set of basic transformations to be implemented for the general image processing. The homogeneous and 2-dimensional cartesian coordinates are employed to represent the transformations, each of which is implemented via an augmented CORDIC as a processing element. A specific scheme for a processor, which utilizes full-pipelining at the macro-level and parallel constant-factor-redundant arithmetic and full-pipelining at the micro-level, is assessed to produce a single VLSI chip for HDTV applications using state-of-art MOS technology.

Kim, K.↗

Power Actuation and Switching Module Test Results

The X2000 Power System Electronics (PSE) is a Jet Propulsion Laboratory (JPL) task to develop a new generation of power system building blocks for use on future deep-space missions. The effort includes the development of electronic components and modules that can be used as building blocks in the design of generic spacecraft power systems. All X2000 avionics components and modules are designed for use in centralized or distributed spacecraft architectures. The Power Actuation and Switching Module (PASM) has been developed under the X2000 program. This component enables a modular and scalable design approach for power switching applications, which can result in a wide variety of power switching architectures using this simple building block. The PASM is designed to provide most of the necessary power switching functions of spacecraft for various Deep Space missions including future missions to Mars, comets, Jupiter and its moons. It is fabricated using an ASIC process that is tolerant of high radiation. The development included two application specific integrated circuits (ASICs) and support circuitry all packaged using High Density Interconnect (HDI) technology. It can be operated in series or parallel with other PASMs. It can be used as a high-side or low-side switch and it can drive thruster valves, pyrotechnic devices such as NASA standard initiators, bus shunt resistors, and regular spacecraft component loads. Each PASM contains two independent switches with internal current limiting and over-current trip-off functions to protect the power subsystem from load faults. During turnon and turnoff each switch can limit the rate of current change (di/dt) to a value determined by the user. Three-way majority-voted On/Off commandability and full switch status telemetry (both analog and digital) are built into the module. This paper is a follow up to the one presented at he IECEC 2004 conference that will include the lessons learned and test results from the development.

X2000↗

Pattern Identification - A Foundation for Research in the Emphasis of Design Patterns in Systems Engineering and Knowledge Capture

Pattern Language describes the morphology and functionality of a system in the absence of design particulars. Harnessing this capability will provide the Systems Engineering discipline a means of managing the development of increasingly complex systems with increasingly distributed design teams while capturing and retaining knowledge for future generations. Pattern Language is a syntax for describing, and structurally relating, design patterns. Design patterns contextually describe the application of domain knowledge in the engineered solution to the force balance problem. The parallels between pattern recognition and application, as a fundamental stage of human learning, and pattern observation within a complex system, suggests pattern language may be a valuable tool in the capture and dissemination of knowledge. Pattern application has enjoyed considerable study over the last several decades, however much of this work has focused on the replication of design particulars. This work returns to the roots of Pattern Language and explores the utility of patterns as an architectural description and guide, and knowledge capture method, for complex system development beginning with the identification of a time proven design pattern.

Russell, Samuel P.↗

Sparse Symmetric Format for Tucker Decomposition

Tensor-based methods are receiving renewed attention in recent years due to their prevalence in diverse real-world applications. There is considerable literature on tensor representations and algorithms for tensor decompositions, both for dense and sparse tensors. Many applications in hypergraph analytics, machine learning, psychometry, and signal processing result in tensors that are both sparse and symmetric, making them an important class for further study. Similar to the critical Tensor Times Matrix chain operation (TTM c ) in general sparse tensors, the $\underline{S}$ parse $\underline{S}$ ymmetric $\underline{T}$ ensor $\underline{T}$ imes $\underline{S}$ ame $\underline{M}$ atrix $\underline{c}$ hain (S 3 TTM c ) operation is compute and memory intensive due to high tensor order and the associated factorial explosion in the number of non-zeros. We present the novel Compressed Sparse Symmetric (CSS) format for sparse symmetric tensors, along with an efficient parallel algorithm for the S 3 TTM c operation. We theoretically establish that S 3 TTM c on CSS achieves a better memory versus run-time trade-off compared to state-of-the-art implementations, and visualize the variation of the performance gap over the parameter space. We demonstrate experimental findings that confirm these results and achieve up to 2.72× speedup on synthetic and real datasets. The scaling of the algorithm on different test architectures is also showcased to highlight the effect of machine characteristics on algorithm performance.

42 ENGINEERING↗

User Manual - HydraGNN v5.0: Distributed Implementation of Multi-Tasking Graph Neural Networks

This document serves as the user manual for HydraGNN v5.0, a scalable graph neural network (GNN) architecture for simultaneous prediction of multiple target properties using multi-task learning (MTL). This version of HydraGNN has been developed primarily to support the development, training, and deployment of predictive graph-based deep learning (DL) models for atomistic materials modeling. HydraGNN is templated over 13 message-passing policies, including invariant models (GIN, PNA, PNAPlus, GAT, MFC, CGCNN, SAGE, SchNet, DimeNet) and equivariant models (EGNN, PNAEq, PAINN, MACE), and supports distributed training via distributed data parallelism (DDP), DeepSpeed, and Fully Sharded Data Parallelism (FSDP) on leadership-class supercomputers. Although HydraGNN can be applied to problems beyond atomistic materials modeling, its current use is confined to homogeneous graphs. Additional capabilities include machine-learned interatomic potentials with energy-conserving forces, General, Powerful, and Scalable Graph Transformer (GraphGPS) global attention, periodic boundary conditions, hyperparameter optimization, mixed-precision training, and uncertainty quantification.

97 MATHEMATICS AND COMPUTING↗

Wideband arrays with variable element sizes

A new planar array architecture based on adding half-sized elements in between the other elements in order to extend the frequency by one octave is proposed and validated. This wideband array with variable element sizes (WAVES) antenna is shown by calculations and by measurements using Archimedean spirals to be the elements necessary to maintain a simple clean mainbeam and principal plane sidelobes below about -10 dB over two octaves. In spite of using a test antenna with a simple parallel feed and no impedance matching or isolation, the agreement between predicted and measured results is good.

Shively, D. G.↗

High performance computing applications in neurobiological research

The human nervous system is a massively parallel processor of information. The vast numbers of neurons, synapses and circuits is daunting to those seeking to understand the neural basis of consciousness and intellect. Pervading obstacles are lack of knowledge of the detailed, three-dimensional (3-D) organization of even a simple neural system and the paucity of large scale, biologically relevant computer simulations. We use high performance graphics workstations and supercomputers to study the 3-D organization of gravity sensors as a prototype architecture foreshadowing more complex systems. Scaled-down simulations run on a Silicon Graphics workstation and scale-up, three-dimensional versions run on the Cray Y-MP and CM5 supercomputers.

Ross, Muriel D.↗

Multidisciplinary High-Fidelity Analysis and Optimization of Aerospace Vehicles: Formulation - Part 1

An objective of the High Performance Computing and Communication Program at the NASA Langley Research Center is to demonstrate multidisciplinary shape and sizing optimization of a complete aerospace vehicle configuration by using high-fidelity, finite element structural analysis and computational fluid dynamics aerodynamic analysis in a distributed, heterogeneous computing environment that includes high performance parallel computing. A software system has been designed and implemented to integrate a set of existing discipline analysis codes, some of them computationally intensive, into a distributed computational environment for the design of a highspeed civil transport configuration. The paper describes the engineering aspects of formulating the optimization by integrating these analysis codes and associated interface codes into the system. The discipline codes are integrated by using the Java programming language and a Common Object Request Broker Architecture (CORBA) compliant software product. A companion paper presents currently available results.

Walsh, J. L.↗

Power Actuation and Switching Module Development

The Deep Space Avionics (DSA) Project is developing a Power Actuation and Switching Module (PASM). This component enables a modular and scalable design approach for power switching applications, which can result in a wide variety of power switching architectures using this simple building block. The PASM is designed to provide most of the necessary power switching functions of spacecraft for various Deep Space missions including future missions to Mars, comets, Jupiter and its moons. It is fabricated using an A SIC process that is tolerant of high radiation. The development includes two application specific integrated circuits (ASICs) and support circuitry all packaged using High Density Interconnect (HDI) technology. It can be operated in series or parallel with other PASMs, It can be used as a high-side or low-side switch and it can drive thruster valves, pyrotechnic devices such as NASA standard initiators, bus shunt resistors, and regular spacecraft component loads. Each PASM contains two independent switches with internal current limiting and over-current trip-off functions to protect the power subsystem from load faults. During turnon and turnoff each switch can limit the rate of current change (di/dt) to a value determined by the user. Threeway majority-voted On/Off commandability and full switch status telemetry (both analog and digital) are built into the module. This paper describes the development process used to design, model, fabricate, and test these compact and versatile power switches. Preliminary test results from prototype HDI PASM hardware are also discussed.

Power Actuation and Switching Module (PASM)↗

Twisted-layer boron nitride ceramic with high deformability and strength

Moiré superlattices formed by twisted stacking in van der Waals materials have emerged as a new platform for exploring the physics of strongly correlated materials and other emergent phenomena. However, there remains a lack of research on the mechanical properties of twisted-layer van der Waals materials, owing to a lack of suitable strategies for making three-dimensional bulk materials. Here we report the successful synthesis of a polycrystalline boron nitride bulk ceramic with high room-temperature deformability and strength. This ceramic, synthesized from an onion-like boron nitride nanoprecursor with conventional spark plasma sintering and hot-pressing sintering, consists of interlocked laminated nanoplates in which parallel laminae are stacked with varying twist angles. The compressive strain of this bulk ceramic can reach 14% before fracture, about one order of magnitude higher compared with traditional ceramics (less than 1% in general), whereas the compressive strength is about six times that of ordinary hexagonal boron nitride layered ceramics. The exceptional mechanical properties are due to a combination of the elevated intrinsic deformability of the twisted layering in the nanoplates and the three-dimensional interlocked architecture that restricts deformation from propagating across individual nanoplates. The advent of this twisted-layer boron nitride bulk ceramic opens a gate to the fabrication of highly deformable bulk ceramics.

36 MATERIALS SCIENCE↗

Scaling comb-driven resonator-based DWDM silicon photonic links to multi-Tb/s in the multi-FSR regime

The use of chip-based micro-resonator Kerr frequency combs in conjunction with dense wavelength-division multiplexing (DWDM) enables massively parallel intensity-modulated direct-detection data transmission with low energy consumption. Resonator-based modulators and filters used in such systems can limit the number of usable wavelength channels due to practical constraints on the maximum achievable free spectral range (FSR). In this work, we introduce the design of multi-Tb/s comb-driven resonator-based silicon photonic links by leveraging the multi-FSR regime. We demonstrate the viability of the link architecture with yield estimates that are supported by extensive wafer-scale measurements of 704 micro-resonators fabricated in a commercial complementary metal–oxide–semiconductor foundry. We show that a 2.80 Tb/s link is realizable with a ≥6 σ yield (∼99.999%), and that aggregate bandwidths of 3.76 Tb/s and 4.72 Tb/s are possible if yield targets are relaxed (3 σ and 1 σ , respectively). All designs represent a 1.94−3.28× boost to aggregate link bandwidth while maintaining BER≤10 −10 performance, with a theoretical bandwidth of 10.51 Tb/s being possible for sufficiently robust resonators. We use high-speed BER measurements to inform co-optimization of data rate and aggressor spacing ( λ ag ), limiting any additional loss-based power penalties to off-resonance insertion loss (IL) and routing loss. This work demonstrates that, through the multi-FSR regime, there is a clear path toward Kerr comb-driven ultra-broadband, high bandwidth silicon photonic links that can support next-generation data centers and high-performance computers.

James, Aneek (ORCID:0000000262527807)↗

Mechanical Properties of Triaxial Braided Carbon/Epoxy Composites

In an on-going effort to increase the safety and efficiency of turbine engines, the National Aeronautics and Space Administration is exploring lightweight alternatives to the metal containment structures that currently encase commercial jet engines. Epoxy reinforced with braided carbon fibers is a candidate structural material which may be suitable for an engine case. This paper reports flat-coupon mechanical-property experiments performed to compliment previously reported subcomponent impact testing and analytical simulation of containment structures. Triaxial-braid T700/5208 epoxy and triaxial-braid T700h436 toughened epoxy composites were evaluated. Also, two triaxial-braid architectures (0 degrees plus or minus 60 degrees, and 0 degrees plus or minus 45 degrees) with the M36 resin were evaluated through tension, compression, and shear testing. Tensile behavior was compared between standard straight-sided specimens (ASTM D3039) and bow-tie specimens. Both double-notch shear (ASTM D3846) and Iosepescu (ASTM D5379) tests were performed as well. The M36/O degrees plus or minus 45 degrees configuration yield the best response when measurements were made parallel to the axial tows. Conversely, the M36/0 degrees plus or minus 60 degrees configuration was best when measurements were made perpendicular to the axial tows. The results were used to identify critical properties and to augment the analysis of impact experiments.

Bowman, C. L.↗

Multidisciplinary High-Fidelity Analysis and Optimization of Aerospace Vehicles: Preliminary Results - Part 2

An objective of the High Performance Computing and Communication Program at the NASA Langley Research Center is to demonstrate multidisciplinary shape and sizing optimization of a complete aerospace vehicle configuration by using high-fidelity finite-element structural analysis and computational fluid dynamics aerodynamic analysis in a distributed, heterogeneous computing environment that includes high performance parallel computing. A software system has been designed and implemented to integrate a set of existing discipline analysis codes, some of them computationally intensive, into a distributed computational environment for the design of a high-speed civil transport configuration. The paper describes both the preliminary results from implementing and validating the multidisciplinary analysis and the results from an aerodynamic optimization. The discipline codes are integrated by using the Java programming language and a Common Object Request Broker Architecture compliant software product. A companion paper describes the formulation of the multidisciplinary analysis and optimization system.

Walsh, J. L.↗

SALT: The Simulator for the Analysis of LWP Timing

With the emergence of new processor architectures that are highly multithreaded, and support features such as full/empty memory semantics and split-phase memory transactions, the need for a processor simulator to handle these features becomes apparent. This paper describes such a simulator, called SALT.

simulation↗

Evaluation of Graph Analytics Frameworks Using the GAP Benchmark Suite

The analysis of connected data is an increasingly important application in high-performance computing. Such analyses can reveal fraudulent patterns in financial transactions, optimize telecommunications networks, predict information flow in social networks, etc. However, the landscape of graph analytics is highly diverse. Graph algorithms stress processor architectures differently, and no one graph can represent all topologies. Consequently, no single approach or framework is expected to be optimal for all graph analytics problems. To help make sense of this diverse landscape, we evaluated four approaches to graph analytics: GraphBLAS, Galois, BGL17, GraphIt; and compare them against hand-tuned implementations that take advantage of hardware features on our test platform. Graph- BLAS formulates graph analytics as sparse linear algebra. Galois provides syntactic constructs for data parallelism over irregular data structures. BGL17 is a generic C++ template library for implementing graph algorithms. GraphIt provides a domain- specific language to describe and optimize graph algorithms. We use the GAP Benchmark Suite to establish baseline performance and guide the side-by-side evaluation of each framework. GAP consists of 30 tests: six graph analytics algorithms (breadth- first search, single-source shortest path, PageRank, betweenness centrality, connected components, and triangle counting) run on five graphs, each with different topological characteristics (e.g., high diameter, skewed degree distribution, high average degree). High-performance reference implementations are included for each benchmark algorithm. Because a graph can be loaded into memory a number of ways (e.g., flat file on disk, compressed sparse format, data frames, retrieved from SQL or NoSQL databases), our evaluation focused on computational performance rather than I/O. Our results show the relative strengths of each framework.

Graph algorithms, Benchmarking, shared-memory prog↗

VTO FY20Q4 quarterly report

Project Objective.This project has three objectives: (1) tuning microstructures of 3D-printed SSE separators,(2) determining material and processing compatibilities with cathode printing,and (3)3D printing of sintering-free SSE separators.Project Impact.All-solid-state lithium batteries are difficult to process due to the brittleness of ceramic materials, poor solid-solid contact, and electrolyte-electrode stability issues. As a result, the energy and power density and also cycling stability are far from satisfying. This project will address fabrication difficulties by using state-of-the-art 3D-printing techniques that can introduce 3D interfaces and architectures to enhance solid-solid contact and reduce charge transfer resistance. Success will benefit the DOE by establishing the best manufacturing methods for ASSBsto achieve VTO goals on the performance of beyond Li-ion batteries. Approach.The project employs 3D-printing techniques to manufacture SSEs and related components for ASSBs. The team starts with direct ink writing (DIW) to develop ink recipes with desired rheological properties and explore post-sintering approaches to achieve high densification. In parallel with DIW3D printing, the team also explores other 3D printing options, such as projection microstereolithography (PuSL). Both sintering and sintering-free approaches can gain benefit from 3D printing and therefore will be investigated.Out-Year Goals.The team will determine particle sizes and morphologies as well as post-processing conditions that deliver good ionic conductivity and charge transfer properties of LLZTO separators. They will examine co-sintering of LLZTO/cathode and determine the effects of material, particle size, surface coating, and sintering conditions.Collaborations.Microstructures, ionic conductivities, and mechanical properties will be provided to the LLNL simulation team, led by PI B. Wood, for establishing and validating phase-field modeling methods.

36 MATERIALS SCIENCE↗