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NASA NTRS1992

Unsteady turbomachinery flow simulations on massively parallel architectures

The accurate numerical simulation of unsteady, three-dimensional viscous flow in turbomachines is computationally very intensive, requiring prohibitively large amounts of computer time on current vector supercomputers. In recent years, computer systems based on massively parallel architectures have been developed that offer the promise of meeting the computational power requirements of such large-scale simulations. However, a rethinking of existing algorithms and methodology is required in order to fully harness the computational power of such architectures. In this paper the capabilities of the Connection Machine (CM-2) in predicting unsteady flows in turbomachines are evaluated. The implementation on the CM-2 of an implicit, time-accurate, zonal algorithm for the Navier-Stokes equations in two dimensions is described. Programming issues and modifications made to the original algorithm (developed for vector, pipelined supercomputers) in order to improve performance on the CM-2 are outlined. Algorithm performance is evaluated and compared with a functionally equivalent code for the CRAY-YMP.

Madavan, N. K.↗

NASA NTRS1993

System architecture for asynchronous multi-processor robotic control system

The architecture for the Modular Telerobot Task Execution System (MOTES) as implemented in the Supervisory Telerobotics (STELER) Laboratory is described. MOTES is the software component of the remote site of a local-remote telerobotic system which is being developed for NASA for space applications, in particular Space Station Freedom applications. The system is being developed to provide control and supervised autonomous control to support both space based operation and ground-remote control with time delay. The local-remote architecture places task planning responsibilities at the local site and task execution responsibilities at the remote site. This separation allows the remote site to be designed to optimize task execution capability within a limited computational environment such as is expected in flight systems. The local site task planning system could be placed on the ground where few computational limitations are expected. MOTES is written in the Ada programming language for a multiprocessor environment.

Steele, Robert D.↗

NASA NTRS1992

The application of Open System Architecture to planetary surface systems

The issues that future planet surface activities must confront are explored, the basic concepts that provide the basis for establishing an Open System Architecture (OSA) are defined, the appropriate features of such an architecture are identified, and examples of OSAs are discussed. OSAs are designed to provide flexibility and evolutionary growth of planet surface systems to support the users needs. An OSA is based on two fundamental principles: precise definition of component functionality and the establishment of standards. An OAS must be functionally decomposed, top down, to identify all functions, subfunctions, subsubfunctions, etc., that are required to be performed by the system. There is an allocation of function, or process, to components. The functional packaging within a component becomes the user's primary perception of the system. The standards of an OSA enable the user to attain the full functional capabilities inherent in the system.

Petri, D. A.↗

NASA NTRS1993

The use of CMAC neural architectures in obstacle avoidance

In this paper, CMAC neural architectures are used in conjunction with a hierarchical planning approach to find collision free paths over two dimensional analog valued obstacle fields. The method constructs a coarse resolution version of the original problem and then finds the corresponding coarse optimal path using multipass dynamic programming. CMAC artificial neural architectures are used to estimate the analog transition costs that dynamic programming requires. The coarse optimal path is then used as a baseline for the construction of a fine scale optimal path through the original obstacle array.

Peterson, James K.↗

NASA NTRS1993

The application of multiple instruction retry to VLIW architectures using compiler generated hazard-free code

In this paper, we describe the development of compiler assisted multiple instruction word retry for VLIW architectures. Compiler generated hazard-free code with different degrees of rollback capability is compacted by a trace scheduling algorithm. Performances are compared under three parameters: N, the rollback distance for uni-processors; P, the number of functional units; and Np, the rollback distance for VLIW architectures. In the majority of benchmarks examined, for fixed P and Np, the larger N tends to generate compacted code with better performance.

Chen, Shyh-Kwei↗

NASA NTRS1987

The Massively Parallel Processor: Architecture and application

The massively parallel processor (MPP) has a simple, yet elegant architecture. Some have granted that it is novel, and other have claimed it to be fundamental. Whichever is the case, it has shown itself to be both useful and practical. Its hardware embodiment consumes relatively low power compared to other supercomputers, does not require special cooling, has an instruction cycle time that is relatively long, thus allowing it to avoid high speed technologies, and yet it competes respectably with any currently available supercomputer in speed of execution of applications. Due to the efficiency of the architecture, ease of construction and variety of applications, it is conceivable that within a few years computational accelerators more powerful than the MPP will be available at reasonable cost to be placed inside desktop workstations.

Dorband, John E.↗

NASA NTRS1987

Applicative architectures for fault-tolerant multiprocessors

Functional programming frameworks for the design of highly reliable multiprocessor systems are proposed. In contrast to imperative programming environments, a functional environment offers elegant, relatively simple, and efficient solutions to concurrent error detection and recovery problems in multiprocessors. Specific fault tolerance mechanisms for upset exposure, fault containment, secure task assignment, and recovery are developed for a class of applicative multiprocessor architectures. Verification of abstract behavioral characteristics of applicative tasks is used for exposing faults during the execution of tasks. The fault containment mechanism is based on isolation of stack and heap segments of tasks. A protocol for secure task assignment is defined between system components. The architecture permits incremental, distributed, and asynchronous backups of system state. Finally, recovery is accomplished, even in the worst cases, by re-execution of a small number of tasks.

Sharma, Madhumitra↗

NASA NTRS1992

STGT program: Ada coding and architecture lessons learned

STGT (Second TDRSS Ground Terminal) is currently halfway through the System Integration Test phase (Level 4 Testing). To date, many software architecture and Ada language issues have been encountered and solved. This paper, which is the transcript of a presentation at the 3 Dec. meeting, attempts to define these lessons plus others learned regarding software project management and risk management issues, training, performance, reuse, and reliability. Observations are included regarding the use of particular Ada coding constructs, software architecture trade-offs during the prototyping, development and testing stages of the project, and dangers inherent in parallel or concurrent systems, software, hardware, and operations engineering.

Usavage, Paul↗

NASA NTRS1993

Destination-directed, packet-switched architecture for a geostationary communications satellite network

A major goal of the Digital Systems Technology Branch at the NASA Lewis Research Center is to identify and develop critical digital components and technologies that either enable new commercial missions or significantly enhance the performance, cost efficiency, and/or reliability of existing and planned space communications systems. NASA envisions a need for low-data-rate, interactive, direct-to-the-user communications services for data, voice, facsimile, and video conferencing. The network would provide enhanced very-small-aperture terminal (VSAT) communications services and be capable of handling data rates of 64 kbps through 2.048 Mbps in 64-kbps increments. Efforts have concentrated heavily on the space segment; however, the ground segment has been considered concurrently to ensure cost efficiency and realistic operational constraints. The focus of current space segment developments is a flexible, high-throughput, fault-tolerant onboard information-switching processor (ISP) for a geostationary satellite communications network. The Digital Systems Technology Branch is investigating both circuit and packet architectures for the ISP. Destination-directed, packet-switched architectures for geostationary communications satellites are addressed.

Ivancic, William D.↗

NASA NTRS1992

Software design by reusing architectures

Abstraction fosters reuse by providing a class of artifacts that can be instantiated or customized to produce a set of artifacts meeting different specific requirements. It is proposed that significant leverage can be obtained by abstracting software system designs and the design process. The result of such an abstraction is a generic architecture and a set of knowledge-based, customization tools that can be used to instantiate the generic architecture. An approach for designing software systems based on the above idea are described. The approach is illustrated through an implemented example, and the advantages and limitations of the approach are discussed.

Bhansali, Sanjay↗

NASA NTRS1993

On-board B-ISDN fast packet switching architectures. Phase 1: Study

The broadband integrate services digital network (B-ISDN) is an emerging telecommunications technology that will meet most of the telecommunications networking needs in the mid-1990's to early next century. The satellite-based system is well positioned for providing B-ISDN service with its inherent capabilities of point-to-multipoint and broadcast transmission, virtually unlimited connectivity between any two points within a beam coverage, short deployment time of communications facility, flexible and dynamic reallocation of space segment capacity, and distance insensitive cost. On-board processing satellites, particularly in a multiple spot beam environment, will provide enhanced connectivity, better performance, optimized access and transmission link design, and lower user service cost. The following are described: the user and network aspects of broadband services; the current development status in broadband services; various satellite network architectures including system design issues; and various fast packet switch architectures and their detail designs.

Faris, Faris↗

NASA NTRS1993

A novel VLSI processor architecture for supercomputing arrays

Design of the processor element for general purpose massively parallel supercomputing arrays is highly complex and cost ineffective. To overcome this, the architecture and organization of the functional units of the processor element should be such as to suit the diverse computational structures and simplify mapping of complex communication structures of different classes of algorithms. This demands that the computation and communication structures of different class of algorithms be unified. While unifying the different communication structures is a difficult process, analysis of a wide class of algorithms reveals that their computation structures can be expressed in terms of basic IP,IP,OP,CM,R,SM, and MAA operations. The execution of these operations is unified on the PAcube macro-cell array. Based on this PAcube macro-cell array, we present a novel processor element called the GIPOP processor, which has dedicated functional units to perform the above operations. The architecture and organization of these functional units are such to satisfy the two important criteria mentioned above. The structure of the macro-cell and the unification process has led to a very regular and simpler design of the GIPOP processor. The production cost of the GIPOP processor is drastically reduced as it is designed on high performance mask programmable PAcube arrays.

Venkateswaran, N.↗

NASA NTRS1993

Space Generic Open Avionics Architecture (SGOAA) standard specification

The purpose of this standard is to provide an umbrella set of requirements for applying the generic architecture interface model to the design of a specific avionics hardware/software system. This standard defines a generic set of system interface points to facilitate identification of critical interfaces and establishes the requirements for applying appropriate low level detailed implementation standards to those interface points. The generic core avionics system and processing architecture models provided herein are robustly tailorable to specific system applications and provide a platform upon which the interface model is to be applied.

Wray, Richard B.↗

NASA NTRS1993

Architectures and protocols for an integrated satellite-terrestrial mobile system

This paper aims to depict some basic concepts related to the definition of an integrated system for mobile communications, consisting of a satellite network and a terrestrial cellular network. In particular three aspects are discussed: (1) architecture definition for the satellite network; (2) assignment strategy of the satellite channels; and (3) definition of 'internetworking procedures' between cellular and satellite network, according to the selected architecture and the satellite channel assignment strategy.

Delre, E.↗

NASA NTRS1994

A Novel Approach to Noise-Filtering Based on a Gain-Scheduling Neural Network Architecture

A gain-scheduling neural network architecture is proposed to enhance the noise-filtering efficiency of feedforward neural networks, in terms of both nominal performance and robustness. The synergistic benefits of the proposed architecture are demonstrated and discussed in the context of the noise-filtering of signals that are typically encountered in aerospace control systems. The synthesis of such a gain-scheduled neurofiltering provides the robustness of linear filtering, while preserving the nominal performance advantage of conventional nonlinear neurofiltering. Quantitative performance and robustness evaluations are provided for the signal processing of pitch rate responses to typical pilot command inputs for a modern fighter aircraft model.

Troudet, T.↗

NASA NTRS1994

The Nomad Explorer assembly assist vehicle: An architecture for rapid global extraterrestrial base infrastructure establishment

Traditional concepts of lunar bases describe scenarios where components of the bases are landed on the lunar surface, one at a time, and then put together to form a complete stationary lunar habitat. Recently, some concepts have described the advantages of operating a mobile or 'roving' lunar base. Such a base vastly improves the exploration range from a primary lunar base. Roving bases would also allow the crew to first deploy, test, operationally certify, and then regularly maintain, service, and evolve long life-cycle facilities like observatories or other science payload platforms that are operated far apart from each other across the extraterrestrial surface. The Nomad Explorer is such a mobile lunar base. This paper describes the architectural program of the Nomad Explorer, its advantages over a stationary lunar base, and some of the embedded system concepts which help the roving base to speedily establish a global extraterrestrial infrastructure. A number of modular autonomous logistics landers will carry deployable or erectable payloads, service, and logistically resupply the Nomad Explorer at regular intercepts along the traverse. Starting with the deployment of science experiments and telecommunication networks, and the manned emplacement of a variety of remote outposts using a unique EVA Bell system that enhances manned EVA, the Nomad Explorer architecture suggests the capability for a rapid global development of the extraterrestrial body. The Moon and Mars are candidates for this 'mission oriented' strategy. The lunar case is emphasized in this paper.

Thangavelu, Madhu↗

NASA NTRS1994

Software architecture standard for simulation virtual machine, version 2.0

The Simulation Virtual Machine (SBM) is an Ada architecture which eases the effort involved in the real-time software maintenance and sustaining engineering. The Software Architecture Standard defines the infrastructure which all the simulation models are built from. SVM was developed for and used in the Space Station Verification and Training Facility.

Sturtevant, Robert↗

NASA NTRS1993

Standards in the architectural effort

The NASA Scientific and Technical Information (STI) Project Architecture Group was established to build a framework for modernization, provide guidance and direction for standardization and integration efforts, and to develop a set of concepts, interfaces, and entities to specifiy standards. The STI data processing architecture is a set of diagrams and descriptions that characterize the principal functions and services as well as hardware and software components. The use of standards promotes scalability and interchangeability.

Markham, Howard↗