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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,441 records · Page 80

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NASA NTRS1991

A RAM architecture for concurrent access and on-chip testing

A novel RAM architecture supporting concurrent memory access and on-chip testing (CMAT) is proposed. A large-capacity memory chip is decomposed into test neighborhoods (TNDs), each of which is tested independently. When there are data stored in a TND, the data are saved into a buffer before testing the TND, and the TND's contents are restored using buffered data after testing the TND. If an external request is not made to the TND, the request can be directed to the addressed memory cells. Otherwise, the buffered data can be loaded back into the TND, or the request is detoured to a corresponding buffer. By deriving an analytical model, the performance penalty and hardware overhead of the CMAT architecture are shown to be very small.

Liu, Jyh-Charn↗

NASA NTRS1991

Options for a lunar base surface architecture

The analysis of the Space Exploration Initiative architectures involves making definitions of systems engineering designs for the construction of lunar and Mars bases for the support of science, exploration, and resource production on these planets. This paper discusses the results of the Space Resource Utilization Architecture study, which was initiated to develop the technical capability for extracting useful materials from the indigenous resources of the moon and Mars. For the moon, an infrastructure concept of a base is designed which can support a crew of 12. The major phases of the lunar-base development, the systems and the elements involved, and the physical layout and evolution of the base are described.

Roberts, Barney B.↗

NASA NTRS1991

Architecture, performance, and implementation of the tandem banyan fast packet switch

The authors propose a space-division fast packet switch architecture based on banyan interconnection networks, called the tandem banyan switching fabric. It consists of placing banyan networks in tandem, offering multiple paths from each input to each output, thus overcoming in a very simple way the effect of conflicts among packets (to which banyan networks are prone) and achieving output buffering. From a hardware implementation perspective, this architecture is simple in that it consists of several instances of only two VLSI chips, one implementing the banyan network and the other implementing the output buffer function. The basic structure and operation of the tandem banyan switching fabric are described, and its performance is discussed. The authors propose a modification to the basic structure which decreases the hardware complexity of the switch while maintaining its performance. An implementation of the banyan network using a high-performance BiCMOS sea-of-gates on 0.8-micron technology is reported.

Tobagi, Fouad A.↗

NASA NTRS1992

On-board processing satellite network architectures for broadband ISDN

Onboard baseband processing architectures for future satellite broadband integrated services digital networks (B-ISDN's) are addressed. To assess the feasibility of implementing satellite B-ISDN services, critical design issues, such as B-ISDN traffic characteristics, transmission link design, and a trade-off between onboard circuit and fast packet switching, are analyzed. Examples of the two types of switching mechanisms and potential onboard network control functions are presented. A sample network architecture is also included to illustrate a potential onboard processing system.

Inukai, Thomas↗

NASA NTRS1992

Network architectures and protocols for the integration of ACTS and ISDN

A close integration of satellite networks and the integrated services digital network (ISDN) is essential for satellite networks to carry ISDN traffic effectively. This also shows how a given (pre-ISDN) satellite network architecture can be enhanced to handle ISDN signaling and provide ISDN services. It also describes the functional architecture and high-level protocols that could be implemented in the NASA Advanced Communications Technology Satellite (ACTS) low burst rate communications system to provide ISDN services.

Chitre, D. M.↗

NASA NTRS1992

A VLSI architecture for simplified arithmetic Fourier transform algorithm

The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical FFT in terms of accuracy, complexity, and speed. Theorems developed in a previous paper for the AFT algorithm are used here to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A VLSI architecture is suggested for this simplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25 percent of that used in the direct method.

Reed, Irving S.↗

NASA NTRS1992

Microwave systems applications in deep space telecommunications and navigation - Space Exploration Initiative architectures

The general support requirements of a typical SEI mission set, along with the mission operations objectives and related telecommunications, navigation, and information management (TNIM) support infrastructure options are described. Responsive system architectures and designs are proposed, including a Mars orbiting communications relay satellite system and a Mars-centered navigation capability for servicing all Mars missions. With the TNIM architecture as a basis, key elements of the microwave link design are proposed. The needed new technologies which enable these designs are identified, and current maturity is assessed.

Hall, Justin R.↗

NASA NTRS1991

Enhanced ATAMM for increased throughput performance of multicomputer data flow architectures

The Algorithm To Architecture Mapping Model (ATAMM) is a Petri-net-based model which provides a strategy for periodic execution of a class of real-time algorithms on multicomputer dataflow architectures. The problem domain of particular interest is the execution of large-grained, decision-free algorithms on homogeneous processing elements. Design techniques are discussed and performance measurements are defined. A multiple-graph execution strategy is shown to increase throughput performance. It is shown that the same increase in performance is attainable with minor modifications to the existing ATAMM.

Jones, R. L.↗

NASA NTRS1991

A fault-tolerant network architecture for integrated avionics

The Army Fault-Tolerant Architecture (AFTA) under construction at the Charles Stark Draper Laboratory is an example of a highly integrated critical avionics system. The AFTA system must connect to other redundant and nonredundant systems, as well as to input/output devices. A fault-tolerant data bus (FTDB) is being developed to provide highly reliable communication between the AFTA computer and other network stations. The FTDB is being designed for Byzantine resilience and is probably capable of tolerating any single arbitrary fault. The author describes a prototype architecture for the fault-tolerant data bus.

Butler, Bryan↗

NASA NTRS1992

Modeling of Euclidean braided fiber architectures to optimize composite properties

Three-dimensional braided fiber reinforcements are a very effective toughening mechanism for composite materials. The integral yarn path inherent to this fiber architecture allows for effective multidirectional dispersion of strain energy and negates delamination problems. In this paper a geometric model of Euclidean braid fiber architectures is presented. This information is used to determine the degree of geometric isotropy in the braids. This information, when combined with candidate material properties, can be used to quickly generate an estimate of the available load-carrying capacity of Euclidean braids at any arbitrary angle.

Armstrong-Carroll, E.↗

NASA NTRS1991

Architectures for intelligent machines

The theory of intelligent machines has been recently reformulated to incorporate new architectures that are using neural and Petri nets. The analytic functions of an intelligent machine are implemented by intelligent controls, using entropy as a measure. The resulting hierarchical control structure is based on the principle of increasing precision with decreasing intelligence. Each of the three levels of the intelligent control is using different architectures, in order to satisfy the requirements of the principle: the organization level is moduled after a Boltzmann machine for abstract reasoning, task planning and decision making; the coordination level is composed of a number of Petri net transducers supervised, for command exchange, by a dispatcher, which also serves as an interface to the organization level; the execution level, include the sensory, planning for navigation and control hardware which interacts one-to-one with the appropriate coordinators, while a VME bus provides a channel for database exchange among the several devices. This system is currently implemented on a robotic transporter, designed for space construction at the CIRSSE laboratories at the Rensselaer Polytechnic Institute. The progress of its development is reported.

Saridis, George N.↗

NASA NTRS1990

Reliable and Efficient Parallel Processing Algorithms and Architectures for Modern Signal Processing

Least-squares (LS) estimations and spectral decomposition algorithms constitute the heart of modern signal processing and communication problems. Implementations of recursive LS and spectral decomposition algorithms onto parallel processing architectures such as systolic arrays with efficient fault-tolerant schemes are the major concerns of this dissertation. There are four major results in this dissertation. First, we propose the systolic block Householder transformation with application to the recursive least-squares minimization. It is successfully implemented on a systolic array with a two-level pipelined implementation at the vector level as well as at the word level. Second, a real-time algorithm-based concurrent error detection scheme based on the residual method is proposed for the QRD RLS systolic array. The fault diagnosis, order degraded reconfiguration, and performance analysis are also considered. Third, the dynamic range, stability, error detection capability under finite-precision implementation, order degraded performance, and residual estimation under faulty situations for the QRD RLS systolic array are studied in details. Finally, we propose the use of multi-phase systolic algorithms for spectral decomposition based on the QR algorithm. Two systolic architectures, one based on triangular array and another based on rectangular array, are presented for the multiphase operations with fault-tolerant considerations. Eigenvectors and singular vectors can be easily obtained by using the multi-pase operations. Performance issues are also considered.

Liu, Kuojuey Ray↗

NASA NTRS1992

Lunar architecture and urbanism

Human civilization and architecture have defined each other for over 5000 years on Earth. Even in the novel environment of space, persistent issues of human urbanism will eclipse, within a historically short time, the technical challenges of space settlement that dominate our current view. By adding modern topics in space engineering, planetology, life support, human factors, material invention, and conservation to their already renaissance array of expertise, urban designers can responsibly apply ancient, proven standards to the exciting new opportunities afforded by space. Inescapable facts about the Moon set real boundaries within which tenable lunar urbanism and its component architecture must eventually develop.

Sherwood, Brent↗

NASA NTRS1992

Lunar subsurface architecture enhanced by artificial biosphere concepts

The integration of artificial biosphere technology with subselene architecture can create a life-enhancing, productive habitat that is safe from solar radiation and extreme temperature fluctuations while maximizing resources brought from Earth and derived from lunar regolith. In the short term, the resulting biotectural (biosphere and architectural) designs will not only make the structures more habitable, productive, and manageable, but will ultimately provide the self-sufficiency factors necessary for the mature lunar settlement. From a long-term perspective, this biotecture approach to astronautics and extraterrestrial development (1) helps reduce mass lift requirements, (2) contributes to habitat self-sufficiency, and (3) actualizes at least one philosophy of solar system exploration, which is to exploit nonterrestrial resources in an effort to conserve our natural resources on this planet.

Klassi, Jason D.↗

NASA NTRS1993

On-board B-ISDN fast packet switching architectures. Phase 1: Study

Broadband ISDN (B-ISDN) extends the service integration concept to include future high speed, high volume network services as well as to accommodate narrowband ISDN in its infrastructure. The impact of B-ISDN services on satellite communications can be significant, requiring the same or similar quality of communications services provided by the terrestrial B-ISDN network. Potential satellite applications, alternate satellite network architectures, system design issues, and onboard switching/processing options for satellite B-ISDN services are investigated. Special attention is focused on fast packet switching architectures and switch design details to exploit the feasibility of implementing a fast packet switch in the future advanced communications satellite.

Faris, Faris↗

NASA NTRS1991

A safety-based decision making architecture for autonomous systems

Engineering systems designed specifically for space applications often exhibit a high level of autonomy in the control and decision-making architecture. As the level of autonomy increases, more emphasis must be placed on assimilating the safety functions normally executed at the hardware level or by human supervisors into the control architecture of the system. The development of a decision-making structure which utilizes information on system safety is detailed. A quantitative measure of system safety, called the safety self-information, is defined. This measure is analogous to the reliability self-information defined by McInroy and Saridis, but includes weighting of task constraints to provide a measure of both reliability and cost. An example is presented in which the safety self-information is used as a decision criterion in a mobile robot controller. The safety self-information is shown to be consistent with the entropy-based Theory of Intelligent Machines defined by Saridis.

Musto, Joseph C.↗

NASA NTRS1991

An integrated autonomous rendezvous and docking system architecture using Centaur modern avionics

The avionics system for the Centaur upper stage is in the process of being modernized with the current state-of-the-art in strapdown inertial guidance equipment. This equipment includes an integrated flight control processor with a ring laser gyro based inertial guidance system. This inertial navigation unit (INU) uses two MIL-STD-1750A processors and communicates over the MIL-STD-1553B data bus. Commands are translated into load activation through a Remote Control Unit (RCU) which incorporates the use of solid state relays. Also, a programmable data acquisition system replaces separate multiplexer and signal conditioning units. This modern avionics suite is currently being enhanced through independent research and development programs to provide autonomous rendezvous and docking capability using advanced cruise missile image processing technology and integrated GPS navigational aids. A system concept was developed to combine these technologies in order to achieve a fully autonomous rendezvous, docking, and autoland capability. The current system architecture and the evolution of this architecture using advanced modular avionics concepts being pursued for the National Launch System are discussed.

Nelson, Kurt↗

NASA NTRS1992

Stochastic architecture for Hopfield neural nets

An expandable stochastic digital architecture for recurrent (Hopfield like) neural networks is proposed. The main features and basic principles of stochastic processing are presented. The stochastic digital architecture is based on a chip with n full interconnected neurons with a pipeline, bit processing structure. For large applications, a flexible way to interconnect many such chips is provided.

Pavel, Sandy↗