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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
NASA NTRS1991

High-Gain AlxGa1-xAs/GaAs Transistors For Neural Networks

High-gain AlxGa1-xAs/GaAs npn double heterojunction bipolar transistors developed for use as phototransistors in optoelectronic integrated circuits, especially in artificial neural networks. Transistors perform both photodetection and saturating-amplification functions of neurons. Good candidates for such application because structurally compatible with laser diodes and light-emitting diodes, detect light, and provide high current gain needed to compensate for losses in holographic optical elements.

Kim, Jae-Hoon↗
NASA NTRS1991

Alternative AlxGa1-xAs/GaAs Transistors For Neural Networks

Further development efforts yield alternative version of transistors described in "High-Gain AlxGa1-xAs/GaAs Transistors For Neural Networks" (NPO-18101). Efforts focused on determining effects of various aspects of design and of fabrication processes upon leakage currents and on current gain.

Kim, Jae-Hoon↗
NASA NTRS1991

Optimization of transistor design including large signal device/circuit interactions at extremely high frequencies (20-100+GHz)

Transistor design for extremely high frequency applications requires consideration of the interaction between the device and the circuit to which it is connected. Traditional analytical transistor models are to approximate at some of these frequencies and may not account for variations of dopants and semiconductor materials (especially some of the newer materials) within the device. Physically based models of device performance are required. These are based on coupled systems of partial differential equations and typically require 20 minutes of Cray computer time for a single AC operating point. A technique is presented to extract parameters from a few partial differential equation solutions for the device to create a nonlinear equivalent circuit model which runs in approximately 1 second of personal computer time. This nonlinear equivalent circuit model accurately replicates the contact current properties of the device as computed by the partial differential solver on which it is based. Using the nonlinear equivalent circuit model of the device, optimization of systems design can be performed based on device/circuit interactions.

Levy, Ralph↗
NASA NTRS1990

Pass transistor implementations of multivalued logic

A simple straight-forward Karnaugh map logic design procedure for realization of multiple-valued logic circuits is presented in this paper. Pass transistor logic gates are used to realize multiple-valued networks. This work is an extension of pass transistor implementations for binary-valued logic.

Maki, G.↗
NASA NTRS1991

VHDL simulation with access to transistor models

Hardware description languages such as VHDL have evolved to aid in the design of systems with large numbers of elements and a wide range of electronic and logical abstractions. For high performance circuits, behavioral models may not be able to efficiently include enough detail to give designers confidence in a simulation's accuracy. One option is to provide a link between the VHDL environment and a transistor level simulation environment. The coupling of the Vantage Analysis Systems VHDL simulator and the NOVA simulator provides the combination of VHDL modeling and transistor modeling.

Gibson, J.↗
NASA NTRS1993

Delay analysis of combinations of pass transistors and classical logic gates

Combinations of pass transistors and logic gates driving nonlinear capacitive loads are analyzed for the presence of characteristics that will permit easier and more accurate digital logic simulation. Accurate time delay models are developed by studying the nature of the response of simplified circuit models to variations of input waveform rise and fall times and output loading. The nonlinear effects of the CMOS logic devices are minimized to permit easier interpretation of the influence of nonlinear capacitive loads. The performance of a CMOS inverter with a complex nonlinear load consisting of a pass transistor that separates a range of capacitances is compared to the same inverter circuit with a linear capacitive load to develop an understanding of the unique requirements of modeling a nonlinear system. Several methods of modeling the delay of CMOS circuits are reviewed, and a multi-parameter linear model is described. General guidelines for designing CMOS circuits with complex load circuits are developed, emphasizing that the circuit output rise delays and fall delays must be separately analyzed.

Gibson, Jonathan S.↗
NASA NTRS1992

Heterojunction bipolar transistor technology for data acquisition and communication

Heterojunction Bipolar Transistor (HBT) technology has emerged as one of the most promising technologies for ultrahigh-speed integrated circuits. HBT circuits for digital and analog applications, data conversion, and power amplification have been realized, with speed performance well above 20 GHz. At Rockwell, a baseline AlGaAs/GaAs HBT technology has been established in a manufacturing facility. This paper describes the HBT technology, transistor characteristics, and HBT circuits for data acquisition and communication.

Wang, C.↗
NASA NTRS1995

Superconducting Field-Effect Transistors

Devices offer switching speeds greater than semiconducting counterparts. High-Tc superconducting field-effect transistors (SUPEFETs) investigated for use as electronic switches in delay-line-type microwave phase shifters. Resemble semiconductor field-effect transistors in some respects, but their operation based on different principle; namely, electric-field control of transition between superconductivity and normal conductivity.

Bhasin, Kul↗
NASA NTRS1995

Long-Wavelength-Infrared Hot-Electron Transistor

Dark current reduced by energy-discriminating quantum filter. Very long-wavelength-infrared hot-electron transistor developed. Device detects photons at wavelengths around 16 micrometers. Comprises photodector integrated with energy-discriminating quantum filter in multiple-quantum-well structure. Made of variously doped and undoped layers of GaAs (quantum wells) and Al(x)Ga(1-x)As (barriers between wells). In transistor, bound-to-continuum GaAs/Al(x)Ga(1-x)As multiple-quantum-well infrared photodectors (QWIP) serves as photosensitive emitter. Wide quantum well serves as base, and there is thick barrier between base and collector. Combination of barrier and base quantum well acts as energy-discriminating filter: electrons with higher energies pass through filter to collector, those with lower energies blocked and diverted from output-current path through base contact.

Gunapala, Sarath D.↗
NASA NTRS1999

Analyses of Transistor Punchthrough Failures

The failure of two transistors in the Altitude Switch Assembly for the Solid Rocket Booster followed by two additional failures a year later presented a challenge to failure analysts. These devices had successfully worked for many years on numerous missions. There was no history of failures with this type of device. Extensive checks of the test procedures gave no indication for a source of the cause. The devices were manufactured more than twenty years ago and failure information on this lot date code was not readily available. External visual exam, radiography, PEID, and leak testing were performed with nominal results Electrical testing indicated nearly identical base-emitter and base-collector characteristics (both forward and reverse) with a low resistance short emitter to collector. These characteristics are indicative of a classic failure mechanism called punchthrough. In failure analysis punchthrough refers to an condition where a relatively low voltage pulse causes the device to conduct very hard producing localized areas of thermal runaway or "hot spots". At one or more of these hot spots, the excessive currents melt the silicon. Heavily doped emitter material diffuses through the base region to the collector forming a diffusion pipe shorting the emitter to base to collector. Upon cooling, an alloy junction forms between the pipe and the base region. Generally, the hot spot (punch-through site) is under the bond and no surface artifact is visible. The devices were delidded and the internal structures were examined microscopically. The gold emitter lead was melted on one device, but others had anomalies in the metallization around the in-tact emitter bonds. The SEM examination confirmed some anomalies to be cosmetic defects while other anomalies were artifacts of the punchthrough site. Subsequent to these analyses, the contractor determined that some irregular testing procedures occurred at the time of the failures heretofore unreported. These testing irregularities involved the use of a breakout box and were the likely cause of the failures. There was no evidence to suggest a generic failure mechanism was responsible for the failure of these transistors.

Nicolas, David P.↗
NASA NTRS2001

Electronic Model of a Ferroelectric Field Effect Transistor

A pair of electronic models has been developed of a Ferroelectric Field Effect transistor. These models can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The models use the Schmitt trigger circuit as a basis for their design. One model uses bipolar junction transistors and one uses MOSFET's. Each model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current from each model has similar values to an actual FFET that was measured experimentally. T'he input and o Output resistance in the models are also similar to that of the FFET. The models are valid for all frequencies below RF levels. No attempt was made to model the high frequency characteristics of the FFET. Each model can be used to design circuits using FFET's with standard electrical simulation packages. These circuits can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The models consist of only standard electrical components, such as BJT's, MOSFET's, diodes, resistors, and capacitors. Each model is compared to the experimental data measured from an actual FFET.

MacLeod, Todd C.↗
NASA NTRS2001

Analysis of long-channel nanotube field-effect-transistors (NT FETs)

This viewgraph presentation provides an analysis of long-channel nanotube (NT) field effect transistors (FET) from NASA's Ames Research Center. The structure of such a transistor including the electrode contact, 1D junction, and the planar junction is outlined. Also mentioned are various characteristics of a nanotube tip-equipped scanning tunnel microscope (STM).

Toshishige, Yamada↗
NASA NTRS2001

Wavelength Division Multiplexing Scheme for Radio-Frequency Single Electron Transistors

We describe work on a wavelength division multiplexing scheme for radio-frequency single electron transistors. We use a network of resonant impedance matching circuits to direct applied rf carrier waves to different transistors depending on carrier frequency. Using discrete components, we made a two-channel demonstration of this concept and successfully reconstructed input signals with small levels of cross coupling. A lithographic version of the rf circuits had measured parameters in agreement with electromagnetic modeling, with reduced cross capacitance and inductance, and should allow 20 to 50 channels to be multiplexed.

Stevenson, Thomas R.↗
NASA NTRS2001

Multiplexing of Radio-Frequency Single Electron Transistors

We present results on wavelength division multiplexing of radio-frequency single electron transistors. We use a network of resonant impedance matching circuits to direct applied rf carrier waves to different transistors depending on carrier frequency. A two-channel demonstration of this concept using discrete components successfully reconstructed input signals with small levels of cross coupling. A lithographic version of the rf circuits had measured parameters in agreement with electromagnetic modeling, with reduced cross capacitance and inductance, and should allow 20 to 50 channels to be multiplexed.

Stevenson, Thomas R.↗
NASA NTRS2002

Progress Towards High-Sensitivity Arrays of Detectors of Sub-mm Radiation using Superconducting Tunnel Junctions with Radio-Frequency Single-Electron Transistors

The science drivers for the SPIRIT/SPECS missions demand sensitive, fast, compact, low-power, large-format detector arrays for high resolution imaging and spectroscopy in the far infrared and submillimeter. Detector arrays with 10,000 pixels and sensitivity less than 10(exp 20)-20 W/Hz(exp 20)0.5 are needed. Antenna-coupled superconducting tunnel junction detectors with integrated rf single-electron transistor readout amplifiers have the potential for achieving this high level of sensitivity, and can take advantage of an rf multiplexing technique when forming arrays. The device consists of an antenna structure to couple radiation into a small superconducting volume and cause quasiparticle excitations, and a single-electron transistor to measure currents through tunnel junction contacts to the absorber volume. We will describe optimization of device parameters, and recent results on fabrication techniques for producing devices with high yield for detector arrays. We will also present modeling of expected saturation power levels, antenna coupling, and rf multiplexing schemes.

Stevenson, T. R.↗
NASA NTRS2002

Fabrication of Tunnel Junctions For Direct Detector Arrays With Single-Electron Transistor Readout Using Electron-Beam Lithography

This paper will describe the fabrication of small aluminum tunnel junctions for applications in astronomy. Antenna-coupled superconducting tunnel junctions with integrated single-electron transistor readout have the potential for photon-counting sensitivity at sub-millimeter wavelengths. The junctions for the detector and single-electron transistor can be made with electron-beam lithography and a standard self-aligned double-angle deposition process. However, high yield and uniformity of the junctions is required for large-format detector arrays. This paper will describe how measurement and modification of the sensitivity ratio in the resist bilayer was used to greatly improve the reliability of forming devices with uniform, sub-micron size, low-leakage junctions.

Stevenson, T. R.↗
NASA NTRS1961

Irradiation Effects of 22 and 240 MeV Protons on Several Transistors and Solar Cells

The work covered in this report has been directed toward the investigation of the irradiation effects of 22 and 240 MeV protons on several transistors, solar cells, resistors, and condensers to be used in the space radiation environment. The experimental data indicated definite detrimental effects on transistors and solar cells but no apparent effects on the types of resistors and condensers tested. The detrimental effects are of two distinct types: transient and permanent.

Hulten, W. C.↗
NASA NTRS2003

High Electron Mobility SiGe/Si Transistor Structures on Sapphire Substrates

SiGe/Si n-type modulation doped field effect structures and transistors (n-MODFETs) have been fabricated on r-plane sapphire substrates. The structures were deposited using molecular beam epitaxy, and antimony dopants were incorporated via a delta doping process. Secondary ion mass spectroscopy (SIMS) indicates that the peak antimony, concentration was approximately 4 x 10(exp19) per cubic cm. The electron mobility was over 1,200 and 13,000 sq cm/V-sec at room temperature and 0.25 K, respectively. At these two temperatures, the electron carrier densities were 1.6 and 1.33 x 10(exp 12) per sq cm, thus demonstrating that carrier confinement was excellent. Shubnikov-de Haas oscillations were observed at 0.25 K, thus confirming the two-dimensional nature of the carriers. Transistors, with gate lengths varying from 1 micron to 5 microns, were fabricated using these structures and dc characterization was performed at room temperature. The saturated drain current region extended over a wide source-to-drain voltage (V(sub DS)) range, with (V(sub DS)) knee voltages of approximately 0.5 V and increased leakage starting at voltages slightly higher than 4 V.

Alterovitz, Samuel A.↗