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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
NASA NTRS1992

User needs as a basis for advanced technology

The NASA Integrated Technology Plan (ITP) is described with treatment given to the identification of U.S. technology needs, space research and technology programs, and some ITP implementations. The ITP is based on the development and transfer of technologies relevant to the space program that also have significant implications for general technological research. Among the areas of technological research identified are: astrophysics, earth sciences, microgravity, and space physics. The Office of Space Science and Applications prioritizes the technology needs in three classes; the highest priority is given to submm and microwave technologies for earth sciences and astrophysics study. Other government and commercial needs are outlined that include cryogenic technologies, low-cost engines, advanced data/signal processing, and low-cost ELVs. It is demonstrated that by identifying and addressing these areas of user technology needs NASA's research and technology program can enhance U.S. trade and industrial competitiveness.

Mankins, John C.↗
NASA NTRS1986

Advances in gallium arsenide monolithic microwave integrated-circuit technology for space communications systems

Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMIC's to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMIC's is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. In this paper, current developments in GaAs MMIC technology are described, and the status and prospects of the technology are assessed.

Bhasin, K. B.↗
NASA NTRS2007

Making Technology Ready: Integrated Systems Health Management

This paper identifies work needed by developers to make integrated system health management (ISHM) technology ready and by programs to make mission infrastructure ready for this technology. This paper examines perceptions of ISHM technologies and experience in legacy programs. Study methods included literature review and interviews with representatives of stakeholder groups. Recommendations address 1) development of ISHM technology, 2) development of ISHM engineering processes and methods, and 3) program organization and infrastructure for ISHM technology evolution, infusion and migration.

Malin, Jane T.↗
DOE OSTI2022

Evaluation of Heat Exchanger Technology for Integrated Energy System: Methodology and Preliminary Application

This report proposes a novel heat exchanger evaluation method, based on integrated QFD-AHP technique, to support strategic optimal selection of heat exchanger (HX) technology for integrated energy systems. The term “optimal selection” is defined as selecting a product (i.e., HX) that best meets various aspects of end user demand, including both technical and economic requirements. Compared to previous HX evaluation methods, the proposed approach allows decision makers to explicitly take into account the practical demand of customers (i.e., HX end users) which may vary depending on the HX application target. In addition, the proposed evaluation method can be used not only for high-level decisions to select HX type, but also for low-level decisions such as the selection of the key components including HX material or heat transfer fluid. The focus of this study is to describe the new HX evaluation method and to illustrate the overall HX evaluation and selection processes using the three nuclear heat application cases that represent the thermal integration between advanced nuclear reactors and industrial processes. As a preliminary study, three different types of HX, i.e., shell-and-tube heat exchanger, printed circuit heat exchanger, and heat pipe heat exchanger, were compared.

42 ENGINEERING↗
NASA NTRS2016

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 C

We have reported SiC integrated circuits (IC's) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 C [1, 2]. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 C [3]. However, this thermal ramp was not ended until a peak temperature of 880 C (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology. Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 C. In one test, the temperature was ramped and then held at 727 C, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 C before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 C (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 C.

JFET↗
NASA NTRS1982

Integrated optics technology study

The materials and processes available for the fabrication of single mode integrated electrooptical components are described. Issues included in the study are: (1) host material and orientation, (2) waveguide formation, (3) optical loss mechanisms, (4) wavelength selection, (5) polarization effects and control, (6) laser to integrated optics coupling,(7) fiber optic waveguides to integrated optics coupling, (8) souces, (9) detectors. The best materials, technology and processes for fabrication of integrated optical components for communications and fiber gyro applications are recommended.

Chen, B.↗
NASA NTRS2001

Novel Low Loss Wide-Band Multi-Port Integrated Circuit Technology for RF/Microwave Applications

In this paper, novel low loss, wide-band coplanar stripline technology for radio frequency (RF)/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth, and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semi-conductor devices and microelectromechanical systems (MEMS).

Simons, Rainee N.↗
NASA NTRS2016

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 Degrees Centigrade

We have reported SiC integrated circuits (ICs) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 degrees Centigrade. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 degrees Centigrade. However, this thermal ramp was not ended until a peak temperature of 880 degrees Centigrade (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology.Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 degrees Centigrade. In one test, the temperature was ramped and then held at 727 degrees Centigrade, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 degrees Centigrade before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 degrees Centigrade (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 degrees Centigrade.

Silicon Carbide↗
NASA NTRS1982

Integrated optics technology study

The status and near term potential of materials and processes available for the fabrication of single mode integrated electro-optical components are discussed. Issues discussed are host material and orientation, waveguide formation, optical loss mechanisms, wavelength selection, polarization effects and control, laser to integrated optics coupling fiber optic waveguides to integrated optics coupling, sources, and detectors. Recommendations of the best materials, technology, and processes for fabrication of integrated optical components for communications and fiber gyro applications are given.

Chen, B.↗
NASA NTRS2009

The Habitat Demonstration Unit Project

This paper will describe an overview of the NASA-led multi-center Habitat Demonstration Unit (HDU) Project. The HDU project is a technology-pull project that integrates technologies and innovations from numerous NASA centers. This project will be used to investigate and validate surface architectures, operations concepts, and requirements definition. The HDU project will be part of the 2010 Desert Research and Technologies Simulations (DRATS). The purpose of this project is to develop, integrate, test, and evaluate a HDU in the context of the mission architectures and surface operation concepts. This HDU is based on the Constellation Architecture Scenario 12.1 concept of a vertically oriented habitat module. A multi-center approach with be utilized to build, integrate, and test the HDU project through a shared collaborative effort of multiple NASA centers. This project is part of the strategic plan from the ESMD Directorate Integration Office (DIO) and the Lunar Surface Systems Project Office (LSSPO) to test surface elements in a surface analog environment which includes two Lunar Electric Rovers and the HDU during the 2010 analog field test. This paper will describe the overall objectives, its various configurations, strategic plan, and technology integration as it pertains to the 2010 and 2011 field analog tests.

Kennedy, Kriss J.↗
NASA NTRS2024

Alignment of NASA’s Human System Risks with Technological Capability Gaps to Enable Integrated Research and Technology Development Strategic Planning

BACKGROUND: Radiation, reduced gravity, distance from earth, isolation and confinement, and habitation within artificially created and controlled life support environments are hazards that present risk to human space explorers. NASA’s Human System Risk Board (HSRB) maintains a set of twenty-nine different Human System Risks with subject matter experts from across the agency providing regular updates to the estimated likelihood and consequence associated with each risk. The Human Research Program (HRP) has historically used these risk classifications as a primary basis for identifying and prioritizing human research investments aimed at characterizing and/or mitigating the respective human system risks. In many cases, technology development is required to mature and validate risk mitigation strategies, however, NASA’s primary technology development programs have not typically used Human System Risks as a basis for strategic planning. A primary function of the Environmental Control and Life Support Systems (ECLSS) – Crew Health and Performance (CHP) System Capability Leadership Team (SCLT) is to continually identify, review, and update technological capability gaps and to establish and oversee multiyear strategic roadmaps aimed at guiding NASA’s technology development priorities in these areas. These roadmaps are intended to be agency-wide and independent of any program, directorate, or other organization within NASA. DESCRIPTION: The SCLT and HRP collaborated to establish a set of Human System Capability Gaps, which establish a formal linkage between the capability gaps used to prioritize investments across much of NASA, and the Human System Risks that are primarily used to inform and prioritize human research. This set of twenty-eight gaps was developed by subject matter experts, and each gap mapped to the primary associated Human System Risks. The gaps and risk mapping were then reviewed and approved via the HSRB, thereby formally aligning the research-focused Human System Risks with the technology-focused capability gaps. DISCUSSION: This effort has enabled development of integrated roadmaps and budget coordination with research and technology development activities that are formally linked to agency-recognized capability gaps and Human System Risks. Close and ongoing coordination between the SCLT, HRP, Mars Campaign Office, and the Health & Medical Technical Authority (HMTA) is essential to ensure alignment and prioritization of CHP-related research and technology development to enable NASA’s future exploration missions.

Andrew F J Abercromby↗
NASA NTRSDate not supplied

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRSDate not supplied

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRS2023

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRS2010

The Habitat Demonstration Unit Project Overview

This paper will describe an overview of the National Aeronautics and Space Administration (NASA) led multi-center Habitat Demonstration Unit (HDU) Project. The HDU project is a "technology-pull" project that integrates technologies and innovations from numerous NASA centers. This project will be used to investigate and validate surface architectures, operations concepts, and requirements definition of various habitation concepts. The first habitation configuration this project will build and test is the Pressurized Excursion Module (PEM). This habitat configuration - the PEM - is based on the Constellation Architecture Scenario 12.1 concept of a vertically oriented habitat module. The HDU project will be tested as part of the 2010 Desert Research and Technologies Simulations (D-RATS) test objectives. The purpose of this project is to develop, integrate, test, and evaluate a habitat configuration in the context of the mission architectures and surface operation concepts. A multi-center approach will be leveraged to build, integrate, and test the PEM through a shared collaborative effort of multiple NASA centers. The HDU project is part of the strategic plan from the Exploration Systems Mission Directorate (ESMD) Directorate Integration Office (DIO) and the Lunar Surface Systems Project Office (LSSPO) to test surface elements in a surface analog environment. The 2010 analog field test will include two Lunar Electric Rovers (LER) and the PEM among other surface demonstration elements. This paper will describe the overall objectives, its various habitat configurations, strategic plan, and technology integration as it pertains to the 2010 and 2011 field analog tests. To accomplish the development of the PEM from conception in June 2009 to rollout for operations in July 2010, the HDU project team is using a set of design standards to define the interfaces between the various systems of PEM and to the payloads, such as the Geology Lab, that those systems will support. Scheduled activities such as early fit-checks and the utilization of a habitat avionics test bed prior to equipment installation into PEM are planned to facilitate the integration process.

Kennedy, Kriss J.↗
NASA NTRS2004

Ultra-Efficient Engine Technology Project Integrated Into NASA's Vehicle Systems Program

The Ultra-Efficient Engine Technology (UEET) Project is formulated according to the Office of Aerospace Technology's objectives as outlined in the NASA Strategic Plan. It is directly related to the "protect the environment" objective and will make progress toward the "increase mobility" and "support national security" objectives as well. UEET technologies will impact future civil and military aircraft and will benefit the development of future space transportation propulsion systems. UEET Project success will, therefore, depend on developing revolutionary, but affordable, technology solutions that are inherently safe and reliable and thus can be incorporated in future propulsion system designs. In fiscal year 2003, UEET became part of NASA's Vehicle Systems Program and continues to evolve its programmatic role. The Vehicle Systems Program aims to develop breakthrough technologies and methodologies, push the boundaries of flight through research on advanced vehicle concepts, respond quickly to industry and the Department of Defense on critical safety and other issues, and provide facilities and expert consultation for industry and other Government agencies during product development.

Shaw, Robert J.↗
NASA NTRS2011

HDU Deep Space Habitat (DSH) Overview

This paper gives an overview of the National Aeronautics and Space Administration (NASA) led multi-center Habitat Demonstration Unit (HDU) project Deep Space Habitat (DSH) analog that will be field-tested during the 2011 Desert Research and Technologies Studies (D-RATS) field tests. The HDU project is a technology pull project that integrates technologies and innovations from multiple NASA centers. This project will repurpose the HDU Pressurized Excursion Module (PEM) that was field tested in the 2010 D-RATS, adding habitation functionality to the prototype unit. The 2010 configuration of the HDU-PEM consisted of a lunar surface laboratory module that was used to bring over 20 habitation-related technologies together in a single platform that could be tested as an advanced habitation analog in the context of mission architectures and surface operations. The 2011 HDU-DSH configuration will build upon the PEM work, and emphasize validity of crew operations (habitation and living, etc), EVA operations, mission operations, logistics operations, and science operations that might be required in a deep space context for Near Earth Object (NEO) exploration mission architectures. The HDU project consists of a multi-center team brought together in a skunkworks approach to quickly build and validate hardware in analog environments. The HDU project is part of the strategic plan from the Exploration Systems Mission Directorate (ESMD) Directorate Integration Office (DIO) and the Exploration Mission Systems Office (EMSO) to test destination elements in analog environments. The 2011 analog field test will include Multi Mission Space Exploration Vehicles (MMSEV) and the DSH among other demonstration elements to be brought together in a mission architecture context. This paper will describe overall objectives, various habitat configurations, strategic plan, and technology integration as it pertains to the 2011 field tests.

Kennedy, Kriss J.↗