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At least 145 records · Page 8

A microprocessor based high speed packet switch for satellite communications, executive summary

The feasibility of using microprocessors to control satellite-borne packet switching was investigated by designing a packet switch architecture suitable for microprocessor control, using 2900 series components to design the processor(s), and evaluating the packet switch in terms of system throughput, delay, and queue sizes without the packet switch. System architecture for one, three, and multiple processors was designed and evaluated. The production cost of the single processor packet switch is estimated at $500,000, excluding cost of development. The three processor version which can support a maximum throughput of 500,000 packets/sec is estimated to have a production cost of under $100,000. For the multiple processor system, cost is believed to be proportional to throughput, with $1,000,000 for 500,000 packets/sec being the proportionality factor.

Arozullah, M.

A microprocessor based high speed space-borne packet switch

The design and performance evaluation of a single microprocessor based packet switch for use on-board a satellite are presented. The primary design criterion is to maximize the system throughput. A number of protocols and their impact on the switch design are discussed. Stem and processor hardware architectures are described. The flow charts of the software required to accomplish the essential functions are presented and modification needed for use in a multisatellite network are also indicated. Maximum throughput attainable is calculated, desirable characteristics of microprocessors for this application are pointed out. A queue theoretic model of the packet switch has been developed. Analytical relationships of the average waiting times and the queue sizes at the queues and the overall average response time with the various design parameters of the switch have been obtained. A number of graphs showing the effect of variation in the number of input and output lines, data rates, destination functions, speed of output lines and some other design parameters on the performance of the switch are presented and discussed.

Arozullah, M.

Evaluation of a three-processor architecture for a satellite packet switch

The architecture of a microprocessor-based packet switch using three processors for use on-board satellites is presented. The operation of the switch involves three distinct functions, namely, the input, the routing and the output functions. Each of these functions is performed by one of the three microprocessors. The operation of the switch along with those of the corresponding software routines are explained. An expression for the throughput is presented. A queue theoretic model of the switch is developed. Analytical expressions for the overall average response time at the various queues are obtained. A number of graphs showing the average response time as a function of some parameters of the switch are also presented.

Arozullakh, M.

Microwave switching power divider

A pair of parallel, spaced-apart circular ground planes define a microwave cavity with multi-port microwave power distributing switching circuitry formed on opposite sides of a thin circular dielectric substrate disposed between the ground planes. The power distributing circuitry includes a conductive disk located at the center of the substrate and connected to a source of microwave energy. A high speed, low insertion loss switching diode and a dc blocking capacitor are connected in series between the outer end of a transmission line and an output port. A high impedance, microwave blocking dc bias choke is connected between each switching diode and a source of switching current. The switching source forward biases the diodes to couple microwave energy from the conductive disk to selected output ports and, to associated antenna elements connected to the output ports to form a synthesized antenna pattern.

Stockton, R. J.

Automatic thermal control switches

Two automatic, flexible connection thermal control switches have been designed and tested in a thermal vacuum facility and in the Get Away Special (GAS) container flown on the third Shuttle flight. The switches are complementary in that one switch passes heat when the plate on which it is mounted exceeds some selected temperature and the other switch will pass heat only when the mounting plate temperature is below the selected value. Both switches are driven and controlled by phase-change capsule motors and require no other power source or thermal sensors.

Wing, L. D.

Magneto-optic garnet and liquid crystal optical switches

Magnetic stripe domain and liquid crystal devices are being developed and evaluated as fiber optic switches that can be utilized for nonblocking type nxm optical matrix switches in networking and optical processing. Liquid crystal switches are characterized by very low insertion loss and crosstalk, while stripe domain switches commutate in less than one microsecond. Both switches operate on multimode, randomly polarized fiber light with potentially large values for (n,m). The applications of these magnetic stripe domain and liquid crystal devices are discussed.

Krawczak, J. A.

Design considerations for high-power VHF radar transceivers: T/R switch design

The transceiver (TR) switch developed at NOAA's Aeronomy Laboratory for use in their 50 kW peak power, 50 MHz transmitter is described. The switch mounts inside the transmitter chassis and was designed to be compact while retaining the ability to handle well over 50 kW peak power at average power levels up to 2 kW. The TR switch is a conventional TR/ATR design with equivalent /4 transmission line sections constructed of lumped constant coils and transmitting capacitors in ''Tee' sections. Two TR sections are placed in series to achieve adequate receiver protection. The switch is set into the ''transmit' mode by forward biasing the 3 pin diodes to about 1.2 amperes each. The receive mode is achieved by back biasing the diodes to -15 volts. A directional coupler is also incorporated into the TR switch box to provide a convenient monitor point for forward and reflected transmitter power.

Ecklund, W. L.

The NASA satellite communication 20 x 20 matrix switches

The characteristics of two matrix switches designed for high capacity satellite communications systems are described. The switches provide routing between 20 input and 20 output ports at an IF frequency during TDMA operations. Switching speeds of 10 nsec are projected for dual gate GaAs FETs. The two designs differed in the coupling configurations, bandwidth (2.69-1.2 GHz), off-state isolation (-54 to -40 dB), switching speeds (16-37 nsec), and gain ripple (5.3-2.2 dB). Both designs achieved a 2 nsec reconfiguration rate. Further development is required to reduce the ripple effects and attain the potential 2 nsec switching speed offered by the GaAs FETs.

Saunders, A. L.

New mode switching algorithm for the JPL 70-meter antenna servo controller

The design of control mode switching algorithms and logic for JPL's 70 m antenna servo controller are described. The old control mode switching logic was reviewed and perturbation problems were identified. Design approaches for mode switching are presented and the final design is described. Simulations used to compare old and new mode switching algorithms and logic show that the new mode switching techniques will significantly reduce perturbation problems.

Nickerson, J. A.

The bit-error rate performance of a satellite microwave matrix switch

The matrix switch is a critical element of communications satellites using multiple-beam antennas and on-board switching. Two proof-of-concept models of a microwave matrix switch have been developed under NASA-sponsored contracts. These switches have undergone extensive testing at NASA Lewis Research Center to determine their operating characteristics in a system environment. The results of these tests indicate the effect of the matrix switch on the overall system operation.

Kerczewski, Robert J.

The bit-error rate performance of a satellite microwave matrix switch

The matrix switch is a critical element of communications satellites employing multiple beam antennas and on-board switching. Two proof-of-concept models of a microwave matrix switch have been developed under NASA-sponsored contracts. These switches have undergone extensive testing at NASA Lewis Research Center to determine their operating characteristics in a system environment. The results of these tests indicate the effect of the matrix switch on the overall system operation.

Kerczewski, Robert J.

A self-injection locked, Q-switched, line-narrowed Ti:Al2O3 laser

Line-narrowing, Q-switched, and self-injection locking are studied independently and as a system. Line narrowing is shown both theoretically and experimentally to depend on the inverse square root of the pulse evolution time interval. Q switching of the Ti:Al2O3 laser is demonstrated and the laser output energy as a function of the Q-switch delay is investigated. Self-injection is demonstrated and the operation of the laser is explored as a function of loss and the Q-switch delay. Self-injection locking is demonstrated and the performance as a function of the Q-switch delay is determined.

Barnes, Norman P.

Switch-on shocks

It is argued that parallel propagating Alfven waves steepen to second order in the wave amplitude, rather than first order, as is the case for oblique MHD waves. An analytical solution for the structure of weak switch-on shocks is derived. The Rankine-Hugoniot relations for finite amplitude switch-on shocks are obtained in a compact form. The differential equation for resistive switch-on shocks is solved, and the resistive critical Mach number is obtained. The differential equation for resistive switch-on shocks with finite ion inertia is identical to the one obtained in the pure resistive case. It is argued that efficient electron heat conduction can significantly extend the range of upstream parameters for which switch-on shocks are expected.

Kennel, C. F.

Fast packet switch architectures for broadband integrated services digital networks

Background information on networking and switching is provided, and the various architectures that have been considered for fast packet switches are described. The focus is solely on switches designed to be implemented electronically. A set of definitions and a brief description of the functionality required of fast packet switches are given. Three basic types of packet switches are identified: the shared-memory, shared-medium, and space-division types. Each of these is described, and examples are given.

Tobagi, Fouad A.

Multiphase complete exchange on a circuit switched hypercube

On a distributed memory parallel computer, the complete exchange (all-to-all personalized) communication pattern requires each of n processors to send a different block of data to each of the remaining n - 1 processors. This pattern is at the heart of many important algorithms, most notably the matrix transpose. For a circuit switched hypercube of dimension d(n = 2(sup d)), two algorithms for achieving complete exchange are known. These are (1) the Standard Exchange approach that employs d transmissions of size 2(sup d-1) blocks each and is useful for small block sizes, and (2) the Optimal Circuit Switched algorithm that employs 2(sup d) - 1 transmissions of 1 block each and is best for large block sizes. A unified multiphase algorithm is described that includes these two algorithms as special cases. The complete exchange on a hypercube of dimension d and block size m is achieved by carrying out k partial exchange on subcubes of dimension d(sub i) Sigma(sup k)(sub i=1) d(sub i) = d and effective block size m(sub i) = m2(sup d-di). When k = d and all d(sub i) = 1, this corresponds to algorithm (1) above. For the case of k = 1 and d(sub i) = d, this becomes the circuit switched algorithm (2). Changing the subcube dimensions d, varies the effective block size and permits a compromise between the data permutation and block transmission overhead of (1) and the startup overhead of (2). For a hypercube of dimension d, the number of possible combinations of subcubes is p(d), the number of partitions of the integer d. This is an exponential but very slowly growing function and it is feasible over these partitions to discover the best combination for a given message size. The approach was analyzed for, and implemented on, the Intel iPSC-860 circuit switched hypercube. Measurements show good agreement with predictions and demonstrate that the multiphase approach can substantially improve performance for block sizes in the 0 to 160 byte range. This range, which corresponds to 0 to 40 floating point numbers per processor, is commonly encountered in practical numeric applications. The multiphase technique is applicable to all circuit-switched hypercubes that use the common e-cube routing strategy.

Bokhari, Shahid H.

Monolithic mm-wave phase shifter using optically activated superconducting switches

A phase shifter is disclosed having a reference path and a delay path, light sources, and superconductive switches. Each of the superconductive switches is terminated in a virtual short circuit, which may be a radial stub. Switching between the reference path and delayed path is accomplished by illuminating the superconductive switches connected to the desired path, while not illuminating the superconductive switches connected to the other path.

Romanofsky, Robert R.

Cost-effective optical switch matrix for microwave phased-array

An all-fiber (6x6) optical shutter switch matrix with the control system for microwave phased array has been demonstrated. The device offers the advantages of integrated configuration, low cost, low power consumption, small size, and light weight. The maximum extinction ratio (among 36 individual pixel) of this switch matrix at 840 nm is 24.2 dB, and the switching time is less than 120 microsec. In addition to phased array application, this low cost switch matrix is extremely attractive for fiber optic switching networks.

Pan, J. J.

Transient current interruption mechanism in a magnetically delayed vacuum switch

The capacity of a magnetically delayed vacuum switch to conduct current depends on the density of plasma injected into the switch. Exceeding the current capacity results in the switch entering a lossy mode of operation characterized by a transient interruption of the main current (opening behavior) and a rapid increase of voltage across the vacuum gap. Streak and framing photographs of the discharge indicate that a decrease of luminosity near the middle of the gap preceeds the transition to the opening phase. The zone of low luminosity propagates toward the cathode. This evidence suggests that the mechanism causing the opening phase is erosion of the background plasma in a manner similar to that in a plasma-opening switch. The resulting ion depletion forces a space-charge-limited conduction mode. The switch inductance maintains a high discharge current even during the space-charge-limited conduction phase, thus producing high internal fields. The high accelerating voltage, in turn, produces electron and ion beams that heat the electrode surfaces. As a result of the heating, jets of electrode vapor issue from the electrodes, either cathode or anode, depending on the selection of electrode materials.

Morris, Gibson, Jr.