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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
NASA NTRS2004

Cryogenic Characterization and Testing of Magnetically-Actuated Microshutter Arrays for the James Webb Space Telescope

Two-dimensional MEMS microshutter arrays (MSA) have been fabricated at the NASA Goddard Space Flight Center (GSFC) for the James Webb Space Telescope (JWST) to enable cryogenic (approximately 35 K) spectrographic astronomy measurements in the near-infrared region. Functioning as a focal plane object selection device, the MSA is a 2-D programmable aperture mask with fine resolution, high efficiency and high contrast. The MSA are close- packed silicon nitride shutters (cell size of 100 x 200 microns) patterned with a torsion flexure to allow opening to 90 degrees. A layer of magnetic material is deposited onto each shutter to permit magnetic actuation. Two electrodes are deposited, one onto each shutter and another onto the support structure side-wall, permitting electrostatic latching and 2-D addressing. New techniques were developed to test MSA under mission-similar conditions (8 K less than or equal to T less than 300K). The magnetic rotisserie has proven to be an excellent tool for rapid characterization of MSA. Tests conducted with the magnetic rotisserie method include accelerated cryogenic lifetesting of unpackaged 128 x 64 MSA and parallel measurement of the magneto-mechanical stiffness of shutters in pathfinder test samples containing multiple MSA designs. Lifetest results indicate a logarithmic failure rate out to approximately 10(exp 6) shutter actuations. These results have increased our understanding of failure mechanisms and provide a means to predict the overall reliability of MSA devices.

King, T. T.↗
NASA NTRS2017

Environmental Effects on Data Retention in Flash Cells

Flash technology is being utilized in fuzed munition applications and, based on the development of digital logic devices in the commercial world, usage of flash technology will increase. Antifuse technology, prevalent in non-volatile field programmable gate arrays (FPGAs), will eventually be phased out as new devices have not been developed for approximately a decade. The reliance on flash technology presents a long-term reliability issue for both DoD and NASA safety- and mission-critical applications. A thorough understanding of the data retention failure modes and statistics associated with Flash data retention is of vital concern to the fuze safety community. A key retention parameter for a flash cell is the threshold voltage (VTH), which is an indirect indicator of the amount of charge stored on the cells floating gate. This paper will present the results of our on-going tests: long-term storage at 150 C for a small population of devices, neutron radiation exposure, electrostatic discharge (ESD) testing, and the trends of large populations (over 300 devices for each condition) exposed to three difference temperatures: 25 C, 125 C, and 150 C.

Flash↗
NASA NTRS1978

Test-vehicle cycle programmer

Instrument reduces manpower needed for testing electric powered vehicles. Device has dual scale that allows operator to compare actual speed with preprogrammed test speed. Features include large meter, buzzer, packaging to allow ready interchange of memories with different profiles, small size, minimal current drain, and reverse supply voltage protection.

Lesco, D. J.↗
NASA NTRS2004

A Discussion of Using a Reconfigurable Processor to Implement the Discrete Fourier Transform

This paper presents the design and implementation of the Discrete Fourier Transform (DFT) algorithm on a reconfigurable processor system. While highly applicable to many engineering problems, the DFT is an extremely computationally intensive algorithm. Consequently, the eventual goal of this work is to enhance the execution of a floating-point precision DFT algorithm by off loading the algorithm from the computing system. This computing system, within the context of this research, is a typical high performance desktop computer with an may of field programmable gate arrays (FPGAs). FPGAs are hardware devices that are configured by software to execute an algorithm. If it is desired to change the algorithm, the software is changed to reflect the modification, then download to the FPGA, which is then itself modified. This paper will discuss methodology for developing the DFT algorithm to be implemented on the FPGA. We will discuss the algorithm, the FPGA code effort, and the results to date.

White, Michael J.↗
NASA NTRS2013

Human Machine Interface Programming and Testing

Human Machine Interface (HMI) Programming and Testing is about creating graphical displays to mimic mission critical ground control systems in order to provide NASA engineers with the ability to monitor the health management of these systems in real time. The Health Management System (HMS) is an online interactive human machine interface system that monitors all Kennedy Ground Control Subsystem (KGCS) hardware in the field. The Health Management System is essential to NASA engineers because it allows remote control and monitoring of the health management systems of all the Programmable Logic Controllers (PLC) and associated field devices. KGCS will have equipment installed at the launch pad, Vehicle Assembly Building, Mobile Launcher, as well as the Multi-Purpose Processing Facility. I am designing graphical displays to monitor and control new modules that will be integrated into the HMS. The design of the display screen will closely mimic the appearance and functionality of the actual modules. There are many different field devices used to monitor health management and each device has its own unique set of health management related data, therefore each display must also have its own unique way to display this data. Once the displays are created, the RSLogix5000 application is used to write software that maps all the required data read from the hardware to the graphical display. Once this data is mapped to its corresponding display item, the graphical display and hardware device will be connected through the same network in order to test all possible scenarios and types of data the graphical display was designed to receive. Test Procedures will be written to thoroughly test out the displays and ensure that they are working correctly before being deployed to the field. Additionally, the Kennedy Ground Controls Subsystem's user manual will be updated to explain to the NASA engineers how to use the new module displays.

Foster, Thomas Garrison↗
NASA NTRS1990

Programmable Analog Memory Resistors For Electronic Neural Networks

Electrical resistance of new solid-state device altered repeatedly by suitable control signals, yet remains at steady value when control signal removed. Resistance set at low value ("on" state), high value ("off" state), or at any convenient intermediate value and left there until new value desired. Circuits of this type particularly useful in nonvolatile, associative electronic memories based on models of neural networks. Such programmable analog memory resistors ideally suited as synaptic interconnects in "self-learning" neural nets. Operation of device depends on electrochromic property of WO3, which when pure is insulator. Potential uses include nonvolatile, erasable, electronically programmable read-only memories.

Ramesham, Rajeshuni↗
NASA NTRS2007

Assurance of Complex Electronics. What Path Do We Take?

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled in software, such as communication protocols. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of "software-like" bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and "bugs" can be detected earlier in the development cycle, thus creating a development process for CE that will be easily maintained and configurable based on the device used.

FROM↗
NASA NTRS2007

Software Process Assurance for Complex Electronics

Complex Electronics (CE) now perform tasks that were previously handled in software, such as communication protocols. Many methods used to develop software bare a close resemblance to CE development. Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. With CE devices obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that used standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques were used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that was more easily maintained, consistent and configurable based on the device used.

Plastow, Richard A.↗
NASA NTRS2007

Software Process Assurance for Complex Electronics (SPACE)

Complex Electronics (CE) are now programmed to perform tasks that were previously handled in software, such as communication protocols. Many of the methods used to develop software bare a close resemblance to CE development. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that looks at using standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques can be used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that will be more easily maintained, consistent and configurable based on the device used.

Plastow, Richard A.↗
NASA NTRS1995

The Impact on Space Radiation Requirements and Effects on ASIMS

The evolution of highly miniaturized electronic and mechanical systems will be accompanied by new problems and issues regarding the radiation response of these systems in the space environment. In this paper we discuss some of the more prominent radiation problems brought about by miniaturization. For example, autonomous micro-spacecraft will require large amounts of high density memory, most likely in the form of stacked, multichip modules of DRAM's, that must tolerate the radiation environment. However, advanced DRAM's (16 to 256 Mbit) are quite susceptible to radiation, particularly single event effects, and even exhibit new radiation phenomena that were not a problem for older, less dense memory chips. Another important trend in micro-spacecraft electronics is toward the use of low-voltage microelectronic systems that consume less power. However, the reduction in operating voltage also caries with it an increased susceptibility to radiation. In the case of application specific integrated microcircuits (ASIM's), advanced devices of this type, such as high density field programmable gate arrays (FPGA's) exhibit new single event effects (SEE), such as single particle reprogramming of anti-fuse links. New advanced bipolar circuits have been shown recently to degrade more rapidly in the low dose rate space environment than in the typical laboratory total dose radiation test used to qualify such devices. Thus total dose testing of these parts is no longer an appropriately conservative measure to be used for hardness assurance. We also note that the functionality of micromechanical Si-based devices may be altered due to the radiation-induced deposition of charge in the oxide passivation layers.

Barnes, C.↗
NASA NTRS1986

Test and evaluation of a multifunction keyboard and a dedicated keyboard for control of a flight management computer

A flight management computer (FMC) control display unit (CDU) test was conducted to compare two types of input devices: a fixed legend (dedicated) keyboard and a programmable legend (multifunction) keyboard. The task used for comparison was operation of the flight management computer for the Boeing 737-300. The same tasks were performed by twelve pilots on the FMC control display unit configured with a programmable legend keyboard and with the currently used B737-300 dedicated keyboard. Flight simulator work activity levels and input task complexity were varied during each pilot session. Half of the points tested were previously familiar with the B737-300 dedicated keyboard CDU and half had no prior experience with it. The data collected included simulator flight parameters, keystroke time and sequences, and pilot questionnaire responses. A timeline analysis was also used for evaluation of the two keyboard concepts.

Crane, J. M.↗
NASA NTRS2010

Flexible Peripheral Component Interconnect Input/Output Card

The Flexible Peripheral Component Interconnect (PCI) Input/Output (I/O) Card is an innovative circuit board that provides functionality to interface between a variety of devices. It supports user-defined interrupts for interface synchronization, tracks system faults and failures, and includes checksum and parity evaluation of interface data. The card supports up to 16 channels of high-speed, half-duplex, low-voltage digital signaling (LVDS) serial data, and can interface combinations of serial and parallel devices. Placement of a processor within the field programmable gate array (FPGA) controls an embedded application with links to host memory over its PCI bus. The FPGA also provides protocol stacking and quick digital signal processor (DSP) functions to improve host performance. Hardware timers, counters, state machines, and other glue logic support interface communications. The Flexible PCI I/O Card provides an interface for a variety of dissimilar computer systems, featuring direct memory access functionality. The card has the following attributes: 8/16/32-bit, 33-MHz PCI r2.2 compliance, Configurable for universal 3.3V/5V interface slots, PCI interface based on PLX Technology's PCI9056 ASIC, General-use 512K 16 SDRAM memory, General-use 1M 16 Flash memory, FPGA with 3K to 56K logical cells with embedded 27K to 198K bits RAM, I/O interface: 32-channel LVDS differential transceivers configured in eight, 4-bit banks; signaling rates to 200 MHz per channel, Common SCSI-3, 68-pin interface connector.

Bigelow, Kirk K.↗
NASA NTRS2016

Usable Translational Hand Controllers for NASA's Habitability Design Center

This summer I was given the opportunity to work at the Habitability Design Center (HDC). NASA Johnson Space Center's HDC is currently developing Cislunar and Mars spacecraft mockups. I contributed to this effort by designing from scratch low cost, functional translational hand controllers (THCs) that will be used in spacecraft mission simulation in low to medium fidelity exploration spacecraft mockups. This project fell under the category of mechatronics, a combination of mechanical, electrical, and computer engineering. Being an aerospace engineering student, I was out of my comfort zone. And that was a wonderful thing. The autonomy that my mentor, Dr. Robert Howard, allowed me gave me the opportunity to learn by trying, failing, and trying again. This project was not only a professional success for me, but a significant learning experience. I appreciated the freedom that I had to take the time to learn new things for myself rather than blindly follow instructions. I was the sole person working on this project, and was required to work independently to solve the many hardware and software challenges that the project entailed. I researched THCs that have been used on the ISS, the Space Shuttle, and the Orion MPVC and based my design off of these. I worked through many redesigns before finding an optimal configuration of the necessary mechanisms and electrical components for the THC. Once I had a functional hardware design, I dove into the challenge of getting an Arduino Uno, an extremely low cost and easily programmable microcontroller, to behave as a human interface device. The THCs I built needed to be able to integrate to a mission simulation designed by NASA's Graphics and Visualization Lab. This proved to be the most challenging aspect of the project. To accomplish this I learned how to change the firmware of the USB serial converter microcontroller. The process was very complicated as it involved multiple software programs and manual flashing of pins on the Arduino itself. When I successfully achieved the goal I wrote an instructions manual for the process so that the HDC will be able to do this easily in the future for any human interface device they may want to create. I also created a detailed CAD model of my THC design with construction instructions. My THC utilizes three ultrasonic sensors, one for each axis of motion. I wrote a code that stimulates these sensors continuously and feeds back values from each axis ranging from -%100 to %100 of the min/max position in relation to the neutral position of each axis. This was the data that the Graphics and Visualization Lab required to interface with their simulation. I truly enjoyed working in the HDC surrounded by passionate, proactive, and brilliantly creative people. I felt valued and respected as a part of their team. I was given the time and support of my mentor whenever I asked for it. Beyond my positive project experience, I was fortunate enough to be able to take advantage of many of the extra activities that JSC has to offer. I took Russian Phase One during my lunch break every day and can now read Russian and accomplish basic verbal communication. I was heavily involved with the co-tern music video, which led to numerous incredible experiences and friendships. I saw every facility, attended every lecture, and met everyone that I could. I had coffee with Lauri Hansen. I played on an intern volleyball team at the Gilruth. I traveled to Michoud, Stennis, NOLA, and Big Bend National Park. I had the time of my life and I fell in love with JSC. In the next month I will return to Maryland and start my senior year of my undergraduate degree. As I work through it I will remember that all of the studying I do, all of the concentration I give, and all of the sacrifices that I make for school are so that I can work at a place like JSC where I am proud and excited to go into work every day. This internship was an invaluable experience for me, both professionally and personally.

Westbrook, Kimberly↗
NASA NTRS2011

S-Band POSIX Device Drivers for RTEMS

This is a set of POSIX device driver level abstractions in the RTEMS RTOS (Real-Time Executive for Multiprocessor Systems real-time operating system) to SBand radio hardware devices that have been instantiated in an FPGA (field-programmable gate array). These include A/D (analog-to-digital) sample capture, D/A (digital-to-analog) sample playback, PLL (phase-locked-loop) tuning, and PWM (pulse-width-modulation)-controlled gain. This software interfaces to Sband radio hardware in an attached Xilinx Virtex-2 FPGA. It uses plug-and-play device discovery to map memory to device IDs. Instead of interacting with hardware devices directly, using direct-memory mapped access at the application level, this driver provides an application programming interface (API) offering that easily uses standard POSIX function calls. This simplifies application programming, enables portability, and offers an additional level of protection to the hardware. There are three separate device drivers included in this package: sband_device (ADC capture and DAC playback), pll_device (RF front end PLL tuning), and pwm_device (RF front end AGC control).

Lux, James P.↗
NASA NTRS2017

Digital Device Architecture and the Safe Use of Flash Devices in Munitions

Flash technology is being utilized in fuzed munition applications and, based on the development of digital logic devices in the commercial world, usage of flash technology will increase. Digital devices of interest to designers include flash-based microcontrollers and field programmable gate arrays (FPGAs). Almost a decade ago, a study was undertaken to determine if flash-based microcontrollers could be safely used in fuzes and, if so, how should such devices be applied. The results were documented in the Technical Manual for the Use of Logic Devices in Safety Features. This paper will first review the Technical Manual and discuss the rationale behind the suggested architectures for microcontrollers and a brief review of the concern about data retention in flash cells. An architectural feature in the microcontroller under study will be discussed and its use will show how to screen for weak or failed cells during manufacture, storage, or immediately prior to use. As was done for microcontrollers a decade ago, architectures for a flash-based FPGA will be discussed, showing how it can be safely used in fuzes. Additionally, architectures for using non-volatile (including flash-based) storage will be discussed for SRAM-based FPGAs.

Katz, Richard B.↗
NASA NTRS2007

Filling the Assurance Gap on Complex Electronics

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled by software, such as communication protocols. For example, the James Webb Space Telescope will use Field Programmable Gate Arrays (FPGAs), which can have over a million logic gates, to send telemetry. System-on-chip (SoC) devices, another type of complex electronics, can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, mature software methodologies have been proposed, with slight modifications, to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and bugs can be detected earlier in the development cycle, thus creating a development process for CE that can be easily maintained and configurable based on the device used.

Plastow, Richard A.↗
NASA NTRS1987

Implementation of a robotic flexible assembly system

As part of the Intelligent Task Automation program, a team developed enabling technologies for programmable, sensory controlled manipulation in unstructured environments. These technologies include 2-D/3-D vision sensing and understanding, force sensing and high speed force control, 2.5-D vision alignment and control, and multiple processor architectures. The subsequent design of a flexible, programmable, sensor controlled robotic assembly system for small electromechanical devices is described using these technologies and ongoing implementation and integration efforts. Using vision, the system picks parts dumped randomly in a tray. Using vision and force control, it performs high speed part mating, in-process monitoring/verification of expected results and autonomous recovery from some errors. It is programmed off line with semiautomatic action planning.

Benton, Ronald C.↗
NASA NTRS2001

Microshutter Arrays for the NGST NIRSpec

We are developing a programmable multiobject field selector for the NGST NIRSpec. This device is a microshutter array, a close-packed 2000 x 2000 array of 100 micrometer x 100 micrometer shutters fabricated with Micro-ElectroMechanical Systems (MEMS) technologies. The shutters are opened using a magnet scanned over the array. The shutters are held open by electrostatic potentials on adjacent vertical electrodes. Modeling of the magnetic actuation of the microshutters allowed optimization of the magnetic field configuration, the distance between magnet and shutters, and the force and torque produced by the magnet. The results of laboratory tests are consistent with our modeling. We have demonstrated actuation, latching and addressing. We are able to rotate shutters out of the plane up to 90 degree and more, to latch them electrostatically to the walls and release them selectively. During the last six month all critical elements of the array have been demonstrated. Fabrication processes were developed to deposit vertical electrodes on support grid side walls and insulated light-shields that block the gaps between shutters and the support grid. Physical optics analysis was performed to assess the expected optical performance of the microshutters. A preliminary Fourier optics analysis on the microshutter array performance has been carried out. More detailed analysis of wave propagation through 3D structures is a next step. An optical test station for verifying optical parameters of the shutter array at room temperature has been developed. It allows to measure parameters, such as transmission, scattering, contrast ratio, and diffraction of the array structure. Initial data have been acquired and are being analyzed and compared to theoretical predictions.

Moseley, Harvey↗