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6U SpaceVPX Multi Processor Module: Preliminary Concept [Slides]
Abstract not provided.
Understanding HPC Benchmark Performance on Intel Broadwell and Cascade Lake Processors
Hardware platforms in high performance computing are constantly getting more complex to handle even when considering multicore CPUs alone. Numerous features and configuration options in the hardware and the software environment that are relevant for performance are not even known to most application users or developers. Microbenchmarks, i.e., simple codes that fathom a particular aspect of the hardware, can help to shed light on such issues, but only if they are well understood and if the results can be reconciled with known facts or performance models. The insight gained from microbenchmarks may then be applied to real applications for performance analysis or optimization. In this paper we investigate two modern Intel x86 server CPU architectures in depth: Broadwell EP and Cascade Lake SP. We highlight relevant hardware configuration settings that can have a decisive impact on code performance and show how to properly measure on-chip and off-chip data transfer bandwidths. The new victim L3 cache of Cascade Lake and its advanced replacement policy receive due attention. Finally we use DGEMM, sparse matrix-vector multiplication, and the HPCG benchmark to make a connection to relevant application scenarios.
Multiscale System Modeling of Single Event Induced Faults in Advanced Node Processors.
Abstract not provided.
Achieving Extreme Heterogeneity: CoDesign using Neuromorphic Processors.
Abstract not provided.
6U SpaceVPX/OpenVPX Payload Processor [Slides]
The slides show a space-grade single-board computer that is flexible and reconfigurable, with commercial interoperability. Design trade-offs are described.
Using pygsti for quantum processor characterization and benchmarking .
Abstract not provided.
Towards multi-qudit quantum processor using superconducting RF cavities
Superconducting radio-frequency (SRF) cavities made using high-purity Niobium can reach single photon lifetimes longer than a second with proper treatment [1]. These resonator cavities are thus an excellent choice for storing higher-dimensional quantum states. However, preparing and manipulating quantum states with larger photon numbers require a nonlinear component, like a transmon, with a sufficiently long coherence time. With the advancement in materials processing enabling coherence times for transmons exceeding hundreds of micro-seconds, one can encode and process quantum information using d-levels (qudit) of the resonators. In this talk, we will present preliminary results showing the control of a single-qudit and our progress toward building multi-qudit architecture using multi-mode SRF cavities.
Quantum Memories, Processors and Transducers
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Sample-efficient verification of continuously-parameterized quantum gates for small quantum processors
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Using Neuromorphic Processors to Model Biological Neural Processing: Synthetic Cognition in a Neuromorphic Agent?
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Robust resonator-assisted ZZ cancellation in superconducting quantum processors
Strong qubit interactions are essential for faster two-qubit gates, but they often come with undesirable ZZ interactions that limit gate fidelity. Existing methods to mitigate these interactions, such as flux-tunable couplers, can introduce additional noise and complexity. In contrast, our work presents a simpler, more robust approach using a driven resonator to cancel the static ZZ interaction between qubits [1]. The experiment was performed on a revised 9-qubit quantum processing unit from Rigetti, developed in collaboration with SQMS scientists. We validate the resonator-induced-phase (RIP) interaction, where an off-resonant drive on the resonator dynamically cancels ZZ coupling. This marks an important step toward high gate fidelities. We also explore the entangling gates enabled by this coupling scheme, focusing on minimizing gate duration and qubit decoherence while maintaining effective ZZ cancellation.
Characterizing Quasistatic Noise in Quantum Processors
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Feedback-based calibration for rapid tuning and drift control of quantum processors
This presentation will cover an abstract that has been submitted to the conference, but will not include a paper publication. The presentation details an experimental method for calibrating quantum bits and quantum circuits. All of the data on the slides has been gathered via PyGSTi, an open-source Python-based software developed by Sandia's Quantum Performance Laboratory.