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At least 145 records · Page 8

Superconducting disordered neural networks for neuromorphic processing with fluxons

In superconductors, magnetic fields are quantized into discrete fluxons (flux quanta Φ 0 ), made of microscopic circulating supercurrents. We introduce a multiterminal synapse network comprising a disordered array of superconducting loops with Josephson junctions. The loops can trap fluxons defining memory, while the junctions allow their movement between loops. Dynamics of fluxons through such a disordered system through a complex reconfigurable energy landscape represents brain-like spiking information flow. In this work, we experimentally demonstrate a three-loop network using YBa 2 Cu 3 O 7 –δ -based superconducting loops and Josephson junctions, which exhibit stable memory configurations of trapped flux in loops that determine the rate of flow of fluxons through synaptic connections. The memory states are, in turn, affected by the applied input signals but can also be externally configured electrically through control current/feedback terminals. These results establish a previously unexplored, biologically similar architectural approach to neuromorphic computing that is scalable while dissipating energy of atto Joules/spike.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Selective area doping for Mott neuromorphic electronics

The cointegration of artificial neuronal and synaptic devices with homotypic materials and structures can greatly simplify the fabrication of neuromorphic hardware. We demonstrate experimental realization of vanadium dioxide (VO 2 ) artificial neurons and synapses on the same substrate through selective area carrier doping. By locally configuring pairs of catalytic and inert electrodes that enable nanoscale control over carrier density, volatility or nonvolatility can be appropriately assigned to each two-terminal Mott memory device per lithographic design, and both neuron- and synapse-like devices are successfully integrated on a single chip. Feedforward excitation and inhibition neural motifs are demonstrated at hardware level, followed by simulation of network-level handwritten digit and fashion product recognition tasks with experimental characteristics. Spatially selective electron doping opens up previously unidentified avenues for integration of emerging correlated semiconductors in electronic device technologies.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Low Power Hardware-In-The-Loop Neuromorphic Training Accelerator

The training process for spiking neural networks can be very computationally intensive. Approaches such as evolutionary algorithms may require evaluating thousands or millions of candidate solutions. In this work, we propose using neuromorphic cores implemented on a Xilinx Zynq system on chip to accelerate and improve the energy efficiency of the evaluation step of an evolutionary training approach. We demonstrate this can significantly reduce the required energy to evolve a network with some cases showing greater than 10 times improvement as compared to a CPU-only system.

Mitchell, Parker↗

AI-Powered Knowledge Graphs for Neuromorphic and Energy-Efficient Computing

The surge in scientific literature obscures breakthroughs and hinders the discovery of new research paths. We propose an artificial intelligence (AI) powered framework using large language models (LLMs) and knowledge graphs (KGs) to automate parts of scientific discovery, focusing on energy-efficient AI circuits. Our hybrid approach combines LLMs, structured data, and ontology-based reasoning to construct a comprehensive knowledge graph that integrates insights across computational neuroscience, spiking neuron models, learning rules, architectural motifs, and neuromorphic device technologies. This multi-domain representation enables the generation of hypotheses that connect biological function with implementable, energy-efficient hardware architectures. Using KG embeddings and graph neural networks, the framework generates hypotheses for novel circuits, validates them through optimization on exascale HPC systems, and with tools like SuperNeuro and Fugu, the most promising designs will be prototyped in hardware. This open-source system aims to accelerate discoveries and bridging neuroscience with hardware innovation, drive collaboration, and unlock new opportunities in low-power AI computing.

Gautam, Ashish [ORNL]↗

ObstacleSense: Low-Power Neuromorphic Vision for Corridor Obstacle Awareness in Low-Level ADAS

The automotive industry’s pursuit of Level 5 autonomy is constrained by substantial perception-compute power requirements, often reaching 1, 000 + watts in full autonomy stacks. Reducing this energy burden requires rethinking perception not only at the high-end autonomy level, but also at the foundational Advanced Driver Assistance Systems (ADAS) level where low-power, safety-critical sensing can have broad impact. Neuromorphic vision provides a promising starting point: HD Dynamic Vision Sensors (DVS) can operate below 100 mW at the sensor level by reporting only asynchronous brightness changes. However, low-power sensing alone is insufficient if downstream perception reintroduces dense, energy-intensive computation. In particular, many event-driven object-detection pipelines still rely on CNN backbones, while purely spiking alternatives often trade away accuracy or ignore deployment constraints. We introduce ObstacleSense, a highly compact, CNN-free hybrid ANN–SNN framework for Level 0–1 forward-corridor obstacle awareness. Instead of performing full-scene object detection with a convolutional feature backbone, ObstacleSense targets the safety-critical question of whether the ego corridor is occupied and how far the nearest obstacle is. The architecture combines polarity-conditioned event encoding, lightweight temporal spiking dynamics, axial spatial mixing, and coarse-to-fine range estimation within a regular fixed-grid compute pattern. This design avoids the dense CNN backbone commonly used in event-based detection while maintaining a small state footprint suitable for eventual small-FPGA deployment. Before hardware mapping, we evaluate the software implementation using a model-side power proxy derived from MACs, weight and activation traffic, and spiking state updates under shared FP16 assumptions. On simulated CARLA event corpora, the deployment-oriented model achieves 0.9464 objectness F1, 0.9978 grid-level mAP, and 0.8987 m distance Mean Absolute Error at an estimated 1.92 mW proxy cost, while maintaining performance on unseen generalization test sequences.

Johnson-Scott, Zac [ORNL]↗

Neuromorphic Backpropagation Algorithm Software

This software is an implementation of the backpropagation algorithm for Intel's neuromorphic research processor, Loihi. The software implements the neural circuit itself and a demonstration application where the MNIST dataset (a standard test problem) is used to train a neural network.

Sornborger, Andrew↗

Analytical Tool to evaluate Heterogeneous Neuromorphic Architectures (ATHENA)

SAND2022-7062 O The Analytical Tool to Evaluate Heterogeneous Neuromorphic Architectures (ATHENA) quickly evaluates performance metrics like energy, area, and latency for an AI/ML network. It currently supports the evaluation of analog neural networks. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525.

Hahn, Andrew↗

High accuracy single-layer free-space diffractive neuromorphic classifiers for spatially incoherent light

Free-space all-optical diffractive systems have shown promise for neuromorphic classification of objects without converting light to the electronic domain. While the factors that govern these systems have been studied for coherent light, the fundamental properties for incoherent light have not been addressed, despite the importance for many applications. Here we use a co-design approach to show that optimized systems for spatially incoherent light can achieve performance on par with the best linear electronic classifiers even with a single layer containing few diffractive features. This performance is limited by the inherent linear nature of incoherent optical detection. We circumvent this limit by using a differential detection scheme that achieves greater than 94% classification accuracy on the MNIST dataset and greater than 85% classification accuracy for Fashion-MNIST, using a single layer metamaterial.

Léonard, François (ORCID:0000000249736743)↗

Low-Power Deep Learning Inference using the SpiNNaker Neuromorphic Platform

n this presentation we will discuss recent results on using the SpiNNaker neuromorphic platform (48-chip model) for deep learning neural network inference. We use the Sandia Labs developed Whet stone spiking deep learning library to train deep multi-layer perceptrons and convolutional neural networks suitable for the spiking substrate on the neural hardware architecture. By using the massively parallel nature of SpiNNaker, we are able to achieve, under certain network topologies, substantial network tiling and consequentially impressive inference throughput. Such high-throughput systems may have eventual application in remote sensing applications where large images need to be chipped, scanned, and processed quickly. Additionally, we explore complex topologies that push the limits of the SpiNNaker routing hardware and investigate how that impacts mapping software-implemented networks to on-hardware instantiations.

97 MATHEMATICS AND COMPUTING↗

ATHENA: Analytical Tool for Heterogeneous Neuromorphic Architectures

The ASC program seeks to use machine learning to improve efficiencies in its stockpile stewardship mission. Moreover, there is a growing market for technologies dedicated to accelerating AI workloads. Many of these emerging architectures promise to provide savings in energy efficiency, area, and latency when compared to traditional CPUs for these types of applications — neuromorphic analog and digital technologies provide both low-power and configurable acceleration of challenging artificial intelligence (AI) algorithms. If designed into a heterogeneous system with other accelerators and conventional compute nodes, these technologies have the potential to augment the capabilities of traditional High Performance Computing (HPC) platforms [5]. This expanded computation space requires not only a new approach to physics simulation, but the ability to evaluate and analyze next-generation architectures specialized for AI/ML workloads in both traditional HPC and embedded ND applications. Developing this capability will enable ASC to understand how this hardware performs in both HPC and ND environments, improve our ability to port our applications, guide the development of computing hardware, and inform vendor interactions, leading them toward solutions that address ASC’s unique requirements.

97 MATHEMATICS AND COMPUTING↗

Event-Driven Neuromorphic Accelerator (Caspian)

Software repository for the Caspian neuromorphic system. In order to deploy small, low-power spiking neural networks at the edge, there needs to be 1) an FPGA design for an event simulator to evaluate these neural networks as well as 2) a high-performance cycle-accurate simulator for training these spiking neural networks. This software package solves these problems by providing the Caspian simulator and the µCaspian hardware design in SystemVerilog.

Mitchell, JohnParker [Microsoft Corporation, Redmo↗

The organic redox transistor for neuromorphic computing

Inspired by the in-memory computing architectures of biological systems, neuromorphic computing using crossbar arrays of artificial synapses based on non-volatile memory (NVM) devices with variable conductances has emerged as a new paradigm to enable massively parallel and ultra-low power computing hardware for data centric applications. Although inference has been demonstrated successfully using crossbars based on a variety of NMV technologies, efficient learning and scaling to large arrays (>10 6 elements) remains a challenge due to the synaptic elements' non-ideal electrical characteristics which degrades ANN accuracy. A further challenge is that in the conductive state memristors draw large currents >μA resulting in significant voltage drops in the interconnect wires and increased probability of failure in scaled arrays. We suggest the organic polymer redox transistor (RT) is an alternate approach that could solve many of these challenges, enabling both inference and parallel outer product updates, as recently demonstrated by Fuller et al. An RT consists of redox-active channel and gate electrodes in contact with a liquid or solid electrolyte. lon insertion through the electrolyte controls the channel electronic conductivity, while electron transfer through an external circuit maintains overall charge neutrality. Unlike a rechargeable battery, in the RT the voltage built-up across the electrolyte is kept to a minimum (typically <100 mV) by using the same material for the gate and channel. Elimination of the voltage offset simplifies integration of the RT into programmable arrays by enabling the use of various selectors. RTs based on inorganic and organic materials have been recently demonstrated with conductance tuning occurring at potentials of just a few mV and hundreds to thousands of linearly and symmetrically programmable conductance states, enabling near ideal accuracy in neural network simulations. Introduced in the 1980's, redox transistors with metallic gate electrodes and organic channel materials, also known as organic electrochemical transistors (OECTs), have been explored for a variety of applications such as chem- and bio-sensing, neural interfaces, and low cost printed circuits. A typical channel material for OECTs is the conducting polymer poly(3,4-ethylenedioxythiophene) doped with poly(styrene sulfonate) (PEDOT:PSS). PEDOT is a p-type semiconducting polymer with mobile positively charged polarons that hop chain-to-chain.

Talin, Albert Alec↗

Nanostructured devices having perovskite nanocrystal layer for photodetection, optical memory, and neuromorphic functionality

The present disclosure relates to a device that includes a perovskite nanocrystal (NC) layer, a charge separating layer, an insulating layer, a gate electrode, a cathode, and an anode, where the charge separating layer is positioned between the perovskite NC layer and the insulating layer, the insulating layer is positioned between the charge separating layer and the gate electrode, and the cathode and the anode both electrically contact the charge separating layer and the insulating layer. In some embodiments of the present disclosure, the device may be configured to operate as at least one of a photodetector, an optical switching device, and/or a neuromorphic switching device.

Blackburn, Jeffrey Lee↗

Biomaterial–Based Solid–Electrolyte Organic Electrochemical Transistors for Electronic and Neuromorphic Applications

In this work a systematic study of biomaterial–based solid–state organic electrochemical transistors (OECTs) is presented in which biogels consisting of gelatin and glycerol, two food–grade materials, are chosen as the model solid electrolyte. Such gels are fundamentally attractive for bioelectronics and wearable applications due to their superior and tunable electrical and mechanical properties, which allow one to fabricate solid–state organic transistors with high ON/OFF ratio and transconductance, possible millisecond–switching speed, and 6–month stability in ambient air. Next, the authors show a good control of the state–retention property of biogel OECTs, demonstrated herein by employing them as artificial synapses with various synaptic functions, such as frequency–based short–term plasticity. This study herein paves the way for the development of biomaterial–based electronics by providing guiding principles for future works that employ biomaterials in OECTs.

36 MATERIALS SCIENCE↗

Ultra-Fast Non-Volatile Resistive Switching Devices with Over 512 Distinct and Stable Levels for Memory and Neuromorphic Computing

Low-current multilevel programmability with inherent non-volatility and high stability of resistance states is required for both multi-bit memory storage and deep learning accelerators but is difficult to achieve. Here, in a resistive switching system, this work realizes >512 (>9 bits) distinct non-volatile conductance levels with stable retention for each state with current levels down to the nanoampere range, highly promising for potential integration with small processing nodes with ultra-low power consumption requirements. This is achieved by demonstrating a new thin film design concept that encompasses three key features: an ultra-thin epitaxial oxygen ionic switching layer that provides a tunable energy barrier at the bottom electrode, an overcoat amorphous layer that acts as an ion migration barrier for stable state retention, and a partial conductive filament as a localized electronic transport channel to the epitaxial switching layer. A large dynamic resistance range of up to seven orders of magnitude is achieved with reset-free transitions among intermediate states, and programmability is demonstrated with ultra-fast (20 ns) pulses. Artificial neural network (ANN) simulations, based on the experimental performance and its non-idealities, demonstrate close-to-ideal inference accuracies for various Modified National Institute of Standards and Technology (MNIST) data sets.

36 MATERIALS SCIENCE↗

Reconfigurable Cascaded Thermal Neuristors for Neuromorphic Computing

While the complementary metal-oxide semiconductor (CMOS) technology is the mainstream for the hardware implementation of neural networks, an alternative route is explored based on a new class of spiking oscillators called “thermal neuristors”, which operate and interact solely via thermal processes. Utilizing the insulator-to-metal transition (IMT) in vanadium dioxide, a wide variety of reconfigurable electrical dynamics mirroring biological neurons is demonstrated. Notably, inhibitory functionality is achieved just in a single oxide device, and cascaded information flow is realized exclusively through thermal interactions. To elucidate the underlying mechanisms of the neuristors, a detailed theoretical model is developed, which accurately reflects the experimental results. In conclusion, this study establishes the foundation for scalable and energy-efficient thermal neural networks, fostering progress in brain-inspired computing.

36 MATERIALS SCIENCE↗