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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Modular system changes its architecture to maximize either reliability or capacity. Reconfigurable computer is assembled from four kinds of modules: organizer/scheduler, memory, input/output processor, and central processor. Reconfiguration is initiated by a signal from a control panel or by fault interrupt from one of the modules.
A progam to evaluate, design and demonstrate major advances in control and monitor instrumentation was undertaken. A carbon dioxide removal process, one whose maturity level makes it a prime candidate for early flight demonstration was investigated. The instrumentation design incorporates features which are compatible with anticipated flight requirements. Current electronics technology and projected advances are included. In addition, the program established commonality of components for all advanced life support subsystems. It was concluded from the studies and design activities conducted under this program that the next generation of instrumentation will be greatly smaller than the prior one. Not only physical size but weight, power and heat rejection requirements were reduced in the range of 80 to 85% from the former level of research and development instrumentation. Using a microprocessor based computer, a standard computer bus structure and nonvolatile memory, improved fabrication techniques and aerospace packaging this instrumentation will greatly enhance overall reliability and total system availability.
The feasibility of using the rapidly growing technology of the shape memory alloys actuators in actively controlling the buckling of large flexible structures is investigated. The need for such buckling control systems is becoming inevitable as the design trends of large space structures have resulted in the use of structural members that are long, slender, and very flexible. In addition, as these truss members are subjected mainly to longitudinal loading they become susceptible to structural instabilities due to buckling. Proper control of such instabilities is essential to the effective performance of the structures as stable platforms for communication and observation. Mathematical models are presented that simulate the dynamic characteristics of the shape memory actuator, the compressive structural members, and the associated active control system. A closed-loop computer-controlled system is designed, based on the developed mathematical models, and implemented to control the buckling of simple beams. The performance of the computer-controlled system is evaluated experimentally and compared with the theoretical predictions to validate the developed models. The obtained results emphasize the importance of buckling control and suggest the potential of the shape memory actuators as attractive means for controlling structural deformation in a simple and reliable way.
A document concisely describes a ring bus architecture for a proposed solid-state recorder (SSR) that would serve as buffer of data to be transmitted from a spacecraft to Earth. This architecture would afford fault tolerance needed for reliable operation in an anticipated high-radiation environment in which traditional SSRs cannot operate reliably. Features of the architecture include one or more controller boards and multiple memory boards interconnected in a ringlike topology. The interconnections would be high-speed serial links complying with the Institute of Electrical and Electronics Engineers (IEEE) standard 1393 (which pertains to a spaceborne fiber-optic data bus). Accordingly, each controller and memory board would be equipped with an IEEE-1393-compliant ring-bus-interface unit. The ringlike topology and the multiplicity of memory boards (and, optionally, of controller boards) would afford the redundancy needed for fault tolerance. Each board would be a fault-containment region. The IEEE 1393 links could be routed so that the SSR would continue to function even in the event of multiple failures. This architecture would also support scalability over a wide range. In a fully redundant configuration, it could accommodate between 1 and 125 memory boards.
Virtual Sensor Test Instrumentation is based on the concept of smart sensor technology for testing with intelligence needed to perform sell-diagnosis of health, and to participate in a hierarchy of health determination at sensor, process, and system levels. A virtual sensor test instrumentation consists of five elements: (1) a common sensor interface, (2) microprocessor, (3) wireless interface, (4) signal conditioning and ADC/DAC (analog-to-digital conversion/ digital-to-analog conversion), and (5) onboard EEPROM (electrically erasable programmable read-only memory) for metadata storage and executable software to create powerful, scalable, reconfigurable, and reliable embedded and distributed test instruments. In order to maximize the efficient data conversion through the smart sensor node, plug-and-play functionality is required to interface with traditional sensors to enhance their identity and capabilities for data processing and communications. Virtual sensor test instrumentation can be accessible wirelessly via a Network Capable Application Processor (NCAP) or a Smart Transducer Interlace Module (STIM) that may be managed under real-time rule engines for mission-critical applications. The transducer senses the physical quantity being measured and converts it into an electrical signal. The signal is fed to an A/D converter, and is ready for use by the processor to execute functional transformation based on the sensor characteristics stored in a Transducer Electronic Data Sheet (TEDS). Virtual sensor test instrumentation is built upon an open-system architecture with standardized protocol modules/stacks to interface with industry standards and commonly used software. One major benefit for deploying the virtual sensor test instrumentation is the ability, through a plug-and-play common interface, to convert raw sensor data in either analog or digital form, to an IEEE 1451 standard-based smart sensor, which has instructions to program sensors for a wide variety of functions. The sensor data is processed in a distributed fashion across the network, providing a large pool of resources in real time to meet stringent latency requirements.
Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.
This effort produces a fully-passive surface power generation capability for fuel cell technology. The concept replaces the actively pumped thermal management of a state of the art (SOA) fuel cell/electrolyzer stack with a passive 2-phase thermosyphon for heat transport and a passive shape memory actuating radiator for temperature management. The concept addresses NASA fuel cell technology roadmap needs for greater reliability and longer operating life by eliminating life limiting elements of SOA fuel cell system design that drive failure modes associated with moving parts and control complexity. Applications map to surface power (primary fuel cell), surface energy storage (regenerable fuel cell) and in-situ resource utilization (electrolyzer/unitized reversible fuel cell). The first year of this effort concluded with independent demonstrations of 2-phase thermosyphon heat transport from a simulated fuel cell and temperature driven actuation of a shape memory actuating radiator. Results are in-character with underlying physics and demonstrate the potential to realize the objectives of this concept. his effort produces a fully-passive surface power generation capability for fuel cell technology. The concept replaces the actively pumped thermal management of a state of the art (SOA) fuel cell/electrolyzer stack with a passive 2-phase thermosyphon for heat transport and a passive shape memory actuating radiator for temperature management.
The Solar Electric Propulsion Stage (SEPS) subsystem which consists of the computer, custom input/output (I/O) unit, and tape recorder for mass storage of telemetry data was studied. Computer software and interface requirements were developed along with computer and I/O unit design parameters. Redundancy implementation was emphasized. Reliability analysis was performed for the complete command computer sybsystem. A SEPS fault tolerant memory breadboard was constructed and its operation demonstrated.
Mathematical models are presented that simulate the dynamic characteristics of shape memory alloy actuators made of nickel-titanium alloy (Nitinol) controlling the buckling of compressive structural members. A closed-loop computer-controlled system has been designed, based on the proposed mathematical models, and has been implemented to control the buckling of simple beams. The performance of the computer-controlled system is evaluated experimentally and compared with the theoretical predictions to validate the developed models. The results emphasized the importance of buckling control and suggest the potential of shape memory alloy actuators as attractive means for controlling structural deformation in a simple and reliable way.
A parallel adaptive dynamic relaxation (ADR) algorithm has been developed for nonlinear structural analysis. This algorithm has minimal memory requirements, is easily parallelizable and scalable to many processors, and is generally very reliable and efficient for highly nonlinear problems. Performance evaluations on single-processor computers have shown that the ADR algorithm is reliable and highly vectorizable, and that it is competitive with direct solution methods for the highly nonlinear problems considered. The present algorithm is implemented on the 512-processor Intel Touchstone DELTA system at Caltech, and it is designed to minimize the extent and frequency of interprocessor communication. The algorithm has been used to solve for the nonlinear static response of two and three dimensional hyperelastic systems involving contact. Impressive relative speedups have been achieved and demonstrate the high scalability of the ADR algorithm. For the class of problems addressed, the ADR algorithm represents a very promising approach for parallel-vector processing.
Flexible, deployable arrays are an attractive alternative to conventional solar arrays for near-term and future space power applications, particularly due to their potential for high specific power and low storage volume. Combined with low-cost flexible thin-film photovoltaics, these arrays have the potential to become an enabling or an enhancing technology for many missions. In order to expedite the acceptance of thin-film photovoltaics for space applications, however, parallel development of flexible photovoltaics and the corresponding deployable structure is essential. Many innovative technologies must be incorporated in these arrays to ensure a significant performance increase over conventional technologies. For example, innovative mechanisms which employ shape memory alloys for storage latches, deployment mechanisms, and array positioning gimbals can be incorporated into flexible array design with significant improvement in the areas of cost, weight, and reliability. This paper discusses recent activities at Martin Marietta regarding the development of flexible, deployable solar array technology. Particular emphasis is placed on the novel use of shape memory alloys for lightweight deployment elements to improve the overall specific power of the array. Array performance projections with flexible thin-film copper-indium-diselenide (CIS) are presented, and government-sponsored solar array programs recently initiated at Martin Marietta through NASA and Air Force Phillips Laboratory are discussed.
A need exists for a standardized battery of human performance tests in order to measure the effects of various treatments. The present paper reports on progress in such a program, funded jointly by NASA and the Navy. Three batteries are available which differ in length (7.5, 15, and 30 minutes), and number of tests in the battery (3, 10, and 15). All tests are implemented on a portable, lap-held, briefcase-sized microprocessor (NEC PC 8201A). Performances measured include information processing, memory, visual perception, reasoning, motor skills, etc. Current programs are underway to determine norms, reliabilities, stabilities, factor structure of tests, comparisons with marker tests, apparatus suitability, etc.
Circuit includes a single-word input/output register and a multiword serial memory which are circulated in synchronism. It puts out data at a rate compatible with relatively slow-speed electromechanical devices.
Conventional mobility elements, such as pneumatic tires, suffer from a number of issues related to reliability. Two of the more prevalent problems are the high likelihood of single point failure owing to puncture (i.e. flat tire), and loss of efficiency due to reduction in tire pressure over time. In order to overcome these limitations, alternative compliant tire designs not requiring pneumatics have been developed. However, although current designs have significantly reduced the aforementioned issues, they tend to have their own set of limitations. First, non-pneumatic tires designed for high load applications often have restricted envelopment capability, making their performance less than optimal, especially on uneven terrain. Second, tires designed with larger envelopment capability tend to suffer from large amounts of plasticity (permanent deformation) or failure (rupture). Both of these limitations are the direct result of the choice of material being used for the design; conventional metals undergo plastic deformation at low strain while elastomer based designs are often too rigid for the localized deformations needed for high envelopment. Recent advancements at the NASA Glenn research center in a unique class of metals know as shape memory alloys (SMAs) has opened the design space for non-pneumatic compliant tire technologies allowing designs to incorporate orders of magnitude more deformation without damage. The work presented herein highlights the advantages of using SMAs as compared to conventional metals. Additionally, the development of a unique SMA compliant tire design capable of carrying up to 8.9 kN (2000 lbf) with reversible, local deformations on the order of the side wall height will be presented.
A multiple chip magnetic bubble memory cell design developed for NASA embodies the low power, low weight, environmental tolerance and reliability necessary for successful operation in spacecraft launch and mission environments. Packaging of multiple chips in a common magnetic bias, drive coil assembly reduces weight and volume overhead per chip and also reduces the number of coil drive components required. This 8 x 10 to the 5th bit cell is conduction cooled and provides a metal and ceramic sealed hermetic chip environment.
Magnetoresistive random-access memory (MRAM) is a non-volatile memory that exploits electronic spin, rather than charge, to store data. Instead of moving charge on and off a floating gate to alter the threshold voltage of a CMOS transistor (creating different bit states), MRAM uses magnetic fields to flip the polarization of a ferromagnetic material thus switching its resistance and bit state. These polarized states are immune to radiation-induced upset, thus making MRAM very attractive for space application. These magnetic memory elements also have infinite data retention and erase/program endurance. Presented here are results of reliability testing of two space-qualified MRAM products from Aeroflex and Honeywell.
Optimization of materials’ performance for specific applications often requires balancing multiple aspects of materials’ functionality. Even for the cases where a generative physical model of material behavior is known and reliable, this often requires search over multidimensional function space to identify low-dimensional manifold corresponding to the required Pareto front. In this work, we introduce the multi-objective Bayesian optimization (MOBO) workflow for the ferroelectric/antiferroelectric performance optimization for memory and energy storage applications based on the numerical solution of the Ginzburg–Landau equation with electrochemical or semiconducting boundary conditions. MOBO is a low computational cost optimization tool for expensive multi-objective functions, where we update posterior surrogate Gaussian process models from prior evaluations and then select future evaluations from maximizing an acquisition function. Using the parameters for a prototype bulk antiferroelectric (PbZrO 3 ), we first develop a physics-driven decision tree of target functions from the loop structures. We further develop a physics-driven MOBO architecture to explore multidimensional parameter space and build Pareto-frontiers by maximizing two target functions jointly—energy storage and loss. This approach allows for rapid initial materials and device parameter selection for a given application and can be further expanded toward the active experiment setting. The associated notebooks provide both the tutorial on MOBO and allow us to reproduce the reported analyses and apply them to other systems (https://github.com/arpanbiswas52/MOBO_AFI_Supplements).
In many applications, the limited density of the embedded SRAM does not allow integrating the memory on the same chip with other logic and functional blocks. In such cases, the embedded DRAM provides the optimum combination of very high density, low power, and high performance. For ASIC's to take full advantage of this design strategy, an efficient and highly reliable DRAM compiler must be used. The embedded DRAM architecture, cell, and peripheral circuit design considerations and the algorithm of a high performance memory compiler are presented .