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At least 145 records · Page 8

Solar Particle Induced Upsets in the TDRS-1 Attitude Control System RAM During the October 1989 Solar Particle Events

The three large solar particle events, beginning on October 19, 1989 and lasting approximately six days, were characterized by high fluences of solar protons and heavy ions at 1 AU. During these events, an abnormally large number of upsets (243) were observed in the random access memory of the attitude control system (ACS) control processing electronics (CPE) on-board the geosynchronous TDRS-1 (Telemetry and Data Relay Satellite). The RAM unit affected was composed of eight Fairchild 93L422 memory chips. The Galileo spacecraft, launched on October 18, 1989 (one day prior to the solar particle events) observed the fluxes of heavy ions experienced by TDRS-1. Two solid-state detector telescopes on-board Galileo, designed to measure heavy ion species and energy, were turned on during time periods within each of the three separate events. The heavy ion data have been modeled and the time history of the events reconstructed to estimate heavy ion fluences. These fluences were converted to effective LET spectra after transport through the estimated shielding distribution around the TDRS-1 ACS system. The number of single event upsets (SEU) expected was calculated by integrating the measured cross section for the Fairchild 93L422 memory chip with average effective LET spectrum. The expected number of heavy ion induced SEU's calculated was 176. GOES-7 proton data, observed during the solar particle events, were used to estimate the number of proton-induced SEU's by integrating the proton fluence spectrum incident on the memory chips, with the two-parameter Bendel cross section for proton SEU'S. The proton fluence spectrum at the device level was gotten by transporting the protons through the estimated shielding distribution. The number of calculated proton-induced SEU's was 72, yielding a total of 248 predicted SEU'S, very dose to the 243 observed SEU'S. These calculations uniquely demonstrate the roles that solar heavy ions and protons played in the production of SEU's during the October 1989 solar particle events.

Croley, D. R.↗

Decoding of DBEC-TBED Reed-Solomon codes

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256 K bit DRAM's are organized in 32 K x 8 bit-bytes. Byte-oriented codes such as Reed-Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. The paper presents a special decoding technique for double-byte-error-correcting, triple-byte-error-detecting RS codes which is capable of high-speed operation. This technique is designed to find the error locations and the error values directly from the syndrome without having to use the iterative algorithm to find the error locator polynomial.

Deng, Robert H.↗

Development of a character, line and point display system

A compact graphics terminal for use as the input to a computerized medical records system is described. The principal mode of communication between the terminal and the records system is by checklists and menu selection. However, the terminal accepts short, handwritten messages as well as conventional alphanumeric input. The terminal consists of an electronic tablet, a display, a microcomputer controller, a character generator, and a refresh memory for the display. An Intel SBC 80/10 microcomputer controls the flow of information and a 16 kilobyte memory stores the point-by-point array of information to be displayed. A specially designed interface continuously generates the raster display without the intervention of the microcomputer.

Owen, E. W.↗

Digital control of diode laser for atmospheric spectroscopy

A system is described for remote absorption spectroscopy of trace species using a diode laser tunable over a useful spectral region of 50 to 200 cm(-1) by control of diode laser temperature over range from 15 K to 100 K, and tunable over a smaller region of typically 0.1 to 10 cm(-1) by control of the diode laser current over a range from 0 to 2 amps. Diode laser temperature and current set points are transmitted to the instrument in digital form and stored in memory for retrieval under control of a microprocessor during measurements. The laser diode current is determined by a digital to analog converter through a field effect transistor for a high degree of ambient temperature stability, while the laser diode temperature is determined by set points entered into a digital to analog converter under control of the microprocessor. Temperature of the laser diode is sensed by a sensor diode to provide negative feedback to the temperature control circuit that responds to the temperature control digital to analog converter.

Menzies, R. T.↗

The simplification of fuzzy control algorithm and hardware implementation

The conventional interface composition algorithm of a fuzzy controller is very time and memory consuming. As a result, it is difficult to do real time fuzzy inference, and most fuzzy controllers are realized by look-up tables. Here, researchers derive a simplified algorithm using the defuzzification mean of maximum. This algorithm takes shorter computation time and needs less memory usage, thus making it possible to compute the fuzzy inference on real time and easy to tune the control rules on line. A hardware implementation based on a simplified fuzzy inference algorithm is described.

Wu, Z. Q.↗

Fast decoding techniques for extended single-and-double-error-correcting Reed Solomon codes

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. For example, some 256K-bit dynamic random access memories are organized as 32K x 8 bit-bytes. Byte-oriented codes such as Reed Solomon (RS) codes provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. Some special high speed decoding techniques for extended single and double error correcting RS codes. These techniques are designed to find the error locations and the error values directly from the syndrome without having to form the error locator polynomial and solve for its roots.

Costello, D. J., Jr.↗

Type U CAMAC crate controller for the Spacelab multi-crate, multi-processor system

A set of standard CAMAC modules for Spacelab payloads is being developed by NASA. A crate controller, a processor module, memory modules and a databus to connect them are being developed at the Goddard Space Flight Center. These components will provide for the implementation of CAMAC data systems ranging in complexity from fixed-format, single-crate data collection systems not requiring a processor to a multi-crate data system, including several computers (processors). The Spacelab CAMAC data system is introduced with the role of the crate controller described. The implementation and operation of the crate controller is described. The instruction set of the crate controller is also presented.

Baker, R. G.↗

Combining Video Memory Operations

Designs of video random-access memory (VRAM) integrated circuits operating under control by external logic circuits simplified according to concept of combining two memory operations performed separately heretofore. Eliminates need for DRAM-refresh timers and counters, reducing amount of circuitry needed to control VRAM thereby reducing time needed to design VRAM. Simplification also reduces time needed to redesign DRAM-refresh logic circuitry when adapting VRAM design to another VRAM for which timing specifications different. Concept can be applied to VRAM clocking data out to display unit continuously.

Kania, Michael J.↗

RTSJ Memory Areas and Their Affects on the Performance of a Flight-Like Attitude Control System

The two most important factors in improving performance in any software system, but especially a real-time, embedded system, are knowing which components are the low performers and knowing what can be done to improve their performance. The word performance with respect to a real-time, embedded system does not necessarily mean fast execution, which is the common definition when discussing non real-time systems. It also includes meeting all of the specified execution dead-lines and executing at the correct time without sacrificing non real-time performance. Using a Java prototype of an existing control system used on Deep Space 1[1], the effects from adding memory areas are measured and evaluated with respect to improving performance.

Real-time Specification for Java2 (RTSJ)↗

Weaves as an Interconnection Fabric for ASIM's and Nanosatellites

Many of the micromachines under consideration require computer support, indeed, one of the appeals of this technology is the ability to intermix mechanical, optical, analog, and digital devices on the same substrate. The amount of computer power is rarely an issue, the sticking point is the complexity of the software required to make effective use of these devices. Micromachines are the nano-technologist's equivalent of 'golden screws'. In other words, they will be piece parts in larger assemblages. For example, a nano-satellite may be composed of stacked silicon wafers where each wafer contains hundreds to thousands of micromachines, digital controllers, general purpose computers, memories, and high-speed bus interconnects. Comparatively few of these devices will be custom designed, most will be stock parts selected from libraries and catalogs. The novelty will lie in the interconnections. For example, a digital accelerometer may be a component part in an adaptive suspension, a monitoring element embedded in the wrapper of a package, or a portion of the smart skin of a launch vehicle. In each case, this device must inter-operate with other devices and probes for the purposes of command, control, and communication. We propose a software technology called 'weaves' that will permit large collections of micromachines and their attendant computers to freely intercommunicate while preserving modularity, transparency, and flexibility. Weaves are composed of networks of communicating software components. The network, and the components comprising it, may be changed even while the software, and the devices it controls, are executing. This unusual degree of software plasticity permits micromachines to dynamically adapt the software to changing conditions and allows system engineers to rapidly and inexpensively develop special purpose software by assembling stock software components in custom configurations.

Gorlick, Michael M.↗

Waypoint Following Dynamics of a Quaternion Error Feedback Attitude Control System

Closed-loop attitude steering can be used to implement alternative attitude maneuvers by using a conventional attitude control system to track a non-standard attitude profile sampled as a series of sequential commands. The idea has been employed in practice to perform zero-propellant maneuvers on the International Space Station and minimum time maneuvers on NASA’s TRACE space telescope. A challenge for operational implementation of the idea is the finite capacity of a space vehicle’s command storage buffer. One approach to mitigate the problem is to downsample-and-hold the attitude commands so that the attitude control system to follows a set of waypoints. This paper explores the waypoint following dynamics of a quaternion error feedback control law for downsample-and-hold. It is shown that downsample-and-hold induces a ripple between downsamples that causes the satellite angular rate to significantly overshoot the desired limit. Analysis in the z-domain is carried out in order to understand the phenomenon. An interpolating Chebyshev-type filter is proposed that allows attitude commands to be encoded in terms of a small set of filter coefficients. Using the interpolating filter, commands can be issued at the ACS rate but with significantly reduced memory requirements. The attitude control system of NASA’s Lunar Reconnaissance Orbiter is used as an example to illustrate the behavior of a practical attitude control system.

Mark Karpenko↗

Shared memory for a fault-tolerant computer

A system is described for sharing a memory in a fault-tolerant computer. The memory is under the direct control and monitoring of error detecting and error diagnostic units in the fault-tolerant computer. This computer verifies that data to and from the memory is legally encoded and verifies that words read from the memory at a desired address are, in fact, actually delivered from that desired address. The means are provided for a second processor, which is independent of the direct control and monitoring of the error checking and diagnostic units of the fault-tolerant computer, and to share the memory of the fault-tolerant computer. Circuitry is included to verify that: (1) the processor has properly accessed a desired memory location in the memory; (2) a data word read-out from the memory is properly coded; and (3) no inactive memory was erroneously outputting data onto the shared memory bus.

Gilley, G. C.↗

Microprogrammed digital filters for strapdown guidance application.

Discussion of an approach for implementing digital filters using microprogrammed control logic with read only memory (ROM) for strapdown guidance applications, and description of a second-order multiplexed system using multiprogrammed control instruction. The microprogramming technique for control using ROM is shown to enhance higher order digital filter realization. The high speed of digital circuits reduces propagation time and facilitates multiplexing. Programmed ROM's can be altered easily for different algorithms.

Kapadia, K.↗

DARPA/AFRL/NASA Smart Wing Second Wind Tunnel Test Results

To quantify the benefits of smart materials and structures adaptive wing technology, Northrop Grumman Corp. (NGC) built and tested two 16% scale wind tunnel models (a conventional and a "smart" model) of a fighter/attack aircraft under the DARPA/AFRL/NASA Smart Materials and Structures Development - Smart Wing Phase 1. Performance gains quantified included increased pitching moment (C(sub M)), increased rolling moment (C(subl)) and improved pressure distribution. The benefits were obtained for hingeless, contoured trailing edge control surfaces with embedded shape memory alloy (SMA) wires and spanwise wing twist effected by SMA torque tube mechanisms, compared to conventional hinged control surfaces. This paper presents an overview of the results from the second wind tunnel test performed at the NASA Langley Research Center s (LaRC) 16ft Transonic Dynamic Tunnel (TDT) in June 1998. Successful results obtained were: 1) 5 degrees of spanwise twist and 8-12% increase in rolling moment utilizing a single SMA torque tube, 2) 12 degrees of deflection, and 10% increase in rolling moment due to hingeless, contoured aileron, and 3) demonstration of optical techniques for measuring spanwise twist and deflected shape.

Scherer, L. B.↗

Active control of buckling of flexible beams

Mathematical models are presented that simulate the dynamic characteristics of shape memory alloy actuators made of nickel-titanium alloy (Nitinol) controlling the buckling of compressive structural members. A closed-loop computer-controlled system has been designed, based on the proposed mathematical models, and has been implemented to control the buckling of simple beams. The performance of the computer-controlled system is evaluated experimentally and compared with the theoretical predictions to validate the developed models. The results emphasized the importance of buckling control and suggest the potential of shape memory alloy actuators as attractive means for controlling structural deformation in a simple and reliable way.

Baz, A.↗

Customizable Digital Receivers for Radar

Compact, highly customizable digital receivers are being developed for the system described in 'Radar Interferometer for Topographic Mapping of Glaciers and Ice Sheets' (NPO-43962), NASA Tech Briefs, Vol. 31, No. 7 (August 2007), page 72. The receivers are required to operate in unison, sampling radar returns received by the antenna elements in a digital beam-forming (DBF) mode. The design of these receivers could also be adapted to commercial radar systems. At the time of reporting the information for this article, there were no commercially available digital receivers capable of satisfying all of the operational requirements and compact enough to be mounted directly on the antenna elements. A provided figure depicts the overall system of which the digital receivers are parts. Each digital receiver includes an analog-to-digital converter (ADC), a demultiplexer (DMUX), and a field-programmable gate array (FPGA). The ADC effects 10-bit band-pass sampling of input signals having frequencies up to 3.5 GHz. The input samples are demultiplexed at a user-selectable rate of 1:2 or 1:4, then buffered in part of the FPGA that functions as a first-in/first-out (FIFO) memory. Another part of the FPGA serves as a controller for the ADC, DMUX, and FIFO memory and as an interface between (1) the rest of the receiver and (2) a front-panel data port (FPDP) bus, which is an industry-standard parallel data bus that has a high data-rate capability and multichannel configuration suitable for DBF. Still other parts of the FPGA in each receiver perform signal-processing functions. The digital receivers can be configured to operate in a stand-alone mode, or in a multichannel mode as needed for DBF. The customizability of the receiver makes it applicable to a broad range of system architectures. The capability for operation of receivers in either a stand-alone or a DBF mode enables the use of the receivers in an unprecedentedly wide variety of radar systems.

Moller, Delwyn↗