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At least 145 records · Page 8

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NASA NTRS1993

Design of CMOS logic gates for TID radiation

The rise time, fall time and propagation delay of the logic gates were derived. The effects of total ionizing dose (TID) radiation on the fall and rise times of CMOS logic gates were obtained using C program calculations and PSPICE simulations. The variations of mobility and threshold voltage on MOSFET transistors when subjected to TID radiation were used to determine the dependence of switching times on TID. The results of this work indicate that by increasing the size of P-channel transistor with respect to the N-channel transistors of the CMOS gates, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in TID radiation.

Attia, John Okyere↗

NASA NTRS1993

Delay analysis of combinations of pass transistors and classical logic gates

Combinations of pass transistors and logic gates driving nonlinear capacitive loads are analyzed for the presence of characteristics that will permit easier and more accurate digital logic simulation. Accurate time delay models are developed by studying the nature of the response of simplified circuit models to variations of input waveform rise and fall times and output loading. The nonlinear effects of the CMOS logic devices are minimized to permit easier interpretation of the influence of nonlinear capacitive loads. The performance of a CMOS inverter with a complex nonlinear load consisting of a pass transistor that separates a range of capacitances is compared to the same inverter circuit with a linear capacitive load to develop an understanding of the unique requirements of modeling a nonlinear system. Several methods of modeling the delay of CMOS circuits are reviewed, and a multi-parameter linear model is described. General guidelines for designing CMOS circuits with complex load circuits are developed, emphasizing that the circuit output rise delays and fall delays must be separately analyzed.

Gibson, Jonathan S.↗

NASA NTRS1992

Defect-sensitivity analysis of an SEU immune CMOS logic family

Fault testing of resistive manufacturing defects is done on a recently developed single event upset immune logic family. Resistive ranges and delay times are compared with those of traditional CMOS logic. Reaction of the logic to these defects is observed for a NOR gate, and an evaluation of its ability to cope with them is determined.

Ingermann, Erik H.↗

NASA NTRS1994

Rocket engine system reliability analyses using probabilistic and fuzzy logic techniques

The reliability of rocket engine systems was analyzed by using probabilistic and fuzzy logic techniques. Fault trees were developed for integrated modular engine (IME) and discrete engine systems, and then were used with the two techniques to quantify reliability. The IRRAS (Integrated Reliability and Risk Analysis System) computer code, developed for the U.S. Nuclear Regulatory Commission, was used for the probabilistic analyses, and FUZZYFTA (Fuzzy Fault Tree Analysis), a code developed at NASA Lewis Research Center, was used for the fuzzy logic analyses. Although both techniques provided estimates of the reliability of the IME and discrete systems, probabilistic techniques emphasized uncertainty resulting from randomness in the system whereas fuzzy logic techniques emphasized uncertainty resulting from vagueness in the system. Because uncertainty can have both random and vague components, both techniques were found to be useful tools in the analysis of rocket engine system reliability.

Hardy, Terry L.↗

NASA NTRS1994

Fuzzy logic application for modeling man-in-the-loop space shuttle proximity operations

A software pilot model for Space Shuttle proximity operations is developed, utilizing fuzzy logic. The model is designed to emulate a human pilot during the terminal phase of a Space Shuttle approach to the Space Station. The model uses the same sensory information available to a human pilot and is based upon existing piloting rules and techniques determined from analysis of human pilot performance. Such a model is needed to generate numerous rendezvous simulations to various Space Station assembly stages for analysis of current NASA procedures and plume impingement loads on the Space Station. The advantages of a fuzzy logic pilot model are demonstrated by comparing its performance with NASA's man-in-the-loop simulations and with a similar model based upon traditional Boolean logic. The fuzzy model is shown to respond well from a number of initial conditions, with results typical of an average human. In addition, the ability to model different individual piloting techniques and new piloting rules is demonstrated.

Brown, Robert B.↗

NASA NTRS1996

Fuzzy Logic Decoupled Longitudinal Control for General Aviation Airplanes

It has been hypothesized that a human pilot uses the same set of generic skills to control a wide variety of aircraft. If this is true, then it should be possible to construct an electronic controller which embodies this generic skill set such that it can successfully control difference airplanes without being matched to a specific airplane. In an attempt to create such a system, a fuzzy logic controller was devised to control throttle position and another to control elevator position. These two controllers were used to control flight path angle and airspeed for both a piston powered single engine airplane simulation and a business jet simulation. Overspeed protection and stall protection were incorporated in the form of expert systems supervisors. It was found that by using the artificial intelligence techniques of fuzzy logic and expert systems, a generic longitudinal controller could be successfully used on two general aviation aircraft types that have very difference characteristics. These controllers worked for both airplanes over their entire flight envelopes including configuration changes. The controllers for both airplanes were identical except for airplane specific limits (maximum allowable airspeed, throttle lever travel, etc.). The controllers also handled configuration changes without mode switching or knowledge of the current configuration. This research validated the fact that the same fuzzy logic based controller can control two very different general aviation airplanes. It also developed the basic controller architecture and specific control parameters required for such a general controller.

Duerksen, Noel↗

NASA NTRS1997

Fuzzy Logic Decoupled Lateral Control for General Aviation Airplanes

It has been hypothesized that a human pilot uses the same set of generic skills to control a wide variety of aircraft. If this is true, then it should be possible to construct an electronic controller which embodies this generic skill set such that it can successfully control different airplanes without being matched to a specific airplane. In an attempt to create such a system, a fuzzy logic controller was devised to control aileron or roll spoiler position. This controller was used to control bank angle for both a piston powered single engine aileron equipped airplane simulation and a business jet simulation which used spoilers for primary roll control. Overspeed, stall and overbank protection were incorporated in the form of expert systems supervisors and weighted fuzzy rules. It was found that by using the artificial intelligence techniques of fuzzy logic and expert systems, a generic lateral controller could be successfully used on two general aviation aircraft types that have very different characteristics. These controllers worked for both airplanes over their entire flight envelopes. The controllers for both airplanes were identical except for airplane specific limits (maximum allowable airspeed, throttle ]ever travel, etc.). This research validated the fact that the same fuzzy logic based controller can control two very different general aviation airplanes. It also developed the basic controller architecture and specific control parameters required for such a general controller.

Duerksen, Noel↗

NASA NTRS2000

Inference System Integration Via Logic Morphisms

This is a final report on the accomplishments during the period of the NASA grant. The work on inference servers accomplished the integration of the SLANG logic (Specware's default specification logic) with a number of inference servers in order to make their complementary strengths available. These inverence servers are (1) SNARK. (2) Gandalf, Setheo, and Spass, (3) the Prototype Verification System (PVS) from SRI. (4) HOL98. We designed and implemented MetaSlang, an ML-like language, which we are using to specify and implement all our logic morphisms.

Bjorner, Nikolaj S.↗

NASA NTRS1997

Logic Design Pathology and Space Flight Electronics

Logic design errors have been observed in space flight missions and the final stages of ground test. The technologies used by designers and their design/analysis methodologies will be analyzed. This will give insight to the root causes of the failures. These technologies include discrete integrated circuit based systems, systems based on field and mask programmable logic, and the use computer aided engineering (CAE) systems. State-of-the-art (SOTA) design tools and methodologies will be analyzed with respect to high-reliability spacecraft design and potential pitfalls are discussed. Case studies of faults from large expensive programs to "smaller, faster, cheaper" missions will be used to explore the fundamental reasons for logic design problems.

Katz, Richard↗

NASA NTRS2002

Software Safety Assurance of Programmable Logic

Programmable Logic (PLC, FPGA, ASIC) devices are hybrids - hardware devices that are designed and programmed like software. As such, they fall in an assurance gray area. Programmable Logic is usually tested and verified as hardware, and the software aspects are ignored, potentially leading to safety or mission success concerns. The objective of this proposal is to first determine where and how Programmable Logic (PL) is used within NASA and document the current methods of assurance. Once that is known, raise awareness of the PL software aspects within the NASA engineering community and provide guidance for the use and assurance of PL form a software perspective.

Berens, Kalynnda↗

NASA NTRS2005

Fuzzy Logic Particle Tracking

A new all-electronic Particle Image Velocimetry technique that can efficiently map high speed gas flows has been developed in-house at the NASA Lewis Research Center. Particle Image Velocimetry is an optical technique for measuring the instantaneous two component velocity field across a planar region of a seeded flow field. A pulsed laser light sheet is used to illuminate the seed particles entrained in the flow field at two instances in time. One or more charged coupled device (CCD) cameras can be used to record the instantaneous positions of particles. Using the time between light sheet pulses and determining either the individual particle displacements or the average displacement of particles over a small subregion of the recorded image enables the calculation of the fluid velocity. Fuzzy logic minimizes the required operator intervention in identifying particles and computing velocity. Using two cameras that have the same view of the illumination plane yields two single exposure image frames. Two competing techniques that yield unambiguous velocity vector direction information have been widely used for reducing the single-exposure, multiple image frame data: (1) cross-correlation and (2) particle tracking. Correlation techniques yield averaged velocity estimates over subregions of the flow, whereas particle tracking techniques give individual particle velocity estimates. For the correlation technique, the correlation peak corresponding to the average displacement of particles across the subregion must be identified. Noise on the images and particle dropout result in misidentification of the true correlation peak. The subsequent velocity vector maps contain spurious vectors where the displacement peaks have been improperly identified. Typically these spurious vectors are replaced by a weighted average of the neighboring vectors, thereby decreasing the independence of the measurements. In this work, fuzzy logic techniques are used to determine the true correlation displacement peak even when it is not the maximum peak, hence maximizing the information recovery from the correlation operation, maintaining the number of independent measurements, and minimizing the number of spurious velocity vectors. Correlation peaks are correctly identified in both high and low seed density cases. The correlation velocity vector map can then be used as a guide for the particle-tracking operation. Again fuzzy logic techniques are used, this time to identify the correct particle image pairings between exposures to determine particle displacements, and thus the velocity. Combining these two techniques makes use of the higher spatial resolution available from the particle tracking. Particle tracking alone may not be possible in the high seed density images typically required for achieving good results from the correlation technique. This two-staged velocimetric technique can measure particle velocities with high spatial resolution over a broad range of seeding densities.

Source record↗

NASA NTRS2009

Diagnosable structured logic array

A diagnosable structured logic array and associated process is provided. A base cell structure is provided comprising a logic unit comprising a plurality of input nodes, a plurality of selection nodes, and an output node, a plurality of switches coupled to the selection nodes, where the switches comprises a plurality of input lines, a selection line and an output line, a memory cell coupled to the output node, and a test address bus and a program control bus coupled to the plurality of input lines and the selection line of the plurality of switches. A state on each of the plurality of input nodes is verifiably loaded and read from the memory cell. A trusted memory block is provided. The associated process is provided for testing and verifying a plurality of truth table inputs of the logic unit.

Whitaker, Sterling↗

NASA NTRS2011

Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters

A circuit topography is used to create usable, digital logic gates using N (negatively doped) channel junction field effect transistors (JFETs), load resistors, level shifting resistors, and supply rails whose values are based on the DC parametric distributions of these JFETs. This method has direct application to the current state-of-the-art in high-temperature (300 to 500 C and higher) silicon carbide (SiC) device production, and defines an adaptation to the logic gate described in U.S. Patent 7,688,117 in that, by removing the level shifter from the output of the gate structure described in the patent (and applying it to the input of the same gate), a source-coupled gate topography is created. This structure allows for the construction AND/OR (sum of products) arrays that use far fewer transistors and resistors than the same array as constructed from the gates described in the aforementioned patent. This plays a central role when large multiplexer constructs are necessary; for example, as in the construction of memory. This innovation moves the resistive level shifter from the output of the basic gate structure to the front as if the input is now configured as what would be the output of the preceding gate, wherein the output is the two level shifting resistors. The output of this innovation can now be realized as the lone follower transistor with its source node as the gate output. Additionally, one may leave intact the resistive level shifter on the new gate topography. A source-coupled to direct-coupled logic translator will be the result.

Krasowski, Michael J.↗

NASA NTRS2003

Block QCA Fault-Tolerant Logic Gates

Suitably patterned arrays (blocks) of quantum-dot cellular automata (QCA) have been proposed as fault-tolerant universal logic gates. These block QCA gates could be used to realize the potential of QCA for further miniaturization, reduction of power consumption, increase in switching speed, and increased degree of integration of very-large-scale integrated (VLSI) electronic circuits. The limitations of conventional VLSI circuitry, the basic principle of operation of QCA, and the potential advantages of QCA-based VLSI circuitry were described in several NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35; and Hybrid VLSI/QCA Architecture for Computing FFTs (NPO-20923), which follows this article. To recapitulate the principle of operation (greatly oversimplified because of the limitation on space available for this article): A quantum-dot cellular automata contains four quantum dots positioned at or between the corners of a square cell. The cell contains two extra mobile electrons that can tunnel (in the quantummechanical sense) between neighboring dots within the cell. The Coulomb repulsion between the two electrons tends to make them occupy antipodal dots in the cell. For an isolated cell, there are two energetically equivalent arrangements (denoted polarization states) of the extra electrons. The cell polarization is used to encode binary information. Because the polarization of a nonisolated cell depends on Coulomb-repulsion interactions with neighboring cells, universal logic gates and binary wires could be constructed, in principle, by arraying QCA of suitable design in suitable patterns. Heretofore, researchers have recognized two major obstacles to realization of QCA-based logic gates: One is the need for (and the difficulty of attaining) operation of QCA circuitry at room temperature or, for that matter, at any temperature above a few Kelvins. It has been theorized that room-temperature operation could be made possible by constructing QCA as molecular-scale devices. However, in approaching the lower limit of miniaturization at the molecular level, it becomes increasingly imperative to overcome the second major obstacle, which is the need for (and the difficulty of attaining) high precision in the alignments of adjacent QCA in order to ensure the correct interactions among the quantum dots.

Firjany, Amir↗

NASA NTRS2016

Coordination Logic for Repulsive Resolution Maneuvers

This paper presents an algorithm for determining the direction an aircraft should maneuver in the event of a potential conflict with another aircraft. The algorithm is implicitly coordinated, meaning that with perfectly reliable computations and information, it will in- dependently provide directional information that is guaranteed to be coordinated without any additional information exchange or direct communication. The logic is inspired by the logic of TCAS II, the airborne system designed to reduce the risk of mid-air collisions between aircraft. TCAS II provides pilots with only vertical resolution advice, while the proposed algorithm, using a similar logic, provides implicitly coordinated vertical and horizontal directional advice.

Narkawicz, Anthony J.↗

NASA NTRS2017

Current Source Logic Gate

A current source logic gate with depletion mode field effect transistor ("FET") transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.

Krasowski, Michael J.↗

NASA NTRS2018

Current Source Logic Gate

Krasowski, Michael J.↗

NASA NTRS2018

Runtime Veriﬁcation: From Propositional to First-Order Temporal Logic

Runtime Veriﬁcation is a branch of formal methods concerned with analysis of execution traces for the purpose of determining the state or general quality of the executing system. The ﬁeld covers numerous approaches, one of which is speciﬁcation-based runtime veriﬁcation, where execution traces are checked against formal speciﬁcations. The paper presents syntax, semantics, and monitoring algorithms for respectively propositional and ﬁrst-order temporal logics. In propositional logics the observed events in the execution trace are represented using atomic propositions, while ﬁrst-order logic allows universal and existential quantiﬁcation over data occurring as arguments in events. Monitoring of the ﬁrst-order case is drastically more challenging than the propositional case, and we present a solution for this problem based on BDDs. We furthermore discuss monitorability of temporal properties by dividing them into different classes representing different degrees of monitorability.

Peled, Doron↗