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At least 145 records · Page 8

Seamless Hybrid-integrated Interconnect NEtwork (SHINE)

Large-scale date centers are becoming increasingly limited by the capacity of interconnects due to the rapid increasing power consumption and bandwidth demands driven by the rigorous down scaling of CMOS critical dimensions in according with the Moore’s Law. As a result of the continuing bandwidth scaling, optical interconnects based on parallel optics, where data are simultaneously transmitted along more than one lane, have becoming a preferred interconnected solution over copper cables. To building an efficient optical interconnect system, optical coupling between different elements, such as optical fibers, photonics chips, is a critical step, which is challenging due to the mode mismatch of varies optical ports. In this project, we proposed and demonstrated an optical interfacing scheme, which provided a light coupling approach with low energy loss, broadband operation, high alignment tolerance and compatible with scalable fabrication and testing. Here, the mode transformation is achieved by a total internal reflection from a chip integrated microscale freefrom surface. Due to the enormous light wavefront manipulating ability associated with the gigantic design space, the freeform couplers platform is universally applicable to a wide range of optical coupling scenarios, such as the interfacing between a waveguide to a fiber, another waveguide, surface normal device, or free space.

42 ENGINEERING↗

Distributed Energy Resource Interconnection Roadmap

Adopting strategic reforms to DER interconnection can help reduce interconnection delays, fairly allocate costs, improve transparency and equity, and support efficient and strategic investment in distribution and sub-transmission grids that can accommodate a rapidly evolving energy landscape. The Interconnection Innovation e-Xchange envisions this roadmap and its transmission system companion volume as collaborative resources to facilitate continued stakeholder discussions, problem-solving, and innovation as the U.S. works together to enable simpler, faster, and fairer interconnection of clean energy resources all while enhancing the reliability, resiliency, and security of our electric grid.

24 POWER TRANSMISSION AND DISTRIBUTION↗

IM3 Projected U.S. Western Interconnection Grid Stress Dataset

This dataset provides projected grid stress and reliability results (including all model inputs and outputs from GO WEST and TEP) for Integrated Multisector, Multiscale Modeling (IM3) Phase 2 simulations across eight different scenarios for the U.S. Western Interconnection through 2055. The scenarios include combinations of two Shared Socioeconomic Pathways (SSP3 and SSP5) with four high-resolution climate projections specific to the United States from a set of Thermodynamic Global Warming (TGW) simulations. These climate projections include "hotter" and "cooler" variants for two Representative Concentration Pathways (RCP4.5 and RCP8.5). The resulting eight simulations are: rcp45cooler_ssp3 rcp45cooler_ssp5 rcp45hotter_ssp3 rcp45hotter_ssp5 rcp85cooler_ssp3 rcp85cooler_ssp5 rcp85hotter_ssp3 rcp85hotter_ssp5 GO WEST is an open-source power grid modeling framework for the U.S. Western Interconnection, which allows users to tailor the model depending on their research study and science questions. It covers 28 balancing authorities (BAs) and 12 states in U.S. Western Interconnection. GO WEST allows users to select different number of nodes and come up with a simplified network by utilizing 10,000 nodal topology of the U.S. Western Interconnection (ACTIVSg10k). Users can select different number of nodes, mathematical formulations (linear programming vs. mixed-integer linear programming), transmission line limit scaling factors, and hurdle rate scaling factors. GO WEST offers a unit commitment and economic dispatch (UC/ED) module to simulate grid operations on an hourly scale. In this sense, users can calibrate and validate their model versions by comparing model outputs to historical datasets. TEP is an open-source transmission capacity expansion model, built on the GO WEST framework. It utilizes linear programming to optimize transmission capacity addition investment on existing lines within the GO WEST framework. The TEP model only increases the thermal capacity of existing transmission lines and does not add new lines to the system, which leaves the topology preserved. In order to use TEP model, users need to create scenarios with the GO WEST framework. Please refer to README file for a detailed description of the dataset including individual files and references.

Capacity Expansion Model↗

Transequatorial loops interconnecting McMath regions 12472 and 12474

The paper reviews the life history of one transequatorial loop in a system observed in soft X-rays for at least 1.5 days and which interconnected a newly born active region with an old region. The birth of the selected loop is discussed along with properties of the interconnected active regions, sharpening and brightening of the loop, decay of the loop system, and physical relations between the interconnected regions. It is concluded that: (1) the loop was most probably born via reconnection of magnetic-field lines extending from the two active regions toward the equator, which occurred later than 33 hr after the younger region was born; (2) the fully developed interconnection was composed of several loops, all of which appeared to be rooted in a spotless magnetic hill of preceding northern polarity but were spread over two separate spotty regions of southern polarity in the magnetically complex new region; (3) the loop electron temperature increased from 2.1 million to 3.1 million K in one to three hours when the loop system brightened; and (4) the loops became twisted during the brightening, possibly due to their rise in the corona while remaining rooted in moving magnetic features in the younger region.

Svestka, Z.↗

Transient brightenings of interconnecting loops. II - Dynamics of the brightened loops

Three different kinds of dynamic events related to interconnecting loops observed in soft X-rays aboard Skylab are discussed: (1) a newly born transequatorial loop that was either emerging from subphotospheric layers or gradually filled in with hot plasma; (2) large-scale twists of interconnecting loops which never relax, and often only form after the loop brightenings, and (3) three events where the loop that later interconnected two active regions had been visible long before one of the interconnecting regions was born. Several impacts this observation might have upon the understanding of the process of flux emergence are suggested.

Svestka, Z.↗

Design solutions for the solar cell interconnect fatigue fracture problem

Mechanical fatigue of solar cell interconnects is a major failure mechanism in photovoltaic arrays. A comprehensive approach to the reliability design of interconnects, together with extensive design data for the fatigue properties of copper interconnects, has been published. This paper extends the previous work, developing failure prediction (fatigue) data for additional interconnect material choices, including aluminum and a variety of copper-Invar and copper-steel claddings. An improved global fatigue function is used to model the probability-of-failure statistics of each material as a function of level and number of cycles of applied strain. Life-cycle economic analyses are used to evaluate the relative merits of each material choce. The copper-Invar clad composites demonstrate superior performance over pure copper. Aluminum results are disappointing.

Mon, G. R.↗

Implementation of optical interconnections for VLSI

This paper reports on the progress in implementing optical interconnections for VLSI. Four areas are covered: (1) the holographic optical element (HOE), (2) the laser sources, (3) the detectors and associated circuits forming an optically addressed gate, and (4) interconnection experiments in which five gates are actuated from one source. A laser scanner system with a resolution of 12 x 20 microns has been utilized to generate the HOEs. Diffraction efficiency of the HOE and diffracted spot size have been measured. Stock lasers have been modified with a high-frequency package for interconnect experiments, and buried heterostructure fabrication techniques have been pursued. Measurements have been made on the fabricated photodetectors to determine dark current, responsivity, and response time. The optical gates and the overall chip have been driven successfully with an input light beam, as well as with the optical signal interconnected through the one to five holograms.

Wu, Wennie H.↗

Optical interconnections and networks; Proceedings of the Meeting, The Hague, Netherlands, Mar. 14, 15, 1990

The conference presents papers on interconnections, clock distribution, neural networks, and components and materials. Particular attention is given to a comparison of optical and electrical data interconnections at the board and backplane levels, a wafer-level optical interconnection network layout, an analysis and simulation of photonic switch networks, and the integration of picosecond GaAs photoconductive devices with silicon circuits for optical clocking and interconnects. Consideration is also given to the optical implementation of neural networks, invariance in an optoelectronic implementation of neural networks, and the recording of reversible patterns in polymer lightguides.

Bartelt, Hartmut↗

Process Developed for Generating Ceramic Interconnects With Low Sintering Temperatures for Solid Oxide Fuel Cells

Solid oxide fuel cells (SOFCs) have been considered as premium future power generation devices because they have demonstrated high energy-conversion efficiency, high power density, and extremely low pollution, and have the flexibility of using hydrocarbon fuel. The Solid-State Energy Conversion Alliance (SECA) initiative, supported by the U.S. Department of Energy and private industries, is leading the development and commercialization of SOFCs for low-cost stationary and automotive markets. The targeted power density for the initiative is rather low, so that the SECA SOFC can be operated at a relatively low temperature (approx. 700 C) and inexpensive metallic interconnects can be utilized in the SOFC stack. As only NASA can, the agency is investigating SOFCs for aerospace applications. Considerable high power density is required for the applications. As a result, the NASA SOFC will be operated at a high temperature (approx. 900 C) and ceramic interconnects will be employed. Lanthanum chromite-based materials have emerged as a leading candidate for the ceramic interconnects. The interconnects are expected to co-sinter with zirconia electrolyte to mitigate the interface electric resistance and to simplify the processing procedure. Lanthanum chromites made by the traditional method are sintered at 1500 C or above. They react with zirconia electrolytes (which typically sinter between 1300 and 1400 C) at the sintering temperature of lanthanum chromites. It has been envisioned that lanthanum chromites with lower sintering temperatures can be co-fired with zirconia electrolyte. Nonstoichiometric lanthanum chromites can be sintered at lower temperatures, but they are unstable and react with zirconia electrolyte during co-sintering. NASA Glenn Research Center s Ceramics Branch investigated a glycine nitrate process to generate fine powder of the lanthanum-chromite-based materials. By simultaneously doping calcium on the lanthanum site, and cobalt and aluminum on the chromium site, we could sinter the materials below 1400 C. The doping concentrations were adjusted so that the thermal expansion coefficient matched that of the zirconia electrolyte. Also, the investigation was focused on stoichiometric compositions so that the materials would have better stability. Co-sintering and chemical compatibility with zirconia electrolyte were examined by X-ray diffraction, scanning electron microscopy, and energy dispersive spectroscopy (line scanning and dot map). The results showed that the materials bond well, but do not react, with zirconia electrolyte. The electric conductivity of the materials measured at 900 C in air was about 20 S/cm.

Zhong, Zhi-Min↗

Electrode and interconnect for miniature fuel cells using direct methanol feed

An improved system for interconnects in a fuel cell. In one embodiment, the membranes are located in parallel with one another, and current flow between them is facilitated by interconnects. In another embodiment, all of the current flow is through the interconnects which are located on the membranes. The interconnects are located between two electrodes.

Narayanan, Sekharipuram R.↗

Free-Space Optical Interconnect Employing VCSEL Diodes

Sensor signal processing is widely used on aircraft and spacecraft. The scheme employs multiple input/output nodes for data acquisition and CPU (central processing unit) nodes for data processing. To connect 110 nodes and CPU nodes, scalable interconnections such as backplanes are desired because the number of nodes depends on requirements of each mission. An optical backplane consisting of vertical-cavity surface-emitting lasers (VCSELs), VCSEL drivers, photodetectors, and transimpedance amplifiers is the preferred approach since it can handle several hundred megabits per second data throughput.The next generation of satellite-borne systems will require transceivers and processors that can handle several Gb/s of data. Optical interconnects have been praised for both their speed and functionality with hopes that light can relieve the electrical bottleneck predicted for the near future. Optoelectronic interconnects provide a factor of ten improvement over electrical interconnects.

Simons, Rainee N.↗

Electronic interconnects and devices with topological surface states and methods for fabricating same

An interconnect is disclosed with enhanced immunity of electrical conductivity to defects. The interconnect includes a material with charge carriers having topological surface states. Also disclosed is a method for fabricating such interconnects. Also disclosed is an integrated circuit including such interconnects. Also disclosed is a gated electronic device including a material with charge carriers having topological surface states.

36 MATERIALS SCIENCE↗

Toward Interpreting Failure in Sintered-Silver Interconnection Systems

The mechanical strength and subsequent reliability of a sintered-silver interconnection system is a function of numerous independent parameters. That system is still undergoing process development. Most of those parameters (e.g., choice of plating) are arguably and unfortunately taken for granted and are independent of the silver s cohesive strength. To explore such effects, shear strength testing and failure analyses were completed on a simple, mock sintered-silver interconnection system consisting of bonding two DBC ceramic substrates. Silver and gold platings were part of the test matrix, as was pre-drying strategies, and the consideration of stencil-printing vs. screen-printing. Shear strength of sintered-silver interconnect systems was found to be was insensitive to the choice of plating, drying practice, and printing method provided careful and consistent processing of the sintered-silver are practiced. But if the service stress in sintered silver interconnect systems is anticipated to exceed ~ 60 MPa, then the system will likely fail.

Wereszczak, Andrew A↗

Electronic interconnects and devices with topological surface states and methods for fabricating same

An interconnect is disclosed with enhanced immunity of electrical conductivity to defects. The interconnect includes a material with charge carriers having topological surface states. Also disclosed is a method for fabricating such interconnects. Also disclosed is an integrated circuit including such interconnects. Also disclosed is a gated electronic device including a material with charge carriers having topological surface states.

36 MATERIALS SCIENCE↗

Photovoltaic sub-cell interconnects

Photovoltaic sub-cell interconnect systems and methods are provided. In one embodiment, a photovoltaic device comprises a thin film stack of layers deposited upon a substrate, wherein the thin film stack layers are subdivided into a plurality of sub-cells interconnected in series by a plurality of electrical interconnection structures; and wherein the plurality of electrical interconnection structures each comprise no more than two scribes that penetrate into the thin film stack layers.

14 SOLAR ENERGY↗

IC layout adjustment method and tool for improving dielectric reliability at interconnects

Method for adjusting a layout used in making an integrated circuit includes one or more interconnects in the layout that are susceptible to dielectric breakdown are selected. One or more selected interconnects are adjusted to increase via to wire spacing with respect to at least one via and one wire of the one or more selected interconnects. Preferably, the selecting analyzes signal patterns of interconnects, and estimates the stress ratio based on state probability of routed signal nets in the layout. An annotated layout is provided that describes distances by which one or more via or wire segment edges are to be shifted. Adjustments can include thinning and shifting of wire segments, and rotation of vias.

42 ENGINEERING↗

On-package multiprocessor ground-referenced single-ended interconnect

A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a second processor chip, and an MCM package configured to include the first processor chip, the second processor chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first GRS interface circuit to the interconnect circuit. The second processor chip is configured to include a second GRS interface circuit. A second set of electrical traces fabricated within the MCM package and configured to coupled the second GRS interface circuit to the interconnect circuit.

Dally, William J.↗

Encoding of symbols for a computer interconnect based on frequency of symbol values

Data are serially communicated over an interconnect between an encoder and a decoder. The encoder includes a first training unit to count a frequency of symbol values in symbol blocks of a set of N number of symbol blocks in an epoch. A circular shift unit of the encoder stores a set of most-recently-used (MRU) amplitude values. An XOR unit is coupled to the first training unit and the first circular shift unit as inputs and to the interconnect as output. A transmitter is coupled to the encoder XOR unit and the interconnect and thereby contemporaneously sends symbols and trains on the symbols. In a system, a device includes a receiver and decoder that receive, from the encoder, symbols over the interconnect. The decoder includes its own training unit for decoding the transmitted symbols.

SeyedzadehDelcheh, SeyedMohammad↗