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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

The Timepix4 analog front-end design: Lessons learnt on fundamental limits to noise and time resolution in highly segmented hybrid pixel detectors

This manuscript describes the optimization of the front-end readout electronics for high granularity hybrid pixel detectors. The theoretical study aims at minimizing the noise and jitter. The model presented here is validated with both circuit post layout simulations and measurements on the Timepix4 Application Specific Integrated Circuit (ASIC). The analog front-end circuit and the procedure to optimize the dimensions of the main transistors are described with detail. The Timepix4 is the most recent ASIC designed in the framework of the Medipix4 Collaboration. It was manufactured in 65nm CMOS process, and consists of a four side buttable matrix of 448 × 512 pixels with 55µm pitch. The analog front-end has a gain of ~36mV/ke - when configured in High Gain Mode, and ~20mV/ke - when configured in Low Gain Mode. The Equivalent Noise Charge (ENC) is ~68e - rms and ~80e - rms in High Gain Mode and in Low Gain Mode respectively. In event driven mode the incoming hits can be time stamped within a ~ 200ps time bin and the chip can deal with a maximum flux of ~ 3.6MHzmm –2 s –1 . In photon counting mode, the chip can deal with up to ~ 5GHzmm –2 s –1 . The routine designed to optimize the Timepix4 front-end is then used to analyze the performance limits in terms of jitter and noise for Charge Sensitive Amplifiers in pixel detectors.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

GaN HEMT Fabrication for Radiation-Hardened Sensing and Communications Electronics

Gallium nitride (GaN), a wide bandgap semiconductor, has vast potential to address two environment conditions associated with the application of electronics to nuclear power: elevated temperatures, and high levels of radiation. A process was developed at The Ohio State University (OSU) to enable fabrication of complex digital and analog electronics circuits for application to nuclear power environments such as locations near or in the reactor core or in spent nuclear fuel casks. Radio frequency (RF)-grade GaN high electron mobility transistor (HEMT) devices were fabricated as part of this process. These were fabricated as depletion mode and enhancement mode devices. They have been electrically characterized and have demonstrated the expected performance. Behavioral models (Verilog-A) were developed from these device measurements to enable electrical simulation of GaN HEMT devices and circuits using common electronics simulation tools based on Simulation Program with Integrated Circuit Emphasis (SPICE). A similar set of GaN HEMT devices is being developed to provide lower speed devices for logic and analog functions. These accomplishments position this technology for effective application to sensor interfacing, signal processing, and data communications in nuclear power plants, including operation in or near the reactor core.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
DOE OSTI2025

Scalable low-loss cryogenic packaging of quantum memories in CMOS-foundry processed photonic chips

Optically linked solid-state quantum memories such as color centers in diamond are a promising platform for distributed quantum information processing and networking. Photonic integrated circuits (PICs) have emerged as a crucial enabling technology for these systems, integrating quantum memories with efficient electrical and optical interfaces in a compact and scalable platform. Packaging these hybrid chips into deployable modules while maintaining low optical loss and resiliency to temperature cycling is a central challenge to their practical use. We demonstrate a packaging method for PICs using surface grating couplers and angle-polished fiber arrays that is robust to temperature cycling, offers scalable channel count, applies to a wide variety of PIC platforms and wavelengths, and offers pathways to automated high-throughput packaging. Using this method, we show optically and electrically packaged quantum memory modules integrating all required qubit controls on chip, operating at millikelvin temperatures with <3 dB losses achievable from fiber to quantum memory for the TE 0 mode at a wavelength of 737 nm.

Bernson, Robert [Tyndall National Institute, Cork ↗
DOE OSTI2025

Designs for scalable construction of hybrid quantum photonic cavities

Nanophotonic resonators are central to numerous applications, from efficient spin–photon interfaces to laser oscillators and precision sensing. A leading approach consists of photonic crystal (PhC) cavities, which have been realized in a wide range of dielectric materials. However, translating proof-of-concept devices into a functional system entails a number of additional challenges, inspiring new approaches that combine resonators with wavelength-scale confinement and high quality factors; scalable integration with integrated circuits and photonic circuits; electrical or mechanical cavity tuning; and, in many cases, a need for heterogeneous integration with functional materials such as III–V semiconductors or diamond color centers for spin–photon interfaces. Here we introduce a concept that generates a finely tunable PhC cavity at a selected wavelength between two heterogeneous optical materials whose properties satisfy the above requirements. The cavity is formed by stamping a hard-to-process material with simple waveguide geometries on top of an easy-to-process material consisting of dielectric grating mirrors and active tuning capability. We simulate our concept for the particularly challenging design problem of multiplexed quantum repeaters based on arrays of cavity-coupled diamond color centers, achieving theoretically calculated unloaded quality factors of 106, mode volumes as small as 1.2(λ/neff)3, and maintaining >60% total on-chip collection efficiency of fluorescent photons. We further introduce a method of low-power piezoelectric tuning of these hybrid diamond cavities, simulating optical resonance shifts up to ∼760 GHz and color center fluorescence tuning of 5 GHz independent of cavity tuning. These results will motivate integrated photonic cavities toward larger scale systems-compatible designs.

Greenspon, Andrew S. (ORCID:0000000296317568)↗
DOE OSTI2024

A Modular 512-Channel Neural Signal Acquisition ASIC for High-Density 4096 Channel Electrophysiology

The complexity of information processing in the brain requires the development of technologies that can provide spatial and temporal resolution by means of dense electrode arrays paired with high-channel-count signal acquisition electronics. In this work, we present an ultra-low noise modular 512-channel neural recording circuit that is scalable to up to 4096 simultaneously recording channels. The neural readout application-specific integrated circuit (ASIC) uses a dense 8.2 mm × 6.8 mm 2D layout to enable high-channel count, creating an ultra-light 350 mg flexible module. The module can be deployed on headstages for small animals like rodents and songbirds, and it can be integrated with a variety of electrode arrays. The chip was fabricated in a TSMC 0.18 µm 1.8 V CMOS technology and dissipates a total of 125 mW. Each DC-coupled channel features a gain and bandwidth programmable analog front-end along with 14 b analog-to-digital conversion at speeds up to 30 kS/s. Additionally, each front-end includes programmable electrode plating and electrode impedance measurement capability. We present both standalone and in vivo measurements results, demonstrating the readout of spikes and field potentials that are modulated by a sensory input.

47 OTHER INSTRUMENTATION↗
DOE OSTI2020

Integrated dispersion compensated mode-locked quantum dot laser

Quantum dot lasers are excellent on-chip light sources, offering high defect tolerance, low threshold, low temperature variation, and high feedback insensitivity. Yet a monolithic integration technique combining epitaxial quantum dot lasers with passive waveguides has not been demonstrated and is needed for complex photonic integrated circuits. We present here, for the first time to our knowledge, a monolithc offset quantum dot integration platform that permits formation of a laser cavity utilizing both the robust quantum dot active region and the versatility of passive GaAs waveguide structures. This platform is substrate agnostic and therefore compatible with the quantum dot lasers directly grown on Si. As an illustration of the potential of this platform, we designed and fabricated a 20 GHz mode-locked laser with a dispersion-engineered on-chip waveguide mirror. Due to the dispersion compensation effect of the waveguide mirror, the pulse width of the mode-locked laser is reduced by a factor of 2.8.

Zhang, Zeyu (ORCID:0000000271576272)↗
DOE OSTI2021

Demonstration of a MOT in a sub-millimeter membrane hole

Abstract We demonstrate the generation of a cold-atom ensemble within a sub-millimeter diameter hole in a transparent membrane, a so-called “membrane MOT”. With a sub-Doppler cooling process, the atoms trapped by the membrane MOT are cooled down to 10 $$\upmu$$ μ K. The atom number inside the unbridged/bridged membrane hole is about $$10^4$$ 10 4 to $$10^5$$ 10 5 , and the $$1/e^2$$ 1 / e 2 -diameter of the MOT cloud is about 180 $$\upmu$$ μ m for a 400 $$\upmu$$ μ m-diameter membrane hole. Such a membrane device can, in principle, efficiently load cold atoms into the evanescent-field optical trap generated by the suspended membrane waveguide for strong atom-light interaction and provide the capability of sufficient heat dissipation at the waveguide. This represents a key step toward the photonic atom trap integrated platform (ATIP).

74 ATOMIC AND MOLECULAR PHYSICS↗
DOE OSTI2020

Neuromorphic spintronics

Neuromorphic computing uses brain-inspired principles to design circuits that can perform computational tasks with superior power efficiency to conventional computers. Approaches that use traditional electronic devices to create artificial neurons and synapses are, however, currently limited by the energy and area requirements of these components. Spintronic nanodevices, which exploit both the magnetic and electrical properties of electrons, can increase the energy efficiency and decrease the area of these circuits, and magnetic tunnel junctions are of particular interest as neuromorphic computing elements because they are compatible with standard integrated circuits and can support multiple functionalities. Here, we review the development of spintronic devices for neuromorphic computing. We examine how magnetic tunnel junctions can serve as synapses and neurons, and how magnetic textures, such as domain walls and skyrmions, can function as neurons. We also explore spintronics-based implementations of neuromorphic computing tasks, such as pattern recognition in an associative memory, and discuss the challenges that exist in scaling up these systems.

42 ENGINEERING↗
DOE OSTI2024

Toward quantum networking with frequency-bin qudits

Quantum networking holds tremendous promise in transforming computation and communication. Entangled-photon sources are critical for quantum repeaters and networking, while photonic integrated circuits are vital for miniaturization and scalability. In this talk, we focus on generating and manipulating frequency-bin entangled states within integrated platforms. We encode quantum information as a coherent superposition of multiple optical frequencies; this approach is favorable due to its amenability to high-dimensional entanglement and compatibility with fiber transmission. We successfully generate and measure the density matrix of biphoton frequency combs from integrated silicon nitride microrings, fully reconstructing the state in an 8 × 8 two-qudit Hilbert space, the highest so far for frequency bins. Moreover, we employ Vernier electro-optic phase modulation methods to perform time-resolved measurements of biphoton correlation functions. Currently, we are exploring bidirectional pumping of microrings to generate indistinguishable entangled pairs in both directions, aiming to demonstrate key networking operations such as entanglement swapping and Greenberger–Horne–Zeilinger state generation in the frequency domain.

Myilswamy, Karthik V.↗
DOE OSTI2022

Rate-capability of the VMM3a front-end in the RD51 Scalable Readout System

The VMM3a is an Application Specific Integrated Circuit (ASIC), specifically developed for the readout of gaseous detectors. Originally developed within the ATLAS New Small Wheel (NSW) upgrade, it has been successfully integrated into the Scalable Readout System (SRS) of the RD51 collaboration. This allows, to use the VMM3a also in small laboratory set-ups and mid-scale experiments, which make use of Micro-Pattern Gaseous Detectors (MPGDs). As part of the integration of the VMM3a into the SRS, the readout and data transfer scheme was optimised to reach a high rate-capability of the entire readout system and profit from the VMM3a's high single-channel rate-capability of 3.6Mhits/s. The optimisation focused mainly on the handling of the data output stream of the VMM3a, but also on the development of a trigger-logic between the front-end cards and the DAQ computer. In this article, two firmware implementations of the non-ATLAS continuous readout mode are presented, as well as the implementation of the trigger-logic. Afterwards, a short overview on X-ray imaging results is presented, to illustrate the high rate-capability from an application point-of-view.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2025

Optoelectronic polymer memristors with dynamic control for power-efficient in-sensor edge computing

Abstract As the demand for edge platforms in artificial intelligence increases, including mobile devices and security applications, the surge in data influx into edge devices often triggers interference and suboptimal decision-making. There is a pressing need for solutions emphasizing low power consumption and cost-effectiveness. In-sensor computing systems employing memristors face challenges in optimizing energy efficiency and streamlining manufacturing due to the necessity for multiple physical processing components. Here, we introduce low-power organic optoelectronic memristors with synergistic optical and mV-level electrical tunable operation for a dynamic “control-on-demand” architecture. Integrating signal sensing, featuring, and processing within the same memristors enables the realization of each in-sensor analogue reservoir computing module, and minimizes circuit integration complexity. The system achieves 97.15% fingerprint recognition accuracy while maintaining a minimal reservoir size and ultra-low energy consumption. Furthermore, we leverage wafer-scale solution techniques and flexible substrates for optimal memristor fabrication. By centralizing core functionalities on the same in-sensor platform, we propose a resilient and adaptable framework for energy-efficient and economical edge computing.

Optics↗
DOE OSTI2023

Prospects and applications of on-chip lasers

Abstract Integrated silicon photonics has sparked a significant ramp-up of investment in both academia and industry as a scalable, power-efficient, and eco-friendly solution. At the heart of this platform is the light source, which in itself, has been the focus of research and development extensively. This paper sheds light and conveys our perspective on the current state-of-the-art in different aspects of application-driven on-chip silicon lasers. We tackle this from two perspectives: device-level and system-wide points of view. In the former, the different routes taken in integrating on-chip lasers are explored from different material systems to the chosen integration methodologies. Then, the discussion focus is shifted towards system-wide applications that show great prospects in incorporating photonic integrated circuits (PIC) with on-chip lasers and active devices, namely, optical communications and interconnects, optical phased array-based LiDAR, sensors for chemical and biological analysis, integrated quantum technologies, and finally, optical computing. By leveraging the myriad inherent attractive features of integrated silicon photonics, this paper aims to inspire further development in incorporating PICs with on-chip lasers in, but not limited to, these applications for substantial performance gains, green solutions, and mass production.

Zhou, Zhican↗
DOE OSTI2024

Investigating resource-efficient neutron/gamma classification ML models targeting eFPGAs

There has been considerable interest and resulting progress in implementing machine learning (ML) models in hardware over the last several years from the particle and nuclear physics communities. A big driver has been the release of the Python package, hls4ml, which has enabled porting models specified and trained using Python ML libraries to register transfer level (RTL) code. So far, the primary end targets have been commercial field-programmable gate arrays (FPGAs) or synthesized custom blocks on application specific integrated circuits (ASICs). However, recent developments in open-source embedded FPGA (eFPGA) frameworks now provide an alternate, more flexible pathway for implementing ML models in hardware. These customized eFPGA fabrics can be integrated as part of an overall chip design. In general, the decision between a fully custom, eFPGA, or commercial FPGA ML implementation will depend on the details of the end-use application. In this work, we explored the parameter space for eFPGA implementations of fully-connected neural network (fcNN) and boosted decision tree (BDT) models using the task of neutron/gamma classification with a specific focus on resource efficiency. We used data collected using an AmBe sealed source incident on Stilbene, which was optically coupled to an OnSemi J-series silicon photomultiplier (SiPM) to generate training and test data for this study. We investigated relevant input features and the effects of bit-resolution and sampling rate as well as trade-offs in hyperparameters for both ML architectures while tracking total resource usage. The performance metric used to track model performance was the calculated neutron efficiency at a gamma leakage of 10 -3 . The results of the study will be used to aid the specification of an eFPGA fabric, which will be integrated as part of a test chip.

47 OTHER INSTRUMENTATION↗
DOE OSTI2020

Invited: Software defined accelerators from learning tools environment

Next generation systems, such as edge devices, will need to provide efficient processing of machine learning (ML) algorithms along several metrics, including energy, performance, area, and latency. However, the quickly evolving field of ML makes it extremely difficult to generate accelerators able to support a wide variety of algorithms. At the same time, designing accelerators in hardware description languages (HDLs) by hand is hard and time consuming, and does not allow quick exploration of the design space. In this paper we present the Software Defined Accelerators From Learning Tools Environment (SODALITE), an automated open source high-level ML framework-to-verilog compiler targeting ML Application-Specific Integrated Circuits (ASICs) chiplets. The SODALITE approach will implement optimal designs by seamlessly combining custom components generated through high-level synthesis (HLS) with templated and fully tunable Intellectural Properties (IPs) and macros, integrated in an extendable resource library. Through a closed loop design space exploration engine, developers will be able to quickly explore their hardware designs along different dimensions.

High-Level Synthesis, Accelerators, Hardware-Softw↗
DOE OSTI2022

High-Density, Actively Multiplexed µECoG Array on Reinforced Silicone Substrate

Simultaneous interrogation of electrical signals from wide areas of the brain is vital for neuroscience research and can aid in understanding the mechanisms of brain function and treatments for neurological disorders. There emerges a demand for development of devices with highly conformal interfaces that can span large cortical regions, have sufficient spatial resolution, and chronic recording capability while keeping a small implantation footprint. In this work, we have designed 61 channel and 48 channel high-density, cortical, micro-electrocorticographic electrode arrays with 400 µm pitch on an ultra-soft but durable substrate. We have also developed a custom multiplexing integrated circuit (IC), methods for packaging the IC in a water-tight liquid crystal polymer casing, and a micro-bonding method for attaching the electronics package to the electrode array. With the integrated multiplexer, the number of external wire connections can be reduced to 16 wires, thereby diminishing the invasive footprint of the device. Both the electrode array and IC were tested in vivo in a rat model to demonstrate the ability to sense finely-localized electrophysiological signals.

Rachinskiy, Iakov↗
DOE OSTI2023

The New Small Wheel electronics

The increase in luminosity, and consequent higher backgrounds, of the LHC upgrades require improved rejection of fake tracks in the forward region of the ATLAS Muon Spectrometer. The New Small Wheel upgrade of the Muon Spectrometer aims to reduce the large background of fake triggers from track segments that don't originate from the interaction point. The New Small Wheel employs two detector technologies, the resistive strip Micromegas detectors and the “small” Thin Gap Chambers, with a total of 2.45 million electrodes to be sensed. The two technologies require the design of a complex electronics system given that it consists of two different detector technologies and is required to provide both precision readout and a fast trigger. It will operate in a high background radiation region up to about 20 kHz/cm 2 at the expected HL-LHC luminosity of $\mathcal{L}$= 7.5 × 10 34 cm -2 s -1 . The architecture of the system is strongly defined by the GBTx data aggregation ASIC, the newly-introduced FELIX data router and the software based data handler of the ATLAS detector. The electronics complex of this new detector was designed and developed in the last ten years and consists of multiple radiation tolerant Application Specific Integrated Circuits, multiple front-end boards, dense boards with FPGA's and purpose-built Trigger Processor boards within the ATCA standard. The New Small Wheel has been installed in 2021 and is undergoing integration within ATLAS for LHC Run 3. It should operate through the end of Run 4 (December 2032). In this manuscript, the overall design of the New Small Wheel electronics is presented.

47 OTHER INSTRUMENTATION↗
DOE OSTI2026

Advancements in NbTiN based circuits for Superconducting Digital Logic

Superconducting (SC) electronics have emerged as a promising platform for high-speed, energy-efficient computing and quantum information processing. This work, centered on NbTiN, presents recent advances in material science and fabrication methods leading to significant improvements in performance, scalability and vertical integration. We specifically report on fabrication and characterization of key components, including Josephson junctions (JJs), flux trapping structures and SC interconnects. Together, these efforts represent critical steps towards realizing practical, complex, dense and large-scale SC integrated circuits.

Pokhrel, A. [Imec,Heverlee,Belgium]↗
DOE OSTI2026

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope integrators. They are capable of working from room to cryogenic temperatures, down to 84 K. The present iteration of the ASIC has been fabricated including several design updates and the addition of an on-chip voltage reference, resulting in improved performance. This work presents the main vulnerabilities solved, the changes carried out, and the resulting performance benefits. Measurements with a skipper-CCD and the ASIC at 140 K showed that the single-electron resolution can be reached by averaging the measured charge in the analog domain using the analog pile-up technique with a readout noise as low as 0.11 erms of equivalent charge for 1200 samples. The channel-to-channel crosstalk was also characterized showing values better than -62 dB.

Alcalde Bessia, Fabricio↗