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At least 145 records · Page 8

Kepler Science Operations Center Architecture

We give an overview of the operational concepts and architecture of the Kepler Science Data Pipeline. Designed, developed, operated, and maintained by the Science Operations Center (SOC) at NASA Ames Research Center, the Kepler Science Data Pipeline is central element of the Kepler Ground Data System. The SOC charter is to analyze stellar photometric data from the Kepler spacecraft and report results to the Kepler Science Office for further analysis. We describe how this is accomplished via the Kepler Science Data Pipeline, including the hardware infrastructure, scientific algorithms, and operational procedures. The SOC consists of an office at Ames Research Center, software development and operations departments, and a data center that hosts the computers required to perform data analysis. We discuss the high-performance, parallel computing software modules of the Kepler Science Data Pipeline that perform transit photometry, pixel-level calibration, systematic error-correction, attitude determination, stellar target management, and instrument characterization. We explain how data processing environments are divided to support operational processing and test needs. We explain the operational timelines for data processing and the data constructs that flow into the Kepler Science Data Pipeline.

Middour, Christopher↗

Navigational Use of Cassini Delta V Telemetry

Telemetry data are used to improve navigation of the Saturn orbiting Cassini spacecraft. Thrust induced delta V's are computed on-board the spacecraft, recorded in telemetry, and downlinked to Earth. This paper discusses how and why the Cassini Navigation team utilizes spacecraft delta V telemetry. Operational changes making this information attractive to the Navigation Team will be briefly discussed, as will spacecraft hardware and software algorithms responsible for the on-board computation. An analysis of past delta V telemetry, providing calibrations and accuracies that can be applied to the estimation of future delta V activity, is described.

Roth, Duane C.↗

An Overview of Production and Validation of the SMAP Passive Soil Moisture Product

The Soil Moisture Active Passive (SMAP) mission is an L-band mission scheduled for launch in Jan. 2015. The SMAP instruments consist of a radar and a radiometer to obtain complementary information from space for soil moisture and freeze/thaw state research and applications. By utilizing novel designs in antenna construction, retrieval algorithms, and acquisition hardware, SMAP provides a capability for global mapping of soil moisture and freeze/thaw state with unprecedented accuracy, resolution, and coverage. This improvement in hydrosphere state measurement is expected to advance our understanding of the processes that link the terrestrial water, energy and carbon cycles, improve our capability in flood prediction and drought monitoring, and enhance our skills in weather and climate forecast. For swath-based soil moisture measurement, SMAP generates three operational geophysical data products: (1) the radiometer-only soil moisture product (L2_SM_P) posted at 36-kilometer resolution, (2) the radar-only soil moisture product (L2_SM_A) posted at 3-kilometers resolution, and (3) the radar-radiometer combined soil moisture product (L2_SM_AP) posted at 9-kilometers resolution. Each product draws on the strengths of the underlying sensor(s) and plays a unique role in hydroclimatological and hydrometeorological applications. A full suite of SMAP data products is given in Table 1.

passive microwave↗

Dynamical Decoupling for Measuring and Suppressing Crosstalk

Dynamical decoupling (DD) is a noise-mitigating strategy in which sequences of pulses are applied to single qubits to average out their interaction with the environment. DD has been extensively studied and demonstrated for suppressing single-qubit decoherence and can be tailored for different noise spectrum. We report another important adaptation of DD where crosstalk between qubits are suppressed. We demonstrate the efficiency of this procedure on quantum circuits on superconducting transmon-based quantum devices. We designed a family of syncopated DD sequences that effectively suppress ZZ coupling between qubit pairs, which is the dominating crosstalk form on the device. We insert DD to a quantum circuit whenever single qubits are idle (often during two-qubits gates on other qubits). While standard periodic DD suppress crosstalk between these qubits and their neighbors, the syncopated DD further decouples crosstalk between these qubits. We further designed short sequences that maximize the application of DD without adding time to the quantum circuit execution. Such DD sequences yield significant improvement of the performance of the algorithm on the hardware. The performance is further boosted by combining DD with another mitigation strategy, randomized compilation. Our work demonstrated that syncopated DD is effective and practical way to suppress crosstalk in quantum circuits and serves as a great probe to characterize the crosstalk and inform hardware design.

Quantum Computing↗

Trellises and Trellis-Based Decoding Algorithms for Linear Block Codes: A Recursive Maximum Likelihood Decoding - Part 3

The Viterbi algorithm is indeed a very simple and efficient method of implementing the maximum likelihood decoding. However, if we take advantage of the structural properties in a trellis section, other efficient trellis-based decoding algorithms can be devised. Recently, an efficient trellis-based recursive maximum likelihood decoding (RMLD) algorithm for linear block codes has been proposed. This algorithm is more efficient than the conventional Viterbi algorithm in both computation and hardware requirements. Most importantly, the implementation of this algorithm does not require the construction of the entire code trellis, only some special one-section trellises of relatively small state and branch complexities are needed for constructing path (or branch) metric tables recursively. At the end, there is only one table which contains only the most likely code-word and its metric for a given received sequence r = (r(sub 1), r(sub 2),...,r(sub n)). This algorithm basically uses the divide and conquer strategy. Furthermore, it allows parallel/pipeline processing of received sequences to speed up decoding.

Lin, Shu↗

Real-Time Adaptive Lossless Hyperspectral Image Compression using CCSDS on Parallel GPGPU and Multicore Processor Systems

The proposed CCSDS (Consultative Committee for Space Data Systems) Lossless Hyperspectral Image Compression Algorithm was designed to facilitate a fast hardware implementation. This paper analyses that algorithm with regard to available parallelism and describes fast parallel implementations in software for GPGPU and Multicore CPU architectures. We show that careful software implementation, using hardware acceleration in the form of GPGPUs or even just multicore processors, can exceed the performance of existing hardware and software implementations by up to 11x and break the real-time barrier for the first time for a typical test application.

realtime↗

Computation of Earth Science Products on Spaceborne Platforms

Spaceborne sensors like NASA's Hyperion hyperspectral imager generate huge data volumes, and several near-term trends indicate that data volumes will only increase. Next-generation hyperspectral missions, such as NASA's Hyperspectral Infrared Imager (HyspIRI), will operate at higher duty cycles and higher data rates, and their users will expect products to be generated from the data in near real time [1]. Barring a sudden advance in satellite downlink capacity, these trends point to a need to process data and generate products onboard the spacecraft. Rather than downlink an entire hyperspectral image cube, onboard processing enables satellites to downlink partial or completed scientific data products, which are often one to two orders of magnitude smaller than the original image. In addition, a satellite with onboard data processing resources and direct broadcast transmission equipment could send data products directly to first responders, research scientists or other users on the ground. Next-generation space-capable data processors will have a combination of reconfigurable gate arrays, digital signal processors and general-purpose CPUs. Correctly programmed and configured, these resources are sufficient to run sophisticated data analysis programs, including hyperspectral image processing algorithms that commonly run on desktop computers [2]. This paper describes how we implemented one such program, the HSEG hierarchical image segmentation algorithm, software commonly used on desktop and parallel processors, on a hardware platform designed to mimic a next-generation space-capable data processor [3]. We also describe our approach to porting the algorithm to and optimizing it for the new platform, and determine the expected performance gains enabled by our design. This extended abstract will describe the HSEG algorithm and hardware platform in greater detail, provide an analysis of the key function within the algorithm that required hardware acceleration, and describe our implementation of that function in hardware.

Fisher, Kevin↗

Efficient and Optimal Attitude Determination Using Recursive Global Positioning System Signal Operations

In this paper, a new and efficient algorithm is developed for attitude determination from Global Positioning System signals. The new algorithm is derived from a generalized nonlinear predictive filter for nonlinear systems. This uses a one time-step ahead approach to propagate a simple kinematics model for attitude determination. The advantages of the new algorithm over previously developed methods include: it provides optimal attitudes even for coplanar baseline configurations; it guarantees convergence even for poor initial conditions; it is a non-iterative algorithm; and it is computationally efficient. These advantages clearly make the new algorithm well suited to on-board applications. The performance of the new algorithm is tested on a dynamic hardware simulator. Results indicate that the new algorithm accurately estimates the attitude of a moving vehicle, and provides robust attitude estimates even when other methods, such as a linearized least-squares approach, fail due to poor initial starting conditions.

Crassidis, John L.↗

Preliminary results from a subsonic high-angle-of-attack flush airdata sensing (HI-FADS) system - Design, calibration, algorithm development, and flight test evaluation

A nonintrusive high angle-of-attack flush airdata sensing (HI-FADS) system was installed and flight-tested on the F-18 high alpha research vehicle. This paper discusses the airdata algorithm development and composite results expressed as airdata parameter estimates and describes the HI-FADS system hardware, calibration techniques, and algorithm development. An independent empirical verification was performed over a large portion of the subsonic flight envelope. Test points were obtained for Mach numbers from 0.15 to 0.94 and angles of attack from -8.0 to 55.0 deg. Angles of sideslip ranged from -15.0 to 15.0 deg, and test altitudes ranged from 18,000 to 40,000 ft. The HI-FADS system gave excellent results over the entire subsonic Mach number range up to 55 deg angle of attack. The internal pneumatic frequency response of the system is accurate to beyond 10 Hz.

Whitmore, Stephen A.↗

Efficient Implementation for Unitary Coupled Cluster State Preparation for Near-Term Quantum Computers

Unitary coupled cluster theory (UCC) is a common wave function ansatz for quantum simulation of molecular electronic structure using the variational quantum eigenvalue solver (VQE). Even for small molecules using a double-ζ basis, the number of variational parameters required to minimize the electronic energy (i.e., optimize the circuit) is large and beyond the reach of current quantum computers. For example, a circuit simulating C2 using the UCCSD ansatz and the cc-pVDZ basis set with frozen-core will require over 10,000 variational parameters and a Hilbert space of over 10^8 determinants. To make progress on simulating such molecular systems on near-term quantum computers, we explore how much of the optimization can be approximately prepared with classical simulation while reducing the number of optimization steps performed on a quantum device. Recently, Chen, Cheng, and Freericks [J. Chem. Theory Comput. 2021, 17, 841-847] presented an algorithm for the factorized form of the UCC ansatz that allows for efficient UCC optimizations on classical hardware. We flip the algorithm around and use it to prepare approximate quantum circuits for systems that require a large number of qubits to represent. We will present results from our implementation and discuss strategies for incorporating this implementation for algorithms involving near-term quantum computers.

J Wayne Mullinax↗

Efficient Implementation for Unitary Coupled Cluster State Preparation for Near-Term Quantum Computers

Unitary coupled cluster theory (UCC) is a common wave function ansatz for quantum simulation of molecular electronic structure using the variational quantum eigenvalue solver (VQE). Even for small molecules using a double-ζ basis, the number of variational parameters required to minimize the electronic energy (i.e., optimize the circuit) is large and beyond the reach of current quantum computers. For example, a circuit simulating C2 using the UCCSD ansatz and the cc-pVDZ basis set with frozen-core will require over 10,000 variational parameters and a Hilbert space of over 10^(8) determinants. To make progress on simulating such molecular systems on near-term quantum computers, we explore how much of the optimization can be approximately prepared with classical simulation while reducing the number of optimization steps performed on a quantum device. Recently, Chen, Cheng, and Freericks [J. Chem. Theory Comput. 2021, 17, 841-847] presented an algorithm for the factorized form of the UCC ansatz that allows for efficient UCC optimizations on classical hardware. We flip the algorithm around and use it to prepare approximate quantum circuits for systems that require a large number of qubits to represent. We will present results from our implementation and discuss strategies for incorporating this implementation for algorithms involving near-term quantum computers.

Quantum Computing↗

Efficient Implementation for Unitary Coupled Cluster State Preparation for Near-Term Quantum Computers

Unitary coupled cluster theory (UCC) is a common wave function ansatz for quantum simulation of molecular electronic structure using the variational quantum eigenvalue solver (VQE). Even for small molecules using a double-ζ basis, the number of variational parameters required to minimize the electronic energy (i.e., optimize the circuit) is large and beyond the reach of current quantum computers. For example, a circuit simulating C2 using the UCCSD ansatz and the cc-pVDZ basis set with frozen-core will require over 10,000 variational parameters and a Hilbert space of over 10^(8) determinants. To make progress on simulating such molecular systems on near-term quantum computers, we explore how much of the optimization can be approximately prepared with classical simulation while reducing the number of optimization steps performed on a quantum device. Recently, Chen, Cheng, and Freericks [J. Chem. Theory Comput. 2021, 17, 841-847] presented an algorithm for the factorized form of the UCC ansatz that allows for efficient UCC optimizations on classical hardware. We flip the algorithm around and use it to prepare approximate quantum circuits for systems that require a large number of qubits to represent. We will present results from our implementation and discuss strategies for incorporating this implementation for algorithms involving near-term quantum computers.

Quantum Computing↗

Framework for a space shuttle main engine health monitoring system

A framework developed for a health management system (HMS) which is directed at improving the safety of operation of the Space Shuttle Main Engine (SSME) is summarized. An emphasis was placed on near term technology through requirements to use existing SSME instrumentation and to demonstrate the HMS during SSME ground tests within five years. The HMS framework was developed through an analysis of SSME failure modes, fault detection algorithms, sensor technologies, and hardware architectures. A key feature of the HMS framework design is that a clear path from the ground test system to a flight HMS was maintained. Fault detection techniques based on time series, nonlinear regression, and clustering algorithms were developed and demonstrated on data from SSME ground test failures. The fault detection algorithms exhibited 100 percent detection of faults, had an extremely low false alarm rate, and were robust to sensor loss. These algorithms were incorporated into a hierarchical decision making strategy for overall assessment of SSME health. A preliminary design for a hardware architecture capable of supporting real time operation of the HMS functions was developed. Utilizing modular, commercial off-the-shelf components produced a reliable low cost design with the flexibility to incorporate advances in algorithm and sensor technology as they become available.

Hawman, Michael W.↗

Hardware-assisted software clock synchronization for homogeneous distributed systems

A clock synchronization scheme that strikes a balance between hardware and software solutions is proposed. The proposed is a software algorithm that uses minimal additional hardware to achieve reasonably tight synchronization. Unlike other software solutions, the guaranteed worst-case skews can be made insensitive to the maximum variation of message transit delay in the system. The scheme is particularly suitable for large partially connected distributed systems with topologies that support simple point-to-point broadcast algorithms. Examples of such topologies include the hypercube and the mesh interconnection structures.

Ramanathan, P.↗

Toward Evolvable Hardware Chips: Experiments with a Programmable Transistor Array

Evolvable Hardware is reconfigurable hardware that self-configures under the control of an evolutionary algorithm. We search for a hardware configuration can be performed using software models or, faster and more accurate, directly in reconfigurable hardware. Several experiments have demonstrated the possibility to automatically synthesize both digital and analog circuits. The paper introduces an approach to automated synthesis of CMOS circuits, based on evolution on a Programmable Transistor Array (PTA). The approach is illustrated with a software experiment showing evolutionary synthesis of a circuit with a desired DC characteristic. A hardware implementation of a test PTA chip is then described, and the same evolutionary experiment is performed on the chip demonstrating circuit synthesis/self-configuration directly in hardware.

Stoica, Adrian↗

Finite element computation with parallel VLSI

This paper describes a parallel processing computer consisting of a 16-bit microcomputer as a master processor which controls and coordinates the activities of 8086/8087 VLSI chip set slave processors working in parallel. The hardware is inexpensive and can be flexibly configured and programmed to perform various functions. This makes it a useful research tool for the development of, and experimentation with parallel mathematical algorithms. Application of the hardware to computational tasks involved in the finite element analysis method is demonstrated by the generation and assembly of beam finite element stiffness matrices. A number of possible schemes for the implementation of N-elements on N- or n-processors (N is greater than n) are described, and the speedup factors of their time consumption are determined as a function of the number of available parallel processors.

Mcgregor, J.↗

Reed-Solomon decoder

A Reed-Solomon decoder with dedicated hardware for five sequential algorithms was designed with overall pipelining by memory swapping between input, processing and output memories, and internal pipelining through the five algorithms. The code definition used in decoding is specified by a keyword received with each block of data so that a number of different code formats may be decoded by the same hardware.

Lahmeyer, Charles R.↗

On Benchmarking Quantum Heuristics

Present an outline of important aspects for benchmarking quantum algorithms, in particular quantum heuristics. Using quantum approximate optimization algorithm as an example, we demonstrate how the choice of cost Hamiltonian, of mixer, and of initial states can affect the performance. We also discuss how realistic aspects of near-term quantum hardware will influence the algorithm performance.

Wang, Zhihui↗