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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
NASA NTRS2005

Highly Reliable, High-Speed, Unidirectional Serial Data Links

Highly reliable, high-speed, unidirectional serial data-communication subsystems have been proposed to be installed in an upgrade of the computing systems aboard the space shuttles. The basic design concept of these serial data links is also adaptable to terrestrial use in applications in which there are requirements for highly reliable serial data communications. The hardware and software aspects of the architecture of the data links are dictated largely by a requirement, in the original space-shuttle application, for one computer to monitor the memory transactions and memory contents of other computers in real time with high reliability and without reliance on requests for retransmission. To minimize weight while affording a capability to transfer data at a required rate of 2.56 x 10(exp 8) bits per second, it was decided that the links would be serial ones of the fiber-channel type. [Fiber channel denotes a type of serial computer bus that is used to connect a computer (usually a supercomputer) with a high-speed data storage device. Depending on the specific application, the physical connection between the transmitter and receiver could be made via an optical fiber or a twisted pair of wires.] Heretofore, fiber-channel links have ordinarily been bidirectional and have operated under protocols that provide for receiving stations to detect errors and request retransmission when necessary. In the present case, the time taken by processing to request retransmission would conflict with the requirement for real-time transfer of data. To ensure reliability without retransmission, a link according to the proposal would utilize a modified version of the normal fiberchannel character set in conjunction with forward error correction by means of a Reed-Solomon code (see figure). The Reed-Solomon encoding and decoding and the translations between the normal and modified character sets would be effected by logic circuitry external to the fiber-channel transmitter and receiver, which would be commercial off-the-shelf units. The receiving end of the link could detect and correct errors at a rate as high as 4 million times per second, if necessary. The receiver detects uncorrectable double-byte errors. It has been estimated that uncorrectable-error rate would amount to one failure in about 10(exp 19) characters.

Cole, Robert M.↗
NASA NTRS2010

Distributed and recoverable digital control system

A real-time multi-tasking digital control system with rapid recovery capability is disclosed. The control system includes a plurality of computing units comprising a plurality of redundant processing units, with each of the processing units configured to generate one or more redundant control commands. One or more internal monitors are employed for detecting data errors in the control commands. One or more recovery triggers are provided for initiating rapid recovery of a processing unit if data errors are detected. The control system also includes a plurality of actuator control units each in operative communication with the computing units. The actuator control units are configured to initiate a rapid recovery if data errors are detected in one or more of the processing units. A plurality of smart actuators communicates with the actuator control units, and a plurality of redundant sensors communicates with the computing units.

Stange, Kent↗
NASA NTRS2005

Multiple Embedded Processors for Fault-Tolerant Computing

A fault-tolerant computer architecture has been conceived in an effort to reduce vulnerability to single-event upsets (spurious bit flips caused by impingement of energetic ionizing particles or photons). As in some prior fault-tolerant architectures, the redundancy needed for fault tolerance is obtained by use of multiple processors in one computer. Unlike prior architectures, the multiple processors are embedded in a single field-programmable gate array (FPGA). What makes this new approach practical is the recent commercial availability of FPGAs that are capable of having multiple embedded processors. A working prototype (see figure) consists of two embedded IBM PowerPC 405 processor cores and a comparator built on a Xilinx Virtex-II Pro FPGA. This relatively simple instantiation of the architecture implements an error-detection scheme. A planned future version, incorporating four processors and two comparators, would correct some errors in addition to detecting them.

Bolotin, Gary↗
NASA NTRS1966

Detection system ensures positive alarm activation in digital message loss

Lost Word Detection System /LOWDS/ provides special identification for each error detection message transmitted from receiver to transmitter. The message is identified as an original message or an n-times retransmitted message so the receiver can detect where a retransmission request was not fulfilled and activate an alarm.

Bokros, P.↗
NASA NTRS1984

A fault-tolerant software strategy for digital systems

Techniques developed for producing fault-tolerant software are described. Tolerance is required because of the impossibility of defining fault-free software. Faults are caused by humans and can appear anywhere in the software life cycle. Tolerance is effected through error detection, damage assessment, recovery, and fault treatment, followed by return of the system to service. Multiversion software comprises two or more versions of the software yielding solutions which are examined by a decision algorithm. Errors can also be detected by extrapolation from previous results or by the acceptability of results. Violations of timing specifications can reveal errors, or the system can roll back to an error-free state when a defect is detected. The software, when used in flight control systems, must not impinge on time-critical responses. Efforts are still needed to reduce the costs of developing the fault-tolerant systems.

Hitt, E. F.↗
NASA NTRS1993

A (72, 36; 15) box code

A (72,36;15) box code is constructed as a 9 x 8 matrix whose columns add to form an extended BCH-Hamming (8,4;4) code and whose rows sum to odd or even parity. The newly constructed code, due to its matrix form, is easily decodable for all seven-error and many eight-error patterns. The code comes from a slight modification in the parity (eighth) dimension of the Reed-Solomon (8,4;5) code over GF(512). Error correction uses the row sum parity information to detect errors, which then become erasures in a Reed-Solomon correction algorithm.

Solomon, G.↗
NASA NTRS1981

Erasure decoding in burst-error channels

A proven means of communicating reliably in a burst-error channel is the code interleaving scheme. Code symbols from a number of component codes are interleaved before being sent through the channel. This method effectively distributes the error detection and correction burden among the component codes and makes errors occurring in a codeword from each component code more or less independent. Erasure decoding techniques allow further refinement on the code interleaving concept. Their application leads to improved overall code performance when the symbol depth of the lead code is shallow compared to the average error-burst length of the channel. Theoretical formulations derived for predicting the performance of separate decoding and erasure decoding schemes are valuable in providing reasonably good estimates on redundancy requirements of the component codes.

Leung, K. S.↗
NASA NTRS2022

Europa Clipper Payload Verification and Validation: Avionics-Instrument Interface Test Campaign

NASA's Europa Clipper mission will investigate Jupiter's icy moon Europa using a payload suite consisting of nine instruments to address a range of scientific objectives concerning Europa's habitability. As the project proceeds past its Critical Design Review, confidence is being built in the system's ability to achieve mission objectives through the implementation of a rigorous payload verification and validation (V&V) program. As part of this payload V&V program, instrument box-level testing was performed by the payload team to verify select instrument-avionics interface requirements. This testing was performed at JPL using the avionics testbed's Bulk Data Storage Emulator (BDSEM) with visiting instrument Test Models. This paper summarizes the Data Link test campaign involving roughly four days of functional testing per instrument, including planning, testing methods, types of issues found, and the requirement closure process. Detail is also provided on the development, deployment, and validation of a standardized analysis tool used in data reviews. This testing verified requirements related to commanding rates, loss of link, packet format, clock counters, loopback test capability, and SpaceWire jitter and skew margins. Additional risk reduction testing of basic commanding, counter behavior, science data collection and transfer, and interface swapping was also performed. Because the BDSEM venue was not originally designed to be a run for record venue, the process of characterizing venue fidelity and establishing suitability for requirement closure using data collected in this venue will also be addressed.In order to close requirements, an extensible tool was developed to post-process instrument command and telemetry data from their original binary to a human-readable format and give visibility to errors detected within the data, such as packets with Cyclic Redundancy Check errors. This tool, called payload-packet-parser, is a Python 3.9 command line tool built using a variety of open-source Python libraries. Payload-packet-parser was designed to support parsing command and telemetry packets for all Europa Clipper instruments and additional analysis tools were developed for verification of specific information interface requirements. This test campaign, including post-processing using a single parsing and verification toolset, allowed for early interface testing, alleviating testing burdens on instrument teams and buying down risk on the instrument-avionics interface by finding hardware and software issues and idiosyncrasies prior to integration with system test venues. Over twenty issues were discovered across the payload, resulting in software updates and instrument rework well in advance of any system impacts. This paper concludes with an assessment of benefits and costs of this type of testing and lessons learned.

Montanez, Leticia↗
NASA NTRS1992

Self-dual (48,24;12) codes

Two self-dual (48,24;12) codes are constructed as 6 x 8 matrices whose columns add up to form an extended BCH-Hamming (8,4;4) code and whose rows sum to odd or even parity. The codes constructed have the identical weight structure of the extended quadratic residue code of length 48. Algebraic isomorphisms may exist between pairs of these three codes. However, because of their matrix form, the newly constructed codes are easily correctable for all five-error and many six-error patterns. The first code comes from restricting a binary cyclic (63,18;36) code to a 6 x 7 matrix and then adjoining six dimensions to the extended 6 x 8 matrix. These six dimensions are generated by linear combinations of row permutations of a 6 x 8 matrix of weight 12, whose sums of rows and columns add to one. The second code comes from a slight modification in the parity (eighth) dimension of the Reed-Solomon (8,4;5) code over GF(64). Error correction in both codes uses the row sum parity information to detect errors in the correction algorithm.

Solomon, G.↗
NASA NTRS1981

Failure detection and isolation analysis of a redundant strapdown inertial measurement unit

The objective of this study was to define and develop techniques for failure detection and isolation (FDI) algorithms for a dual fail/operational redundant strapdown inertial navigation system are defined and developed. The FDI techniques chosen include provisions for hard and soft failure detection in the context of flight control and navigation. Analyses were done to determine error detection and switching levels for the inertial navigation system, which is intended for a conventional takeoff or landing (CTOL) operating environment. In addition, investigations of false alarms and missed alarms were included for the FDI techniques developed, along with the analyses of filters to be used in conjunction with FDI processing. Two specific FDI algorithms were compared: the generalized likelihood test and the edge vector test. A deterministic digital computer simulation was used to compare and evaluate the algorithms and FDI systems.

Motyka, P.↗
NASA NTRS1989

Detection and avoidance of errors in computer software

The acceptance test errors of a computer software project to determine if the errors could be detected or avoided in earlier phases of development. GROAGSS (Gamma Ray Observatory Attitude Ground Support System) was selected as the software project to be examined. The development of the software followed the standard Flight Dynamics Software Development methods. GROAGSS was developed between August 1985 and April 1989. The project is approximately 250,000 lines of code of which approximately 43,000 lines are reused from previous projects. GROAGSS had a total of 1715 Change Report Forms (CRFs) submitted during the entire development and testing. These changes contained 936 errors. Of these 936 errors, 374 were found during the acceptance testing. These acceptance test errors were first categorized into methods of avoidance including: more clearly written requirements; detail review; code reading; structural unit testing; and functional system integration testing. The errors were later broken down in terms of effort to detect and correct, class of error, and probability that the prescribed detection method would be successful. These determinations were based on Software Engineering Laboratory (SEL) documents and interviews with the project programmers. A summary of the results of the categorizations is presented. The number of programming errors at the beginning of acceptance testing can be significantly reduced. The results of the existing development methodology are examined for ways of improvements. A basis is provided for the definition is a new development/testing paradigm. Monitoring of the new scheme will objectively determine its effectiveness on avoiding and detecting errors.

Kinsler, Les↗
NASA NTRS1982

Evaluating software development by analysis of changes: The data from the software engineering laboratory

An effective data collection methodology for evaluating software development methodologies was applied to four different software development projects. Goals of the data collection included characterizing changes and errors, characterizing projects and programmers, identifying effective error detection and correction techniques, and investigating ripple effects. The data collected consisted of changes (including error corrections) made to the software after code was written and baselined, but before testing began. Data collection and validation were concurrent with software development. Changes reported were verified by interviews with programmers.

Source record↗
NASA NTRS1993

Modifying real convolutional codes for protecting digital filtering systems

A novel method is proposed for protecting digital filters from temporary and permanent failures that are not easily detected by conventional fault-tolerant computer design principles, on the basis of the error-detecting properties of real convolutional codes. Erroneous behavior is detected by externally comparing the calculated and regenerated parity samples. Great simplifications are obtainable by modifying the code structure to yield simplified parity channels with finite impulse response structures. A matrix equation involving the original parity values of the code and the polynomial of the digital filter's transfer function is formed, and row manipulations separate this equation into a set of homogeneous equations constraining the modifying scaling coefficients and another set which defines the code parity values' implementation.

Redinbo, G. R.↗
NASA NTRS1994

Differential sea-state bias: A case study using TOPEX/POSEIDON data

We used selected data from the NASA altimeter TOPEX/POSEIDON to calculate differences in range measured by the C and Ku-band altimeters when the satellite overflew 5 to 15 m waves late at night. The range difference is due to free electrons in the ionosphere and to errors in sea-state bias. For the selected data the ionospheric influence on Ku range is less than 2 cm. Any difference in range over short horizontal distances is due only to a small along-track variability of the ionosphere and to errors in calculating the differential sea-state bias. We find that there is a barely detectable error in the bias in the geophysical data records. The wave-induced error in the ionospheric correction is less than 0.2% of significant wave height. The equivalent error in differential range is less than 1% of wave height. Errors in the differential sea-state bias calculations appear to be small even for extreme wave heights that greatly exceed the conditions on which the bias is based. The results also improved our confidence in the sea-state bias correction used for calculating the geophysical data records. Any error in the correction must influence Ku and C-band ranges almost equally.

Stewart, Robert H.↗
NASA NTRS1990

A robust CELP coder with source-dependent channel coding

A CELP coder using Source Dependent Channel Encoding (SDCE) for optimal channel error protection is introduced. With SDCE, each of the CELP parameters are encoded by minimizing a perceptually meaningful error criterion under prevalent channel conditions. Unlike conventional channel coding schemes, SDCE allows for optimal balance between error detection and correction. The experimental results show that the CELP system is robust under various channel bit error rates and displays a graceful degradation in SSNR as the channel error rate increases. This is a desirable property to have in a coder since the exact channel conditions cannot usually be specified a priori.

Sukkar, Rafid A.↗
NASA NTRS2012

Development of Next Generation Memory Test Experiment for Deployment on a Small Satellite

The original Memory Test Experiment successfully flew on the FASTSAT satellite launched in November 2010. It contained a single Ramtron 512K ferroelectric memory. The memory device went through many thousands of read/write cycles and recorded any errors that were encountered. The original mission length was schedule to last 6 months but was extended to 18 months. New opportunities exist to launch a similar satellite and considerations for a new memory test experiment should be examined. The original experiment had to be designed and integrated in less than two months, so the experiment was a simple design using readily available parts. The follow-on experiment needs to be more sophisticated and encompass more technologies. This paper lays out the considerations for the design and development of this follow-on flight memory experiment. It also details the results from the original Memory Test Experiment that flew on board FASTSAT. Some of the design considerations for the new experiment include the number and type of memory devices to be used, the kinds of tests that will be performed, other data needed to analyze the results, and best use of limited resources on a small satellite. The memory technologies that are considered are FRAM, FLASH, SONOS, Resistive Memory, Phase Change Memory, Nano-wire Memory, Magneto-resistive Memory, Standard DRAM, and Standard SRAM. The kinds of tests that could be performed are read/write operations, non-volatile memory retention, write cycle endurance, power measurements, and testing Error Detection and Correction schemes. Other data that may help analyze the results are GPS location of recorded errors, time stamp of all data recorded, radiation measurements, temperature, and other activities being perform by the satellite. The resources of power, volume, mass, temperature, processing power, and telemetry bandwidth are extremely limited on a small satellite. Design considerations must be made to allow the experiment to not interfere with the satellite s primary mission.

MacLeod, Todd↗
NASA NTRS1987

Decoding of DBEC-TBED Reed-Solomon codes

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256 K bit DRAM's are organized in 32 K x 8 bit-bytes. Byte-oriented codes such as Reed-Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. The paper presents a special decoding technique for double-byte-error-correcting, triple-byte-error-detecting RS codes which is capable of high-speed operation. This technique is designed to find the error locations and the error values directly from the syndrome without having to use the iterative algorithm to find the error locator polynomial.

Deng, Robert H.↗