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Coded or modulated digital data converts to nonreturn to zero /NRZ/ data. Technique includes logic implementation and pertinent timing diagrams. Demodulation to NRZ facilitates digital logic operations on incoming data. Phase-delay modulation has advantage of inherent self-timing not present in NRZ modulation.
The design of Integrated Circuits has evolved past the black art practiced by a few semiconductor companies to a world wide community of users. This was basically accomplished by the development of computer aided design tools which were made available to this community. As the tools matured into different components of the design task they were accepted into the community at large. However, the next step in this evolution is being ignored by the large tool vendors hindering the continuation of this process. With system level definition and simulation through the logic specification well understood, why is the physical generation so blatantly ignored. This portion of the development is still treated as an isolated task with information being passed from the designer to the layout function. Some form of result given back but it severely lacks full definition of what has transpired. The level of integration in I.C.'s for tomorrow, whether through new processes or applications will require higher speeds, increased transistor density, and non-digital performance which can only be achieved through attention to the physical implementation.
A digitized synchronous demodulator is constructed entirely of digital components including timing logic, an accumulator, and means to digitally filter the digital output signal. Indirectly, it accepts, at its input, periodic analog signals which are converted to digital signals by traditional analog-to-digital conversion techniques. Broadly, the input digital signals are summed to one of two registers within an accumulator, based on the phase of the input signal and medicated by timing logic. At the end of a predetermined number of cycles of the inputted periodic signals, the contents of the register that accumulated samples from the negative half cycle is subtracted from the accumulated samples from the positive half cycle. The resulting difference is an accurate measurement of the narrow band amplitude of the periodic input signal during the measurement period. This measurement will not include error sources encountered in prior art synchronous demodulators using analog techniques such as offsets, charge injection errors, temperature drift, switching transients, settling time, analog to digital converter missing code, and linearity errors.
Error detecting and correcting codes for locating logic faults in digital computers
The paper describes the fabrication and operation of an optical parallel logic (OPAL) device which performs Boolean algebraic operations on binary images. Several logic operations on two input binary images were demonstrated using an 8 x 8 device with a CdS photoconductor and a twisted nematic liquid crystal. Two such OPAL devices can be interconnected to form a half-adder circuit which is one of the essential components of a CPU in a digital signal processor.
Petahertz, or lightwave, electronics uses tailored optical waveforms to control charge carriers in an electronic circuit at petahertz frequencies. This may enable faster processing than conventional pulsed electronics, which cannot be scaled beyond gigahertz frequencies. In recent years, petahertz-scale currents driven by optical fields have been measured in solid-state systems and nanoscale structures, with several proof-of-principle demonstrations of sub-optical-cycle current generation and optical-field-resolved waveform detection at the sub-femtosecond to few-femtosecond scale. Recent work has taken the first steps towards digital and quantum operation by exploring optical-field-driven logic and memory functionality. Here, in this Review, we discuss the progress towards sub-cycle field-driven current injection, highlighting key theoretical concepts, experimental milestones, and questions remaining as we push towards realizing petahertz electronics for ultrafast optical waveform analysis, digital logic, communications, and quantum computation.
Standard Transistor Array (STAR) design system is semicustom approach to generating random-logic integrated MOS digital circuits. Primary program in STAR system is CAPSTAR, STAR Cell Arrangement Program. CAPSTAR is augmented by automatic routining program, Display program and library of logic cells.
Development and use of digital circuits called all-magnetic logic are reported. In these circuits the magnetic elements and their windings comprise the active circuit devices in the logic portion of a system. The ferrite logic device belongs to the all-magnetic class of logic circuits. The FLO device is novel in that it makes use of a dual or bimaterial ferrite composition in one physical ceramic body. This bimaterial feature, coupled with its potential for relatively high speed operation, makes it attractive for high reliability applications. (Maximum speed of operation approximately 50 kHz.)
Digital computer-aided electric logic circuit analysis and design bibliography
A 0.5-2.3 kW xenon ion propulsion system is presently being developed under the NASA Solar Electric Propulsion Technology Application Readiness (NSTAR) program. This propulsion system includes a 30 cm diameter xenon ion thruster, a Digital Control Interface Unit, a xenon feed system, and a power processing unit (PPU). The PPU consists of the power supply assemblies which operate the thruster neutralizer, main discharge chamber, and ion optics. Also included are recycle logic and a digital microcontroller. The neutralizer and discharge power supplies employ a dual use configuration which combines the functions of two power supplies into one, significantly simplifying the PPU. Further simplification was realized by implementing a single thruster control loop which regulates the beam current via the discharge current. Continuous throttling is possible over a 0.5-2.3 kW output power range. All three power supplies have been fabricated and tested with resistive loads, and have been combined into a single breadboard unit with the recycle logic and microcontroller. All line and load regulation test results show the power supplies to be within the NSTAR flight PPU specified power output of 1.98 kW. The overall efficiency of the PPU, calculated as the combined efficiencies of the power supplies and controller, at 2.3 kW delivered to resistive loads was 0.90. The component was 6.16 kg. Integration testing of the neutralizer and discharge power supplies with a functional model thruster revealed no issues with discharge ignition or steady state operation.
Field programmable logic array (FPLA) is used to make 3-bit arithmetic logic unit (ALU) for large integrator that can be read and cleared while new data is added to begin new integral. Arrangement of device can provide for full carry/lookahead capability with minimum gate delays.
Ten-bit analog-to-digital converter with standard logic circuits
Described herein are various technologies pertaining to randomizing logic associated with dangling nodes in a digital circuit design. A dangling node is an input to or output from a logic gate in the digital circuit design that is identified as not impacting a desired output of the digital circuit design. Randomizing the logic associated with a dangling node can include deleting a logic gate, adding a logic gate, replacing a logic gate with another logic gate, etc. Randomizing the logic associated with the dangling node prevents hardware trojans that may have been inserted into the circuit design from being implemented in a circuit that is generated based upon the design.
Closed circuit television /CCTV/ system automatically guides a welding torch to position the welding arc accurately along weld seams. Digital counting and logic techniques incorporated in the control circuitry, ensure performance reliability.
A pulse stretcher for narrow pulses is presented. The stretcher is composed of an analog section for processing each arriving analog pulse and a digital section with logic for providing command signals to the gates and switches in the analog section.
Small, low-cost comparator with 24-bit-precision yields ratio signal from pair of analog or digital input signals. Arithmetic logic chips (bit-slice) sample two 24-bit analog-to-digital converters approximately once every millisecond and accumulate them in two 24-bit registers. Approach readily modified to arbitrary precision.
Nonvolatile electronic memory devices that store data in the form of electrical- resistance values, and memory circuits based on such devices, have been invented. These devices and circuits exploit an electrically-variable-resistance phenomenon that occurs in thin films of certain oxides that exhibit the colossal magnetoresistive (CMR) effect. It is worth emphasizing that, as stated in the immediately preceding article, these devices function at room temperature and do not depend on externally applied magnetic fields. A device of this type is basically a thin film resistor: it consists of a thin film of a CMR material located between, and in contact with, two electrical conductors. The application of a short-duration, low-voltage current pulse via the terminals changes the electrical resistance of the film. The amount of the change in resistance depends on the size of the pulse. The direction of change (increase or decrease of resistance) depends on the polarity of the pulse. Hence, a datum can be written (or a prior datum overwritten) in the memory device by applying a pulse of size and polarity tailored to set the resistance at a value that represents a specific numerical value. To read the datum, one applies a smaller pulse - one that is large enough to enable accurate measurement of resistance, but small enough so as not to change the resistance. In writing, the resistance can be set to any value within the dynamic range of the CMR film. Typically, the value would be one of several discrete resistance values that represent logic levels or digits. Because the number of levels can exceed 2, a memory device of this type is not limited to binary data. Like other memory devices, devices of this type can be incorporated into a memory integrated circuit by laying them out on a substrate in rows and columns, along with row and column conductors for electrically addressing them individually or collectively.
Remotely sensing the Earth's surface using GNSS signals as bi-static radar sources is one of the most challenging applications for radiometric instrument design. As part of NASA's Instrument Incubator Program, our group at JPL has built a prototype instrument, TOGA (Time-shifted, Orthometric, GNSS Array), to address a variety of GNSS science needs. Observing GNSS reflections is major focus of the design/development effort. The TOGA design features a steerable beam antenna array which can form a high-gain antenna pattern in multiple directions simultaneously. Multiple FPGAs provide flexible digital signal processing logic to process both GPS and Galileo reflections. A Linux OS based science processor serves as experiment scheduler and data post-processor. This paper outlines the TOGA design approach as well as preliminary results of reflection data collected from test flights over the Pacific ocean. This reflections data demonstrates observation of the GPS L1/L2C/L5 signals.