Modulation by pseudo-random sequences.
Signal spectra and digital characteristics in design of binary modulation systems
LOGIC CIRCUIT↗
SEARCH · Engineering Papers
Results for “digital circuits designs”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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An introduction to the BANNING design automation system for shuttle microelectronic hardware development
The BANNING MOS design system is presented. It complements rather than supplant the normal design activities associated with the design and fabrication of low-power digital electronic equipment. BANNING is user-oriented and requires no programming experience to use effectively. It provides the user a simulation capability to aid in his circuit design and it eliminates most of the manual operations involved in the layout and artwork generation of integrated circuits. An example of its operation is given and some additional background reading is provided.
Mcgrady, W. J.↗
Broad-Bandwidth FPGA-Based Digital Polyphase Spectrometer
With present concern for ecological sustainability ever increasing, it is desirable to model the composition of Earth s upper atmosphere accurately with regards to certain helpful and harmful chemicals, such as greenhouse gases and ozone. The microwave limb sounder (MLS) is an instrument designed to map the global day-to-day concentrations of key atmospheric constituents continuously. One important component in MLS is the spectrometer, which processes the raw data provided by the receivers into frequency-domain information that cannot only be transmitted more efficiently, but also processed directly once received. The present-generation spectrometer is fully analog. The goal is to include a fully digital spectrometer in the next-generation sensor. In a digital spectrometer, incoming analog data must be converted into a digital format, processed through a Fourier transform, and finally accumulated to reduce the impact of input noise. While the final design will be placed on an application specific integrated circuit (ASIC), the building of these chips is prohibitively expensive. To that end, this design was constructed on a field-programmable gate array (FPGA). A family of state-of-the-art digital Fourier transform spectrometers has been developed, with a combination of high bandwidth and fine resolution. Analog signals consisting of radiation emitted by constituents in planetary atmospheres or galactic sources are downconverted and subsequently digitized by a pair of interleaved analog-to-digital converters (ADCs). This 6-Gsps (gigasample per second) digital representation of the analog signal is then processed through an FPGA-based streaming fast Fourier transform (FFT). Digital spectrometers have many advantages over previously used analog spectrometers, especially in terms of accuracy and resolution, both of which are particularly important for the type of scientific questions to be addressed with next-generation radiometers.
Jamot, Robert F.↗
Product assurance technology for custom LSI/VLSI electronics
The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification.
Buehler, M. G.↗
CMOS output buffer wave shaper
As the switching speeds and densities of Digital CMOS integrated circuits continue to increase, output switching noise becomes more of a problem. A design technique which aids in the reduction of switching noise is reported. The output driver stage is analyzed through the use of an equivalent RLC circuit. The results of the analysis are used in the design of an output driver stage. A test circuit based on these techniques is being submitted to MOSIS for fabrication.
Albertson, L.↗
Self-Timed Digital System Design
A timing and control strategy that can be used to realize synchronous systems with a level of performance that approaches that of asynchronous circuits or systems was developed in this work. This approach is based upon a single-phase synchronous circuit/system architecture with a variable period clock. The handshaking signals required for asynchronous self-timed circuits are not needed. Dynamic power supply current monitoring is used to generate the timing information, that is comparable to the completion signal found in self-timed circuits; this timing information is used to modify the circuit clock period.
Walker, Alvernon↗
Embedded Fluidic Sensing and Control with Soft Open‐Cell Foams
Abstract The synthesis of soft matter intelligence with circuit‐driven logic has enabled a new class of robots that perform complex tasks or conform to specialized form factors in unique ways that cannot be realized through conventional designs. Translating this hybrid approach to fluidic systems, the present work addresses the need for sheet‐based circuit materials by leveraging the innate porosity of foam—a soft material—to develop pneumatic components that support digital logic, mixed‐signal control, and analog force sensing in wearables and soft robots. Analytical tools and experimental techniques developed in this work serve to elucidate compressible gas flow through porous sheets, and to inform the design of centimeter‐sized foam resistors with fluidic resistances on the order of 10 9 Pa s m −3 . When embedded inside soft robots and wearables, these resistors facilitate diverse functionalities spanning both sensing and control domains, including digital logic using textile logic gates, digital‐to‐analog signal conversion using ladder networks, and analog sensing of forces up to 40 N via compression‐induced changes in resistance. By combining features of both circuit‐based and materials‐based approaches, foam‐enabled fluidic circuits serve as a useful paradigm for future hybrid robotic architectures that fully embody the sensing and computing capabilities of soft fluidic materials.
Rajappan, Anoop↗
Parallel digital modem using multirate digital filter banks
A new class of architectures for an all-digital modem is presented in this report. This architecture, referred to as the parallel receiver (PRX), is based on employing multirate digital filter banks (DFB's) to demodulate, track, and detect the received symbol stream. The resulting architecture is derived, and specifications are outlined for designing the DFB for the PRX. The key feature of this approach is a lower processing rate then either the Nyquist rate or the symbol rate, without any degradation in the symbol error rate. Due to the freedom in choosing the processing rate, the designer is able to arbitrarily select and use digital components, independent of the speed of the integrated circuit technology. PRX architecture is particularly suited for high data rate applications, and due to the modular structure of the parallel signal path, expansion to even higher data rates is accommodated with each. Applications of the PRX would include gigabit satellite channels, multiple spacecraft, optical links, interactive cable-TV, telemedicine, code division multiple access (CDMA) communications, and others.
Sadr, Ramin↗
Automated Addressing Failure Detection for Multiplexer Systems
Multiplexers are electronic devices which select between several input signals and deliver an output signal. Also known as data selectors or mux, multiplexers are commonly used in circuit design to provide signal switching, simplify hardware and manufacturing, and decrease cost. Systems which use a digital mux as a switch or selector are vulnerable to events called addressing failures, arising in hardware or software. An addressing failure results in the system requesting, or the mux delivering, a data signal other than the one intended. The unintended use of this erroneous signal may lead to system-level failures. This paper discusses a novel method of automatic detection for addressing failures, utilizing multiplexer channelization and a monitoring algorithm.
multiplexer↗
A high speed CMOS A/D converter
This paper presents a high speed analog-to-digital (A/D) converter. The converter is a 7 bit flash converter with one half LSB accuracy. Typical parts will function at approximately 200 MHz. The converter uses a novel comparator circuit that is shown to out perform more traditional comparators, and thus increases the speed of the converter. The comparator is a clocked, precharged circuit that offers very fast operation with a minimal offset voltage (2 mv). The converter was designed using a standard 1 micron digital CMOS process and is 2,244 microns by 3,972 microns.
Wiseman, Don R.↗
A digital beacon receiver
A digital satellite beacon receiver is described which provides measurement information down to a carrier/noise density ratio approximately 15 dB below that required by a conventional (phase locked loop) design. When the beacon signal fades, accuracy degrades gracefully, and is restored immediately (without hysteresis) on signal recovery, even if the signal has faded into the noise. Benefits of the digital processing approach used include the minimization of operator adjustments, stability of the phase measuring circuits with time, repeatability between units, and compatibility with equipment not specifically designed for propagation measuring. The receiver has been developed for the European Olympus satellite which has continuous wave (CW) beacons at 12.5 and 29.7 GHz, and a switched polarization beacon at 19.8 GHz approximately, but the system can be reconfigured for CW and polarization-switched beacons at other frequencies.
Ransome, Peter D.↗
Advanced technology satellite demodulator development
Ford Aerospace has developed a proof-of-concept satellite 8 phase shift keying (PSK) modulation and coding system operating in the Time Division Multiple Access (TDMA) mode at a data range of 200 Mbps using rate 5/6 forward error correction coding. The 80 Msps 8 PSK modem was developed in a mostly digital form and is amenable to an ASIC realization in the next phase of development. The codec was developed as a paper design only. The power efficiency goal was to be within 2 dB of theoretical at a bit error rate (BER) of 5x10(exp 7) while the measured implementation loss was 4.5 dB. The bandwidth efficiency goal was 2 bits/sec/Hz while the realized bandwidth efficiency was 1.8 bits/sec/Hz. The burst format used a preamble of only 40 8 PSK symbol times including 32 symbols of all zeros and an eight symbol unique word. The modem and associated special test equipment (STE) were fabricated mostly on a specially designed stitch-weld board although a few of the highest rate circuits were built on printed circuit cards. All the digital circuits were ECL to support the clock rates of from 80 MHz to 360 MHz. The transmitter and receiver matched filters were square-root Nyquist bandpass filters realized at the 3.37 GHz i.f. The modem operated as a coherent system although no analog phase locked (PLL) loop was employed. Within the budgetary constraints of the program, the approach to the demodulator has been proven and is eligible to proceed to the next phase of development of a satellite demodulator engineering model. This would entail the development of an ASIC version of the digital portion of the demodulator, and MMIC version of the quadrature detector, and SAW Nyquist filters to realize the bandwidth efficiency.
Ames, Stephen A.↗
Design methods for fault-tolerant finite state machines
VLSI electronic circuits are increasingly being used in space-borne applications where high levels of radiation may induce faults, known as single event upsets. In this paper we review the classical methods of designing fault tolerant digital systems, with an emphasis on those methods which are particularly suitable for VLSI-implementation of finite state machines. Four methods are presented and will be compared in terms of design complexity, circuit size, and estimated circuit delay.
Niranjan, Shailesh↗
Programmed multiplexing system simultaneously monitors several voltages
System consists of digital voltmeter with binary coded decimal output, programmer, multiplexer, and two to six gated digital displays. Maximum number of circuits monitored is determined by digital voltmeter, rate of change of parameter being measured and complexity of multiplexer design.
Wright, L. S.↗
High-Speed Binary-Output Image Sensor
Photodetector outputs digitized by circuitry on same integrated-circuit chip. Developmental special-purpose binary-output image sensor designed to capture up to 1,000 images per second, with resolution greater than 10 to the 6th power pixels per image. Lower-resolution but higher-frame-rate prototype of sensor contains 128 x 128 array of photodiodes on complementary metal oxide/semiconductor (CMOS) integrated-circuit chip. In application for which it is being developed, sensor used to examine helicopter oil to determine whether amount of metal and sand in oil sufficient to warrant replacement.
Fossum, Eric↗
Using Modern Design Tools for Digital Avionics Development
Using Modem Design Tools for Digital Avionics Development Shrinking development time and increased complexity of new avionics forces the designer to use modem tools and methods during hardware development. Engineers at the Marshall Space Flight Center have successfully upgraded their design flow and used it to develop a Mongoose V based radiation tolerant processor board for the International Space Station's Water Recovery System. The design flow, based on hardware description languages, simulation, synthesis, hardware models, and full functional software model libraries, allowed designers to fully simulate the processor board from reset, through initialization before any boards were built. The fidelity of a digital simulation is limited to the accuracy of the models used and how realistically the designer drives the circuit's inputs during simulation. By using the actual silicon during simulation, device modeling errors are reduced. Numerous design flaws were discovered early in the design phase when they could be easily fixed. The use of hardware models and actual MIPS software loaded into full functional memory models also provided checkout of the software development environment. This paper will describe the design flow used to develop the processor board and give examples of errors that were found using the tools. An overview of the processor board firmware will also be covered.
Hyde, David W.↗
Development of Electronic Load Controllers for Free-Piston Stirling Convertors Aided by Stirling Simulation Model
The free-piston Stirling convertor end-to-end modeling effort at the NASA Glenn Research Center has produced a software-based test bed in which free-piston Stirling convertors can be simulated and evaluated. The simulation model includes all the components of the convertor: the Stirling cycle engine, heat source, linear alternator, controller, and load. So far, it has been used in evaluating the performance of electronic controller designs. Three different controller design concepts were simulated using the model: 1) Controllers with parasitic direct current loading. 2) Controllers with parasitic alternating current loading. 3) Controllers that maintain a reference current. The free-piston Stirling convertor is an electromechanical device that operates at resonance. It is the function of the electronic load controller to ensure that the electrical load seen by the machine is always great enough to keep the amplitude of the piston and alternator oscillation at the rated value. This is done by regulating the load on the output bus. The controller monitors the instantaneous voltage, regulating it by switching loads called parasitic loads onto the bus whenever the bus voltage is too high and removing them whenever the voltage is too low. In the first type of controller, the monitor-ing and switching are done on the direct-current (dc) bus. In the second type, the alternating current bus is used. The model allows designers to test a controller concept before investing time in hardware. The simulation code used to develop the model also offers detailed models of digital and analog electronic components so that the resulting designs are realistic enough to translate directly into hardware circuits.
Regan, Timothy F.↗
Optimal Topology and Experimental Evaluation of Piezoelectric Materials for Actively Shunted General Electric Polymer Matrix Fiber Composite Blades
NASA Glenn Research Center, in collaboration with GE Aviation, has begun the development of a smart adaptive structure system with piezoelectric (PE) transducers to improve composite fan blade damping at resonances. Traditional resonant damping approaches may not be realistic for rotating frame applications such as engine blades. The limited space in which the blades reside in the engine makes it impossible to accommodate the circuit size required to implement passive resonant damping. Thus, a novel digital shunt scheme has been developed to replace the conventional electric passive shunt circuits. The digital shunt dissipates strain energy through the load resistor on a power amplifier. General Electric (GE) designed and fabricated a variety of polymer matrix fiber composite (PMFC) test specimens. Investigating the optimal topology of PE sensors and actuators for each test specimen has revealed the best PE transducer location for each target mode. Also a variety of flexible patches, which can conform to the blade surface, have been tested to identify the best performing PE patch. The active damping control achieved significant performance at target modes. This work has been highlighted by successful spin testing up to 5000 rpm of subscale GEnx composite blades in Glenn s Dynamic Spin Rig.
Choi, Benjamin B.↗