Maximum-likelihood data decoder
Digital convolutional decoder circuit for data communication receiver employs Viterbi decoding algorithm to quickly and efficiently decode data on basis of "maximum likelihood" computations.
Alberda, M. E.↗
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Quick-look decoding schemes for DSN convolutional codes
Decoding schemes are proposed for the tracking systems of the galileo project. Quick look decoding schemes requiring only shift registers are given for the DSN (7, 1/2) and (7, 1/3) convolutional codes. These schemes are used when the communication channel is error free. The schemes decode the data, symbol errors, and the lack of node syncronization.
Greenhall, C. A.↗
Minimax decoding of cyclic block codes
A minimax decoding algorithm utilizing soft bit detection of an (n,k) cyclic block code is described which will permit the correction of up to n-k bit errors interspersed at random locations throughout the block. The decoding solution consists of: (1) identifying the ordered soft bit set and, (2) finding the minimum order solution to the resulting syndrome equations where the nonzero error vector components are constrained to be a subset of the soft bit set. An efficient implementation of the decoding operation is described. In essence, this algorithm focuses the correction capability of the code on those bit positions which have the lowest a posteriori probabilities of correct detection.
Greene, E. P.↗
Erasure decoding in burst-error channels
A proven means of communicating reliably in a burst-error channel is the code interleaving scheme. Code symbols from a number of component codes are interleaved before being sent through the channel. This method effectively distributes the error detection and correction burden among the component codes and makes errors occurring in a codeword from each component code more or less independent. Erasure decoding techniques allow further refinement on the code interleaving concept. Their application leads to improved overall code performance when the symbol depth of the lead code is shallow compared to the average error-burst length of the channel. Theoretical formulations derived for predicting the performance of separate decoding and erasure decoding schemes are valuable in providing reasonably good estimates on redundancy requirements of the component codes.
Leung, K. S.↗
PPM demodulation for Reed-Solomon decoding for the optical space channel
The use of Reed-Solomon (RS) block codes over the pulse position modulated (PPM) frames to obtain the largest degree of error correction is considered. Since RS codes can correct both symbol errors and symbol erasures, a question arises as to the best way to demodulate the PPM laser fields in order to generate the input symbols for the RS decoder. The method selected for demodulating (converting the received laser field to digital symbols) defines the erasure and transmitted symbols of the laser link, and therefore determines the work error probabilities of the system. Several demodulating schemes are considered, and the effect of each on RS decoding performance computed. This computation was carried out for various optical receiver models. It is shown that simple threshold decisioning of pulse slots produces performance that degrades as the background noise increases. This is caused by the generation of too many erasures for the RS decoder to handle. A decision scheme, delta-max demodulation which offers improvement over threshold decisioning by redefining the generation of an erasure is proposed.
Divsalar, D.↗
Simplified Syndrome Decoding of (n, 1) Convolutional Codes
A new syndrome decoding algorithm for the (n, 1) convolutional codes (CC) that is different and simpler than the previous syndrome decoding algorithm of Schalkwijk and Vinck is presented. The new algorithm uses the general solution of the polynomial linear Diophantine equation for the error polynomial vector E(D). This set of Diophantine solutions is a coset of the CC space. A recursive or Viterbi-like algorithm is developed to find the minimum weight error vector cirumflex E(D) in this error coset. An example illustrating the new decoding algorithm is given for the binary nonsymmetric (2,1)CC.
I. S. Reed↗
New Syndrome Decoding Techniques for the (n, K) Convolutional Codes
This paper presents a new syndrome decoding algorithm for the (n,k) convolutional codes (CC) which differs completely from an earlier syndrome decoding algorithm of Schalkwijk and Vinck. The new algorithm is based on the general solution of the syndrome equation, a linear Diophantine equation for the error polynomial vector E(D). The set of Diophantine solutions is a coset of the CC. In this error coset a recursive, Viterbi-like algorithm is developed to find the minimum weight error vector (circumflex)E(D). An example, illustrating the new decoding algorithm, is given for the binary nonsystemmatic (3,1)CC.
Reed, I. S.↗
Real-Time Reed-Solomon Decoder
RS decoder uses dedicated hardware and data pipelining for high-speed operation. Parallel processing techniques provide equivalent of over one billion operations per second at one step in decoding. Decoder finds commercial application in data encoding/decoding, telemetry, and radio communications.
Lahmeyer, C. R.↗
A Systolic VLSI Design of a Pipeline Reed-solomon Decoder
A pipeline structure of a transform decoder similar to a systolic array was developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new decoder is regular and simple, and naturally suitable for VLSI implementation.
Shao, H. M.↗
Fast decoding techniques for extended single-and-double-error-correcting Reed Solomon codes
A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. For example, some 256K-bit dynamic random access memories are organized as 32K x 8 bit-bytes. Byte-oriented codes such as Reed Solomon (RS) codes provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. Some special high speed decoding techniques for extended single and double error correcting RS codes. These techniques are designed to find the error locations and the error values directly from the syndrome without having to form the error locator polynomial and solve for its roots.
Costello, D. J., Jr.↗
Fast decoding of a d(min) = 6 RS code
A method for high speed decoding a d sub min = 6 Reed-Solomon (RS) code is presented. Properties of the two byte error correcting and three byte error detecting RS code are discussed. Decoding using a quadratic equation is shown. Theorems and concomitant proofs are included to substantiate this decoding method.
Deng, H.↗
New syndrome decoding techniques for the (n, k) convolutional codes
This paper presents a new syndrome decoding algorithm for the (n, k) convolutional codes (CC) which differs completely from an earlier syndrome decoding algorithm of Schalkwijk and Vinck. The new algorithm is based on the general solution of the syndrome equation, a linear Diophantine equation for the error polynomial vector E(D). The set of Diophantine solutions is a coset of the CC. In this error coset a recursive, Viterbi-like algorithm is developed to find the minimum weight error vector (circumflex)E(D). An example, illustrating the new decoding algorithm, is given for the binary nonsystemmatic (3, 1)CC. Previously announced in STAR as N83-34964
Reed, I. S.↗
Fast VLSI Viterbi Decoder
Fast Viterbi decoder with fully parallel, pipeline architecture implemented on two VLSI NMOS chips. Decoder used with constraint-length-7, rate-1/2, convolutional error-correcting code widely used by NASA for deepspace telemetry data. With this (7,1/2) code, bit stream contains 2 bits per original data bit, and information about 1 data bit distributed over 7 pairs of bits. Design principles of decoder also applicable to Viterbi codes of other lengths and rates.
Wang, C. C.↗
Sequential Syndrome Decoding of Convolutional Codes
The algebraic structure of convolutional codes are reviewed and sequential syndrome decoding is applied to those codes. These concepts are then used to realize by example actual sequential decoding, using the stack algorithm. The Fano metric for use in sequential decoding is modified so that it can be utilized to sequentially find the minimum weight error sequence.
Reed, I. S.↗
A software simulation study of a (255,223) Reed-Solomon encoder-decoder
A set of software programs which simulates a (255,223) Reed-Solomon encoder/decoder pair is described. The transform decoder algorithm uses a modified Euclid algorithm, and closely follows the pipeline architecture proposed for the hardware decoder. Uncorrectable error patterns are detected by a simple test, and the inverse transform is computed by a finite field FFT. Numerical examples of the decoder operation are given for some test codewords, with and without errors. The use of the software package is briefly described.
Pollara, F.↗
A VLSI design of a pipeline Reed-Solomon decoder
A pipeline structure of a transform decoder similar to a systolic array was developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new decoder is regular and simple, and naturally suitable for VLSI implementation.
Shao, H. M.↗
A VLSI Reed-Solomon decoder architecture for concatenate-coded space and spread spectrum communications
In this paper, a VLSI Reed-Solomon (RS) decoder architecture for concatenate-coded space and spread spectrum communications, is presented. The known decoding procedures for RS codes are exploited and modified to obtain a repetitive and recursive decoding technique which is suitable for VLSI implementation and pipeline processing.
Liu, K. Y.↗
A single chip VLSI Reed-Solomon decoder
A new VLSI design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous design is replaced by a time domain algorithm. A new architecture that implements such an algorithm permits efficient pipeline processing with minimum circuitry. A systolic array is also developed to perform erasure corrections in the new design. A modified form of Euclid's algorithm is implemented by a new architecture that maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and a significant reduction in silicon area, therefore making it possible to build a pipeline (31,15)RS decoder on a single VLSI chip.
Shao, H. M.↗