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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
NASA NTRS2016

Detector Control and Data Acquisition for the Wide-Field Infrared Survey Telescope (WFIRST) with a Custom ASIC

The Wide-Field Infrared Survey Telescope (WFIRST) will have the largest near-IR focal plane ever flown by NASA, a total of 18 4K x 4K devices. The project has adopted a system-level approach to detector control and data acquisition where 1) control and processing intelligence is pushed into components closer to the detector to maximize signal integrity, 2) functions are performed at the highest allowable temperatures, and 3) the electronics are designed to ensure that the intrinsic detector noise is the limiting factor for system performance. For WFIRST, the detector arrays operate at 90 to 100 K, the detector control and data acquisition functions are performed by a custom ASIC at 150 to 180 K, and the main data processing electronics are at the ambient temperature of the spacecraft, notionally approx.300 K. The new ASIC is the main interface between the cryogenic detectors and the warm instrument electronics. Its single-chip design provides basic clocking for most types of hybrid detectors with CMOS ROICs. It includes a flexible but simple-to-program sequencer, with the option of microprocessor control for more elaborate readout schemes that may be data-dependent. All analog biases, digital clocks, and analog-to-digital conversion functions are incorporated and are connected to the nearby detectors with a short cable that can provide thermal isolation. The interface to the warm electronics is simple and robust through multiple LVDS channels. It also includes features that support parallel operation of multiple ASICs to control detectors that may have more capability or requirements than can be supported by a single chip.

data acquisition↗
NASA NTRS2016

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 C

We have reported SiC integrated circuits (IC's) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 C [1, 2]. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 C [3]. However, this thermal ramp was not ended until a peak temperature of 880 C (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology. Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 C. In one test, the temperature was ramped and then held at 727 C, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 C before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 C (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 C.

JFET↗
DOE OSTI2013

Actuation of atomic force microscopy microcantilevers using contact acoustic nonlinearities

A new method of actuating atomic force microscopy (AFM) cantilevers is proposed in which a high frequency (>5 MHz) wave modulated by a lower frequency (∼300 kHz) wave passes through a contact acoustic nonlinearity at the contact interface between the actuator and the cantilever chip. The nonlinearity converts the high frequency, modulated signal to a low frequency drive signal suitable for actuation of tapping-mode AFM probes. The higher harmonic content of this signal is filtered out mechanically by the cantilever transfer function, providing for clean output. A custom probe holder was designed and constructed using rapid prototyping technologies and off-the-shelf components and was interfaced with an Asylum Research MFP-3D AFM, which was then used to evaluate the performance characteristics with respect to standard hardware and linear actuation techniques. Using a carrier frequency of 14.19 MHz, it was observed that the cantilever output was cleaner with this actuation technique and added no significant noise to the system. This setup, without any optimization, was determined to have an actuation bandwidth on the order of 10 MHz, suitable for high speed imaging applications. Using this method, an image was taken that demonstrates the viability of the technique and is compared favorably to images taken with a standard AFM setup.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS2016

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 Degrees Centigrade

We have reported SiC integrated circuits (ICs) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 degrees Centigrade. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 degrees Centigrade. However, this thermal ramp was not ended until a peak temperature of 880 degrees Centigrade (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology.Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 degrees Centigrade. In one test, the temperature was ramped and then held at 727 degrees Centigrade, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 degrees Centigrade before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 degrees Centigrade (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 degrees Centigrade.

Silicon Carbide↗
DOE OSTI2026

Image processing pipeline for AI-driven nanoparticle megalibrary characterization

Recent innovations have made it possible to produce megalibraries, millions of structurally and compositionally distinct nanoparticles on a chip. These megalibraries yield vast volumes of data that are impossible to analyze manually, necessitating the development of automated tools. In previous work, we created a binary classification machine learning model to select quality nanoparticle images for downstream analysis. In this work, we show that adding a custom image processing step before training can produce significantly higher-performing models in a fraction of the time and make them more robust to different image noise levels and microscope acquisition settings. The image processing pipeline proposed here effectively cleans raw nanoparticle images, enhances key features, and allows us to use much lower resolution images and simpler neural network model architectures. These features result in higher performance and significant cost savings. Experiments demonstrate superior performance relative to baseline, including an 18.2% improvement in recall and a 13.1% increase in accuracy. Given the high cost of downstream analysis, it is critical to minimize false positives, and our best-performing model reaches a precision of 95.9% and a weighted F-score of 95.1% on an unseen test set. Additionally, model training time is reduced from hours to less than a minute. We also show that, using this custom image processing pipeline, model performance is significantly improved at lower pixel resolutions compared to downsizing alone. We expect that adopting this pipeline for AI-driven automated nanoparticle characterization will allow researchers to rapidly and accurately analyze much greater volumes of data, thereby accelerating materials discovery.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
NASA NTRS1994

Clementine RRELAX SRAM Particle Spectrometer

The Clementine RRELAX radiation monitor chip consists of a p-FET total dose monitor and a 4-kbit SRAM particle spectrometer. Eight of these chips were included in the RRELAX and used to detect the passage of the Clementine (S/C) and the innerstage adapter (ISA) through the earth's radiation belts and the 21-Feb 1994 solar flare. This is the first space flight for this 1.2 micron rad-soft custom CMOS radiation monitor. This paper emphasizes results from the SRAM particle detector which showed that it a) has a detection range of five orders of magnitude relative to the 21-Feb solar flare, b) is not affected by electrons, and c) detected microflares occurring with a 26.5 day period.

Clementine↗
NASA NTRS1985

Programable Driver for Voltage-Controlled Oscillators

Electronically programable read-only memory (EPROM) and digital-to-analog converter provide customized time-varying voltage for frequency modulation. Voltage used to modulate IMPATT oscillator that serves as microwave pump for solid-state maser in low-noise amplifier. EPROM simple to tailor voltage waveform to suit characteristics of given maser. Digital information for waveform programed into EPROM chip; digital-to-analog converter reads information and produces corresponding analog wave. Principle readily adapted to other applications.

Fowler, L. E.↗
DOE OSTI2025

A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems

Domain-specific systems improve the performance of a specific set of applications compared to general-purpose processing systems by deploying custom hardware accelerators. These hardware accelerators are generated using high-level synthesis (HLS) tools. The HLS tools enable a comprehensive design space exploration to optimize the compute performance of the generated accelerators. However, they often ignore the challenges of implementing the accelerators in a system-on-chip, particularly how the accelerators access memory. Our work introduces a buffering system design that improves accelerators' memory accesses by intelligently employing burst transactions to prefetch useful data from external memory to on-chip local buffers. Our design is dynamic, parametric, and transparent to the accelerators generated by HLS tools. We derive the buffering system parameters using appropriate compiler-based analysis passes and memory channel latency constraints. The proposed buffering system design results in, on average, 8.8x performance improvements while lowering memory channel utilization on average by 53.2% for a set of PolyBench kernels.

Limaye, Ankur M. (ORCID:0000000194062584)↗
NASA NTRS1992

NASA SERC digital correlator projects

Interest in custom digital correlator processors is growing, in both the radio astronomy and earth sensing communities, as scientists realize that VLSI technology is available to them. This paper presents three digital correlator projects currently underway at the NASA SERC for VLSI Systems Design. The projects are as follows: a 60MHz chip for the ESTAR satellite; a 100MHz, 1024 channel autocorrelator; and a 64 MHz, VLSI system consisting of 8 32- channel complex crosscorrelators including phase rotators.

Canaris, John↗
NASA NTRS1990

Custom CMOS Reed Solomon coder for the Hubble Space Telescope

A VLSI coder is presented that can function either as an encoder or decoder for Reed-Solomon codes. VLSI is one approach to implementing high-performance Reed-Solomon decoders. There are three VLSI technologies that could be used: gate arrays, standard cells, and full custom. The first two approaches are relatively easy to implement, but are limited in both performance and density. Full-custom VLSI is used to achieve both circuit density and speed, and allows control of the amount of interconnect. Speed, which is a function of capacitance, which is a function of interconnect, is an important parameter in high-performance VLSI. A single 8.2 mm x 8.4 mm, 200,000 transistor CMOS chip implementation of the Reed-Solomon code required by the Hubble Space Telescope is reported. The chip features a 10-MHz sustained byte rate independent of error pattern. The 1.6-micron CMOS integrated circuit has complete decoder and encoder functions and uses a single data/system clock. Block lengths up to 255 bytes and shortened codes are supported with no external buffering. Erasure corrections and random error corrections are supported with programmable correction of up to 10 symbol errors. Correction time is independent of error pattern and the number of errors in the incoming message.

Whitaker, S.↗
NASA NTRS1992

The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element

A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.

Deyong, Mark R.↗
DOE OSTI2014

Dependence of the colored frequency noise in spin torque oscillators on current and magnetic field

The nano-scale spin torque oscillator (STO) is a compelling device for on-chip, highly tunable microwave frequency signal generation. Currently, one of the most important challenges for the STO is to increase its longer-time frequency stability by decreasing the 1/f frequency noise, but its high level makes even its measurement impossible using the phase noise mode of spectrum analyzers. Here, we present a custom made time-domain measurement system with 150 MHz measurement bandwidth making possible the investigation of the variation of the 1/f as well as the white frequency noise in a STO over a large set of operating points covering 18–25 GHz. The 1/f level is found to be highly dependent on the oscillation amplitude-frequency non-linearity and the vicinity of unexcited oscillation modes. These findings elucidate the need for a quantitative theoretical treatment of the low-frequency, colored frequency noise in STOs. Based on the results, we suggest that the 1/f frequency noise possibly can be decreased by improving the microstructural quality of the metallic thin films.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2022

The Readout Electronics of the Mu2e Electromagnetic Calorimeter

The Mu2e electromagnetic calorimeter has been designed to measure ~100 MeV electrons with energy resolution σE/E <10%, time resolution σt < 500ps and position resolution σx < 1cm. The detector is composed of 1348 un-doped CsI crystals coupled to two large area Silicon Photomultipliers (SiPMs). Each SiPM is connected to a Front End Electronics (FEE) chip which hosts the shaping amplifier and the high voltage linear regulator. A group of 20 FEE is controlled by one Mezzanine Board (MB) which transmits the amplified signals to one Digitizer ReAdout Controller board (DiRAC). The DiRAC samples the waveforms at 200 MHz with 12-bit ADCs, packs the data according to the Mu2e custom format and transmits them to the event builder through an optical transceiver. To limit the number of pass-through connectors and the length of the cables, the readout and digitization electronics is located inside the detector cryostat and close to the interaction target. The boards will have to sustain a neutron fluence of about 5x10 10 n/cm 2 @ 1 MeVeq (Si)/y and a Total Ionizing Dose of about 12 krad, while working into a 1T magnetic field and a vacuum of 10 (-4) Torr. This harsh operational environment has made the electronics design challenging and required an extended campaign of tests to select and qualify the employed electronic components. In this paper we report on the board architecture and design, on the qualification of the prototypes, as well as on the results of the first vertical slice test of the Mu2e calorimeter.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

The QICK (Quantum Instrumentation Control Kit): Readout and control for qubits and detectors

We introduce a Xilinx RF System-on-Chip (RFSoC)-based qubit controller (called the Quantum Instrumentation Control Kit, or QICK for short), which supports the direct synthesis of control pulses with carrier frequencies of up to 6 GHz. The QICK can control multiple qubits or other quantum devices. The QICK consists of a digital board hosting an RFSoC field-programmable gate array, custom firmware, and software and an optional companion custom-designed analog front-end board. We characterize the analog performance of the system as well as its digital latency, important for quantum error correction and feedback protocols. We benchmark the controller by performing standard characterizations of a transmon qubit. We achieve an average gate fidelity of ℱ avg =99.93%. All of the schematics, firmware, and software are open-source.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2015

Holographic patterning of high-performance on-chip 3D lithium-ion microbatteries

Significance Microscale batteries can deliver energy at the actual point of energy usage, providing capabilities for miniaturizing electronic devices and enhancing their performance. Here, we demonstrate a high-performance microbattery suitable for large-scale on-chip integration with both microelectromechanical and complementary metal-oxide–semiconductor (CMOS) devices. Enabled by a 3D holographic patterning technique, the battery possesses well-defined, periodically mesostructured porous electrodes. Such battery architectures offer both high energy and high power, and the 3D holographic patterning technique offers exceptional control of the electrode’s structural parameters, enabling customized energy and power for specific applications.

25 ENERGY STORAGE↗
DOE OSTI2023

Multiport High-pressure Fluid Cell (MHPFC) for Photon and Electron Beams

A multiport high-pressure fluid cell was developed based on an engineered thin film membrane solution with a reinforced frame of boron-doped silicon, optimized to withstand better pressure with an increase of 17.6% in average burst pressure over similar membranes without frame. The novel cells (patent pending) have 8 microfluidic ports, two intra-cavity electrodes and two pressure sensors on a 8 mm x 8 mm Si chip. The prototypes resisted up to 60 bar with 50-nm-thick silicon nitride membranes of size 70 nm x 70 nm. The cells can be used for testing reactions in fluids in medium-high pressure (up to 300 bar) using X-rays (primary application), electron beams, IR or visible light. Improvements in the pressure sensing setup and customization for applications are supposed to follow.

36 MATERIALS SCIENCE↗
DOE OSTI2016

Compact, single mode, frequency stabilized laser spectroscopy sources for isotope analysis

We will discuss here ultra-stable narrow line-width Hybrid External Cavity Lasers (HECL) of visible spectrum. The customer requires ~ 2 MHz linewidth / stability (2.7 fm). It is our goal to design the most stable possible ECL, and then enhance its long-term stability by disciplining it to an atomic wavelength reference. Protection against long-term drift can be provided by calibrating HECL wavelength to a hollow-cathode lamp (HCL) standard using the optogalvanic effect to adjust the HECL set-point. Here we report the short-term stability of the HECL alone, i.e., without the discipline of an atomic wavelength reference. For this purpose, we have studied HECLs operating at 405 nm and at 638 nm. We will interpret their performance in terms of the customer’s need for 600 – 700 nm narrow-linewidth spectroscopy. We selected to perform the portion of the work at 405 nm since the sensitivity to cavity stability is ~2x compared with operating in the 600 – 700 nm wavelength range. Further, we will show excellent wavelength stability over time at 638 nm. The two main ECL components are the semiconductor laser chip, including a high reflectivity (HR) mirror, and a volume Bragg grating (VBG) that provides output coupling. Between them is collimating optics. The theoretical analysis and experimental data suggest that control of ECL wavelength in the femtometer wavelength range can be achieved over short-term time scales by carefully controlling both the temperature and very high current stability. From the results presented here temperature control of the laser to 0.001° C along with current stability of 0.001 mA will be needed in a sensor instrument. Finally, we show a path to achieve 2 MHz short-term stability at 600 to 700 nm.

07 ISOTOPE AND RADIATION SOURCES↗
DOE OSTI2024

Droplet bioprinting of acellular and cell-laden structures at high-resolutions

Advances in digital light projection(DLP) based (bio) printers have made printing of intricate structures at high resolution possible using a wide range of photosensitive bioinks. A typical setup of a DLP bioprinter includes a vat or reservoir filled with liquid bioink, which presents challenges in terms of cost associated with bioink synthesis, high waste, and gravity-induced cell settling, contaminations, or variation in bioink viscosity during the printing process. Here, we report a vat-free, low-volume, waste-free droplet bioprinting method capable of rapidly printing 3D soft structures at high resolution using model bioinks and model cells. A multiphase many-body dissipative particle dynamics model was developed to simulate the dynamic process of droplet-based DLP printing and elucidate the roles of surface wettability and bioink viscosity. Process variables such as light intensity, photo-initiator concentration, and bioink formulations were optimized to print 3D soft structures (∼0.4–3 kPa) with a typical layer thickness of 50 µm, an XY resolution of 38 ± 1.5 μm and Z resolution of 237 ± 5.4 µm. To demonstrate its versatility, droplet bioprinting was used to print a range of acellular 3D structures such as a lattice cube, a Mayan pyramid, a heart-shaped structure, and a microfluidic chip with endothelialized channels. Droplet bioprinting, performed using model C3H/10T1/2 cells, exhibited high viability (90%) and cell spreading. Additionally, microfluidic devices with internal channel networks lined with endothelial cells showed robust monolayer formation while osteoblast-laden constructs showed mineral deposition upon osteogenic induction. Overall, droplet bioprinting could be a low-cost, no-waste, easy-to-use, method to make customized bioprinted constructs for a range of biomedical applications.

DLP↗