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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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NASA computer program automatically analyzes power-system networks under faulted conditions. Program is general enough to calculate single-line to ground faults and three-phase-to-ground faults. Several novel programing techniques automate analysis while reducing computing time and storage requirements. Program is written in FORTRAN IV for batch execution.
Plate motion data along the Southeast, Southwest, and Central Indian ridges have been reduced to 67 spreading rates, 38 transform fault azimuths, and 135 earthquake slip vectors in order to study the current motion between the Australian, Antarctic, and African plates and to investigate whether this plate circuit obeys closure. Magnetic profiles are modeled to determine rates consistently over a 3-m.y. time-averaging interval, and the new rates are shown to differ from published rates by as much as 5 mm/yr. The results indicate that Indian Ocean plate circuit nonclosure and the deformation that it suggests are much smaller than previously supposed, and support a model in which the significant deformation occurs in a diffuse plate boundary along the equatorial Indian Ocean between the Central Indian Ridge and the Sumatra Trench.
This paper overviews Evolvable Hardware (EHW) technology, examining its potential for enhancing survivability and flexibility of future space systems. EHW refers to selfconfiguration of electronic hardware by evolutionary/genetic search mechanisms. Evolvable Hardware can maintain existing functionality in the presence of faults and degradations due to aging, temperature and radiation. It can also configure itself for new functionality when required for mission changes or encountered opportunities. The paper illustrates hardware evolution in silicon using a JPL-designed programmable device reconfigurable at transistor level as the platform and a genetic algorithm running on a DSP as the reconfiguration mechanism. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The experiments demonstrate functional recovery from faults as well as from degradation at extreme temperatures indicating the possibility of expanding the operational range of extreme electronics through evolved circuit solutions.
Logic fault tolerant digital computer design for increased reliability, discussing logic circuits and protective redundancy
Statistical models developed to define the most likely sources of photovoltaic (PV) array failures and the optimum method of allowing for the defects in order to achieve a 20 yr lifetime with acceptable performance degradation are summarized. Significant parameters were the cost of energy, annual power output, initial cost, replacement cost, rate of module replacement, the discount rate, and the plant lifetime. Acceptable degradation allocations were calculated to be 0.0001 cell failures/yr, 0.005 module failures/yr, 0.05 power loss/yr, a 0.01 rate of power loss/yr, and a 25 yr module wear-out length. Circuit redundancy techniques were determined to offset cell failures using fault tolerant designs such as series/parallel and bypass diode arrangements. Screening processes have been devised to eliminate cells that will crack in operation, and multiple electrical contacts at each cell compensate for the cells which escape the screening test and then crack when installed. The 20 yr array lifetime is expected to be achieved in the near-term.
This paper describes the functionality of four application specific integrated circuits (ASICs) developed for the Cassini spacecraft.
The cost of several circuit configurations for large (5MW) array fields were investigated to assess the relative costs of high and low voltage configurations. Three source circuit NOC voltages were evaluated: 400V (ungrounded), 800V (+ or 400V center grounded), and 2000V (+ or - 1000V center grounded). Four source circuit configurations were considered for each of the three NOC voltages. The configurations correspond to source circuit currents of 15, 30, 45, and 60 amperes, respectively. Conceptual layouts for 5MW building blocks for each of the above configurations were developed. The designs were optimized to minimize BOS electrical and structural costs. Only the BOS electrical costs were evaluated. The designs were broken down into the following elements for cost: (1) basic source circuit intermodule wiring, bypass diodes and associated hardware, source circuit to J-Box wiring, etc; (2) J-Box blocking diodes, varistors, heat sinks, and housing; (3) disconnects source circuit disconnects, fuses, and housing; (4) bus cabling J-Box to PCU interface wiring, and trenching; (5) interface bus bar, group disconnects, and fuses; and (6) fault detection shunts, signal wire, electronics, and alarm. It is concluded that high voltage low current circuits are not economical, at higher currents high and low voltage circuit costs approach each other, high voltage circuits are not likely to offer near term advantage, and development work/manufacturer stimulation is needed to develop low cost high voltage hardware.
Pyrotechnic systems often fall into a unique category in that inadvertent activation of these systems resulting from a fault and/or lack of safe margins can lead directly to loss of crew. For example, untimely activation of pyrotechnics used for a flight termination system could override an abort capability. Over the years, NASA and the military have learned lessons about safe pyrotechnic circuit design and test, many of which are codified. However, with NASA’s recent efforts to move toward a development model than leans more heavily on Commercial Partners these requirements have not always been directly levied on projects and in some cases been misinterpreted. This bulletin describes key safety features of pyrotechnic firing circuit design and provides rationale for inclusion of each feature.
Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.
Emerging technology is enabling the design community to consistently expand the amount of functionality that can be implemented within Integrated Circuits (ICs). As the number of gates placed within an FPGA increases, the complexity of the design can grow exponentially. Consequently, the ability to create reliable circuits has become an incredibly difficult task. In order to ease the complexity of design completion, the commercial design community has developed a very rigid (but effective) design methodology based on synchronous circuit techniques. In order to create faster, smaller and lower power circuits, transistor geometries and core voltages have decreased. In environments that contain ionizing energy, such a combination will increase the probability of Single Event Upsets (SEUs) and will consequently affect the state space of a circuit. In order to combat the effects of radiation, the aerospace community has developed several "Hardened by Design" (fault tolerant) design schemes. This paper will address design mitigation schemes targeted for SRAM Based FPGA CMOS devices. Because some mitigation schemes may be over zealous (too much power, area, complexity, etc.. . .), the designer should be conscious that system requirements can ease the amount of mitigation necessary for acceptable operation. Therefore, various degrees of Fault Tolerance will be demonstrated along with an analysis of its effectiveness.
PLLs for clock generation are essential for modern circuits, to generate specialized frequencies for many interfaces and high frequencies for chip internal operation. These circuits depend on analog circuits and careful tailoring for each new process, and making them fault tolerant is an incompletely solved problem. Until now, all digital PLLs have been restricted to sampled data DSP techniques and not available for the highest frequency baseband applications. This paper presents the design and preliminary evaluation of an all-digital baseband technique built entirely with an easily portable 10-cell digital library. The library is also described, as it aids in research and low volume design porting to new processes. The advantages of the digital approach are the wide variety of techniques available to give varying degrees of fault tolerance, and the simplicity of porting the design to new processes, even to exotic processes that may not have analog capability. The only tuning parameter is digital gate delay. An all-digital approach presents unique problems and standard analog loop stability design criteria cannot be directly used. Because of the quantization of frequency, there is effectively infinite gain for very small loop error feedback. The numerically controlled oscillator (NCO) based on a tapped delay line cannot be reliably updated while a pulse is active in the delay line, and ordinarily does not have enough frequency resolution for a low-jitter output.
PLLs for clock generation are essential for modern circuits, to generate specialized frequencies for many interfaces and high frequencies for chip internal operation. These circuits depend on analog circuits and careful tailoring for each new process, and making them fault tolerant is an incompletely solved problem. Until now, all digital PLLs have been restricted to sampled data DSP techniques and not available for the highest frequency baseband applications. This paper presents the design and preliminary evaluation of an all-digital baseband technique built entirely with an easily portable 10-cell digital library. The library is also described, as it aids in research and low volume design porting to new processes. The advantages of the digital approach are the wide variety of techniques available to give varying degrees of fault tolerance, and the simplicity of porting the design to new processes, even to exotic processes that may not have analog capability. The only tuning parameter is digital gate delay. An all-digital approach presents unique problems and standard analog loop stability design criteria cannot be directly used. Because of the quantization of frequency, there is effectively infinite gain for very small loop error feedback. The numerically controlled oscillator (NCO) based on a tapped delay line cannot be reliably updated while a pulse is active in the delay line, and ordinarily does not have enough frequency resolution for a low-jitter output.
The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.
More reliable computers could be assembled by connecting four proposed VSLI "building block" circuits with built-in error detection to standard microprocessors and memory devices to form self checking computer module. Each building block detects its own malfunctions and single bit errors found in memory.
Arithmetic processors hardware logic faults diagnosis while in operation, using arithmetic error codes and associated checking circuits
Wavelength division multiplexing (WDM) represents an approach for expanding the communication capacity and for implementing special data techniques in a fiber optics system. This technology is implemented by adding optical sources of different wavelengths at optical transmitting locations. The present paper is concerned with some of the current efforts in WDM. WDM applications are related to long haul communications, local area data networks, spacecraft and aircraft data systems, fault tolerant computer networks, special sensor devices, high speed data processors, closed circuit and cable television, and submarine cable systems. Attention is given to the current state of wavelength division multiplexing applications, the availability and status of WDM components semiconductor lasers/transmitters, availability and status of fiber optic detectors/receivers, optical fibers/cables/connectors/taps/star couplers, wavelength multiplexers/demultiplexers, and future WDM for local area networks.
A new basic VLSI circuit element is presented that can be used to realize pulse mode asynchronous sequential circuits. A synthesis procedure is developed along with an unconventional state assignment procedure. Level input asynchronous sequential circuits can be realized by converting a regular flow table into a differential mode flow table, thereby allowing the new synthesis technique to be general. The new circuits tolerate 1-1 crossovers. This circuit also provides a means for state sequence detection and real time fault detection.
The Mars Microprobe Mission is the second spacecraft developed as part of the New Millennium Program deep space missions. The objective of the Microprobe Project is to demonstrate the applicability of key technologies for future planetary missions by developing two probes for deployment on Mars. The probes are designed with a single stage entry, descent, and landing system and impact the Martian surface at speeds of approximately 200 meters per second. The microprobes are composed of two main sections, a forebody section that penetrates to a depth below the Martian surface of 0.5 to 2 meters, and an aftbody section that remains on the surface. Each probe system consists of a number of advanced technology components developed specifically for this mission. These include a non-erosive aeroshell for entry into. the atmosphere, a set of low temperature batteries to supply probe power, an advanced microcontroller to execute the mission sequence, collect the science data, and react to possible system fault conditions, a telecommunications subsystem implemented on a set of custom integrated circuits, and instruments designed to provide science measurements from above and below the Martian surface. All of the electronic components have been designed and fabricated to withstand the severe impact shock environment and to operate correctly at predicted temperatures below -100 C.