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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Smart Pixels: In-pixel AI for on-sensor data filtering

We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 µm\textsuperscript{2} in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e\textsuperscript{-} and a total dispersion of $\sim$100e\textsuperscript{-} The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4\% – 75.4\% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm\textsuperscript{2} staying within the experimental constraints.

Parpillon, Benjamin↗
NASA NTRS1991

High resolution decoding of Multi-Anode Microchannel Array detectors

The Multi-Anode Microchannel Array (MAMA) is a photon counting detector which utilizes a photocathode for photon to electron conversion, a microchannel plate (MCP) for signal amplification and a proximity focused anode array for position sensitivity. The detector electronics decode the position of an event through coincidence discrimination. The decoding algorithm which associates a given event with the appropriate pixel is determined by the geometry of the array. A new algorithm incorporated into a CMOS Application Specific Integrated Circuit (ASIC) decoder which improves the pixel spatial resolution is described. The new algorithm does not degrade the detector throughput and does not require any modifications to the detector tube. The standard MAMA detector has a pixel size of 25 x 25 square microns, but with the new decoder circuit the pixel size is reduced to 12.5 x 12.5 square microns. We have built the first set of decode electronics utilizing the new ASIC chips and report here on the first imaging tests of this system.

Kasle, David B.↗
NASA NTRS2006

Product Reliability Trends, Derating Considerations and Failure Mechanisms with Scaled CMOS

As microelectronics is scaled into the deep sub-micron regime, space and aerospace users of advanced technology CMOS are reassessing how scaling effects impact long-term product reliability. The effects of electromigration (EM), time-dependent-dielectric-breakdown (TDDB) and hot carrier degradation (HCI and NBTI) wearout mechanisms on scaled technologies and product reliability are investigated, accelerated stress testing across several technology nodes is performed, and FA is conducted to confirm the failure mechanism(s).

CMOS integrated circuits↗
NASA NTRS2005

Impact of Device Scaling on Deep Sub-micron Transistor Reliability: A Study of Reliability Trends using SRAM

As microelectronics are scaled in to the deep sub-micron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes step-stress techniques to evaluate memory technologies (0.25mum, 0.15mum, and 0.13mum) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data.

CMOS integrated circuits↗
NASA NTRS2004

Parallel-Processing Equalizers for Multi-Gbps Communications

Architectures have been proposed for the design of frequency-domain least-mean-square complex equalizers that would be integral parts of parallel- processing digital receivers of multi-gigahertz radio signals and other quadrature-phase-shift-keying (QPSK) or 16-quadrature-amplitude-modulation (16-QAM) of data signals at rates of multiple gigabits per second. Equalizers as used here denotes receiver subsystems that compensate for distortions in the phase and frequency responses of the broad-band radio-frequency channels typically used to convey such signals. The proposed architectures are suitable for realization in very-large-scale integrated (VLSI) circuitry and, in particular, complementary metal oxide semiconductor (CMOS) application- specific integrated circuits (ASICs) operating at frequencies lower than modulation symbol rates. A digital receiver of the type to which the proposed architecture applies (see Figure 1) would include an analog-to-digital converter (A/D) operating at a rate, fs, of 4 samples per symbol period. To obtain the high speed necessary for sampling, the A/D and a 1:16 demultiplexer immediately following it would be constructed as GaAs integrated circuits. The parallel-processing circuitry downstream of the demultiplexer, including a demodulator followed by an equalizer, would operate at a rate of only fs/16 (in other words, at 1/4 of the symbol rate). The output from the equalizer would be four parallel streams of in-phase (I) and quadrature (Q) samples.

Gray, Andrew↗
DOE OSTI2024

Smart Pixels: In-pixel AI for on-sensor data filtering

We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 $\mu$m$^2$ in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e$^-$ and a total dispersion of $\sim$100e$^-$ The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4% - 75.4% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm$^2$ staying within the experimental constraints.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1992

Detection of feed-through faults in CMOS storage elements

In testing sequential circuits, internal faults in the storage elements (SE's) are sometimes modeled as stuck-at faults in the combinational circuits surrounding the SE. The detection of some transistor-level faults that cannot be modeled as stuck-at are considered. These feed-through faults cause the cell to become either data-feed-through, which makes the cell combinational, or clock-feed-through, which causes the clock signal or its complement to appear at the output. Under such faults, the cell does not function as a memory element. Here it is shown that such faults may or may not be detected depending on delays involved. Conditions under which race-ahead occurs are identified.

Al-Assadi, Waleed K.↗
NASA NTRS2009

SOI CMOS Imager with Suppression of Cross-Talk

A monolithic silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) image-detecting integrated circuit of the active-pixel-sensor type, now undergoing development, is designed to operate at visible and near-infrared wavelengths and to offer a combination of high quantum efficiency and low diffusion and capacitive cross-talk among pixels. The imager is designed to be especially suitable for astronomical and astrophysical applications. The imager design could also readily be adapted to general scientific, biological, medical, and spectroscopic applications. One of the conditions needed to ensure both high quantum efficiency and low diffusion cross-talk is a relatively high reverse bias potential (between about 20 and about 50 V) on the photodiode in each pixel. Heretofore, a major obstacle to realization of this condition in a monolithic integrated circuit has been posed by the fact that the required high reverse bias on the photodiode is incompatible with metal oxide/semiconductor field-effect transistors (MOSFETs) in the CMOS pixel readout circuitry. In the imager now being developed, the SOI structure is utilized to overcome this obstacle: The handle wafer is retained and the photodiode is formed in the handle wafer. The MOSFETs are formed on the SOI layer, which is separated from the handle wafer by a buried oxide layer. The electrical isolation provided by the buried oxide layer makes it possible to bias the MOSFETs at CMOS-compatible potentials (between 0 and 3 V), while biasing the photodiode at the required higher potential, and enables independent optimization of the sensory and readout portions of the imager.

Pain, Bedabrata↗
NASA NTRS1990

Self arbitrated VLSI asynchronous sequential circuits

A new class of asynchronous sequential circuits is introduced in this paper. The new design procedures are oriented towards producing asynchronous sequential circuits that are implemented with CMOS VLSI and take advantage of pass transistor technology. The first design algorithm utilizes a standard Single Transition Time (STT) state assignment. The second method introduces a new class of self synchronizing asynchronous circuits which eliminates the need for critical race free state assignments. These circuits arbitrate the transition path action by forcing the circuit to sequence through proper unstable states. These methods result in near minimum hardware since only the transition paths associated with state variable changes need to be implemented with pass transistor networks.

Whitaker, S.↗
NASA NTRS1991

Bench-level characterization of a CMOS standard-cell D-latch using alpha-particle sensitive test circuits

A methodology is described for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. Measurements were made on a 1.6-micron n-well CMOS 4-kb test SRAM irradiated with an Am-241 alpha-particle source. A collection depth of 6.09 micron was determined using these results and TRIM computer code. Using this collection depth and SPICE derived critical charge results on the latch design, an LET threshold of 34 MeV sq cm/mg was predicted. Heavy ion tests were then performed on the latch and an LET threshold of 41 MeV sq cm/mg was determined.

Blaes, B. R.↗
NASA NTRS1992

A 1 GHz sample rate, 256-channel, 1-bit quantization, CMOS, digital correlator chip

This paper describes the development of a digital correlator chip with the following features: 1 Giga-sample/second; 256 channels; 1-bit quantization; 32-bit counters providing up to 4 seconds integration time at 1 GHz; and very low power dissipation per channel. The improvements in the performance-to-cost ratio of the digital correlator chip are achieved with a combination of systolic architecture, novel pipelined differential logic circuits, and standard 1.0 micron CMOS process.

Timoc, C.↗
NASA NTRS2010

Optimal and Local Connectivity Between Neuron and Synapse Array in the Quantum Dot/Silicon Brain

This innovation is used to connect between synapse and neuron arrays using nanowire in quantum dot and metal in CMOS (complementary metal oxide semiconductor) technology to enable the density of a brain-like connection in hardware. The hardware implementation combines three technologies: 1. Quantum dot and nanowire-based compact synaptic cell (50x50 sq nm) with inherently low parasitic capacitance (hence, low dynamic power approx.l0(exp -11) watts/synapse), 2. Neuron and learning circuits implemented in 50-nm CMOS technology, to be integrated with quantum dot and nanowire synapse, and 3. 3D stacking approach to achieve the overall numbers of high density O(10(exp 12)) synapses and O(10(exp 8)) neurons in the overall system. In a 1-sq cm of quantum dot layer sitting on a 50-nm CMOS layer, innovators were able to pack a 10(exp 6)-neuron and 10(exp 10)-synapse array; however, the constraint for the connection scheme is that each neuron will receive a non-identical 10(exp 4)-synapse set, including itself, via its efficacy of the connection. This is not a fully connected system where the 100x100 synapse array only has a 100-input data bus and 100-output data bus. Due to the data bus sharing, it poses a great challenge to have a complete connected system, and its constraint within the quantum dot and silicon wafer layer. For an effective connection scheme, there are three conditions to be met: 1. Local connection. 2. The nanowire should be connected locally, not globally from which it helps to maximize the data flow by sharing the same wire space location. 3. Each synapse can have an alternate summation line if needed (this option is doable based on the simple mask creation). The 10(exp 3)x10(exp 3)-neuron array was partitioned into a 10-block, 10(exp 2)x10(exp 3)-neuron array. This building block can be completely mapped within itself (10,000 synapses to a neuron).

Duong, Tuan A.↗
NASA NTRS1981

An advanced, radiation hardened bulk CMOS/LSI technology

An advanced, second generation, bulk, Si-gate CMOS process is described. This process is capable of producing LSI and VLSI parts that are latch-up free and hardened to total dose levels in excess of 2 x 10 to the 5th rad-Si for applications in space and weapons radiation environments. Two memories designed to use this process are also described. Both circuits are 4096-bit, static CMOS RAMs.

Schroeder, J. E.↗
DOE OSTI2024

A 32-Channel Cryo-CMOS ASIC for SNSPD Biasing and Readout with Picosecond

Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specific integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifiers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verified using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.

Fredenburg, Jeff↗
DOE OSTI2024

CMOS photonic integrated source of broadband polarization-entangled photons

We showcase a fully on-chip CMOS-fabricated silicon photonic integrated circuit employing a bidirectionally pumped microring and polarization splitter-rotators tailored for the generation of broadband (>9 THz), high-fidelity (90–98%) polarization-entangled photons. Spanning the optical C+L-band and producing over 116 frequency-bin pairs on a 38.4-GHz-spaced grid, this source is ideal for flex-grid wavelength-multiplexed entanglement distribution in multiuser networks.

42 ENGINEERING↗
DOE OSTI2024

A 32-Channel Cryo-CMOS ASIC for SNSPD Biasing and Readout with Picosecond Timing

Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specifc integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verifed using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.

Fredenburg, Jeff↗