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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

2-Aminoanthracene Crystallization in Its Compatible Polystyrene Block: RAFT Synthesis and Enhanced Charge Retention in Pentacene Transistor Gate Dielectrics

We synthesized polystyrene-block-polyanthrylaminomethylstyrene (PS-b-PAAS) via RAFT reaction and side chain modification where the PAAS block is 50%. By blending 2-aminoanthracene (2AA) with PS-b-PAAS, the co-aggregation behavior of the PAAS block and 2AA within the thin film was observed by optical microscopy (OM) and x-ray diffraction. At 5 and 10 wt% of 2AA within the thin film, OM results showed a clear morphological difference between PS matrix and PS-b-PAAS matrix. Differences in the 2AA excited state lifetime in these matrices were also established using transient absorption spectroscopy (TAS). Blends were used as gate dielectrics in pentacene transistors. We compared characteristic voltage (Vc, an indicator of threshold voltage) before and after charging of PS-b-PAAS blended with unsubstituted PS and both polymers individually blended with 2AA. For blended PS-b-PAAS and PS, as the concentration of PS-b-PAAS increases, the decreased Vc especially with negative charging of the pentacene indicated a larger concentration of charge carriers induced by the dielectric film. The charging experiments also revealed that the unique structure formed by the 2AA/PS-b-PAAS blend significantly affected the charge storage capability of the organic field-effect transistors (OFET). Furthermore, this work demonstrates the novel co-aggregation structure in the dielectrics, and furthermore its impact on charge storage capability in pentacene OFETs.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Visualization of Mesoscopic Conductivity Fluctuations in Amorphous Semiconductor Thin-Film Transistors

Charge transport in amorphous semiconductors is considerably more complicated than the process in crystalline materials due to abundant localized states. In addition to device-scale characterization, spatially resolved measurements are important to unveiling electronic properties. Here, we report gigahertz conductivity mapping in amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors by microwave impedance microscopy (MIM), which probes conductivity without Schottky barrier’s influence. The difference between the dc and microwave conductivities reflects the efficacy of the injection barrier in an accumulation-mode transistor. The conductivity exhibits significant nanoscale inhomogeneity in the subthreshold regime, presumably due to trapping and release from localized states. The characteristic length scale of local fluctuations, as determined by the autocorrelation analysis, is about 200 nm. Using a random-barrier model, we can simulate the spatial variation of the potential landscape, which underlies the mesoscopic conductivity distribution. Furthermore, our work provides an intuitive way to understand the charge transport mechanism in amorphous semiconductors at the microscopic level.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Dendritic Computing with Multigate Ferroelectric Field-Effect Transistors

Although inspired by neuronal systems in the brain, artificial neural networks generally employ point-neurons, which offer computational complexity far less than that of their biological counterparts. Neurons have dendritic arbors that connect to different sets of synapses and offer local nonlinear accumulation – playing a pivotal role in processing and learning. Inspired by this, we propose a novel neuron design based on a multigate ferroelectric field-effect transistor that mimics dendrites. It leverages ferroelectric nonlinearity for local computations within dendritic branches while utilizing the transistor action to generate the neuronal output. The branched architecture enables smaller crossbar arrays in hardware integration, improving efficiency. Using an experimentally calibrated device-circuit-algorithm cosimulation framework, we demonstrate that networks incorporating our dendritic neurons achieve superior performance compared to much larger networks without dendrites (∼ 17× fewer trainable weight parameters). These findings suggest that dendritic hardware can significantly improve computational efficiency and learning capacity of neuromorphic systems optimized for edge applications.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Organic thin-film transistors with a bottom bilayer gate dielectric having a low operating voltage and high operational stability

This study reports on p-channel bottom-gate organic thin-film transistors (OTFT) that achieve low-voltage operation with a thin bilayer gate dielectric of CYTOP/HfO 2 that also leads to high operational stability. A bottom-gate geometry allows the thickness of the gate dielectric to be reduced to 17 nm, thereby increasing the gate dielectric capacitance density to a value of up to 258 nF/cm 2 . All OTFTs yielded threshold voltages (V TH ) lower than -1 V, thereby providing minimum operating voltage (gate to source voltage ~ V TH ) of -1 V with field-effect mobility values in the range from 0.3 to 0.8 cm 2 /Vs and subthreshold swing values below 100 mV/dec. Operational stability during DC bias stress was found similar to that measured in devices with a top-gate geometry, with about 1% of drain current change after 6 h. Here, using a double-stretched exponential function, the operational stability characteristics were modeled. It was found that by increasing the metal oxide layer thickness, the threshold voltage can shift toward positive values under DC stress tests. For CYTOP layer thicknesses above 15 nm, a thicker CYTOP layer was found to shift the threshold voltage in the opposite direction toward negative values. Furthermore, these p-channel bottom-gate organic transistor with a bilayer gate dielectric of CYTOP/HfO 2 combine high mobility, high operational stability, and lower voltage operation of -1 V compared to top-gate OTFTs.

36 MATERIALS SCIENCE↗
DOE OSTI2021

Maximized Hole Trapping in a Polystyrene Transistor Dielectric from a Highly Branched Iminobis(aminoarene) Side Chain

We synthesized highly branched and electron donating side chain subunits and attached them to polystyrene (PS) used as a dielectric layer in a pentacene field effect transistor. The influence of these groups on dielectric function, charge retention and threshold voltage shifts (ΔV th ) depending on their positions in dielectric multilayers was determined. We compared the observations made on an N-perphenylated iminobisaniline side chain with those from the same side chains modified with ZnO nanoparticles and with an adduct formed from tetracyanoethylene (TCNE). We also synthesized an analogue in which six methoxy groups are present instead of two amine nitrogens. At 6 mol % side chain, hopping transport was sufficient to cause shorting of the gate, while at 2 mol %, charge trapping was observable as transistor threshold voltage shifts (ΔV th ). Here, we created three types of devices: with the substituted PS layer as single layer dielectric, on top of a crosslinked PS layer but in contact with the pentacene (bilayers), and sandwiched between two PS layers in trilayers. Particularly large bias stress effects and ΔV th , larger than the hexamethoxy and previously studied dimethoxy analogs, were observed in the second case and the effects increased with the increasing electron donating properties of the modified side chains. The highest ΔV th was consistent with a majority of the side chains stabilizing trapped charge. Trilayer devices showed decreased charge storage capability compared to previous work in which we used less donating side chains but in higher concentrations. The ZnO and TCNE modifications resulted in slightly more and less negative ΔV th , respectively, when the side chain polystyrene was not in contact with the pentacene and isolated from the gate electrode. The results indicate a likely maximum combination of molecular charge stabilizing activity and side chain concentration that still allows gate dielectric function.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Domain wall enabled steep slope switching in MoS2 transistors towards hysteresis-free operation

Abstract The device concept of ferroelectric-based negative capacitance (NC) transistors offers a promising route for achieving energy-efficient logic applications that can outperform the conventional semiconductor technology, while viable operation mechanisms remain a central topic of debate. In this work, we report steep slope switching in MoS 2 transistors back-gated by single-layer polycrystalline PbZr 0.35 Ti 0.65 O 3 . The devices exhibit current switching ratios up to 8 × 10 6 within an ultra-low gate voltage window of $$V_{{{\mathrm{g}}}} = \pm \! 0.5$$ V g = ± 0.5 V and subthreshold swing (SS) as low as 9.7 mV decade −1 at room temperature, transcending the 60 mV decade −1 Boltzmann limit without involving additional dielectric layers. Theoretical modeling reveals the dominant role of the metastable polar states within domain walls in enabling the NC mode, which is corroborated by the relation between SS and domain wall density. Our findings shed light on a hysteresis-free mechanism for NC operation, providing a simple yet effective material strategy for developing low-power 2D nanoelectronics.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Tunnel junction-enabled monolithically integrated GaN micro-light emitting transistor

GaN/InGaN microLEDs are a very promising technology for next-generation displays. Switching control transistors and their integration are key components in achieving high-performance, efficient displays. Monolithic integration of microLEDs with GaN switching devices provides an opportunity to control microLED output power with capacitive (voltage)-controlled rather than current-controlled schemes. This approach can greatly reduce system complexity for the driver circuit arrays while maintaining device opto-electronic performance. In this work, we demonstrate a 3-terminal GaN micro-light emitting transistor that combines a GaN/InGaN blue tunneling-based microLED with a GaN n-channel FET. Further, the integrated device exhibits excellent gate control, drain current control, and optical emission control. This work provides a promising pathway for future monolithic integration of GaN FETs with microLED to enable fast switching, high-efficiency microLED display and communication systems.

42 ENGINEERING↗
DOE OSTI2024

Influence of electrical field on the susceptibility of gallium nitride transistors to proton irradiation

Radiation susceptibility of electronic devices is commonly studied as a function of radiation energetics and device physics. Often overlooked is the presence or magnitude of the electrical field, which we hypothesize to play an influential role in low energy radiation. Accordingly, we present a comprehensive study of low-energy proton irradiation on gallium nitride high electron mobility transistors (HEMTs), turning the transistor ON or OFF during irradiation. Commercially available GaN HEMTs were exposed to 300 keV proton irradiation at fluences varying from 3.76 × 10 12 to 3.76 × 10 14 cm 2 , and the electrical performance was evaluated in terms of forward saturation current, transconductance, and threshold voltage. The results demonstrate that the presence of an electrical field makes it more susceptible to proton irradiation. The decrease of 12.4% in forward saturation and 19% in transconductance at the lowest fluence in ON mode suggests that both carrier density and mobility are reduced after irradiation. Additionally, a positive shift in threshold voltage (0.32 V and 0.09 V in ON and OFF mode, respectively) indicates the generation of acceptor-like traps due to proton bombardment. high-resolution transmission electron microscopy and energy dispersive x-ray spectroscopy analysis reveal significant defects introduction and atom intermixing near AlGaN/GaN interfaces and within the GaN layer after the highest irradiation dose employed in this study. According to in-situ Raman spectroscopy, defects caused by irradiation can lead to a rise in self-heating and a considerable increase in (∼750 times) thermoelastic stress in the GaN layer during device operation. The findings indicate device engineering or electrical biasing protocol must be employed to compensate for radiation-induced defects formed during proton irradiation to improve device durability and reliability.

gallium nitride↗
DOE OSTI2017

Tunneling, Current Gain, and Transconductance in Silicon-Germanium Heterojunction Bipolar Transistors Operating at Millikelvin Temperatures

Quantum-transport measurements in advanced silicon-germanium heterojunction bipolar transistors (SiGe HBTs) are presented and analyzed, including tunneling spectroscopy of discrete impurity levels localized within the transistor and the dependence on an applied magnetic field. The collector current at millikelvin temperatures is well accounted for by ideal electron tunneling throughout the entire base. Furthermore, the amplification principle at millikelvin temperatures is fundamentally quantum mechanical in nature: an increase in base voltage, requiring a moderate base current, creates an equal and opposite decrease in the tunneling barrier seen by the electrons in the emitter, thereby increasing the collector current significantly more than the base current, producing current gain. Highly scaled SiGe HBTs operate predictably at millikelvin temperatures, thus opening the possibility of viable SiGe millikelvin circuitry.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2024

Ambipolar Transport in Polycrystalline GeSn Transistors for Complementary Metal-Oxide-Semiconductor Applications

Group-IV alloy GeSn is a promising material for electronic and optoelectronic applications due to its compatibility with both Si substrates and established Si fabrication processes. This study focuses on polycrystalline GeSn (10% Sn), which offers a cost-effective, large-area, and versatile alternative to epitaxial GeSn. We demonstrate ambipolar transport behavior in polycrystalline GeSn thin film transistors, achieving electron and hole field-effect mobilities reaching up to 0.05 cm 2 /Vs and 2.05 cm 2 /Vs, respectively. Through temperature-dependent analysis, we elucidate the underlying mechanism of this phenomenon, which we attribute to quantum tunneling between the Schottky barrier contact and the channel, as well as potential barriers between the grain boundaries of this polycrystalline film, thereby advancing the understanding of polycrystalline GeSn's electrical properties. Furthermore, this work highlights the potential of ambipolar transport as a technique to employ towards the development of GeSn complementary metal-oxide-semiconductor field-effect transistors, promising to simplify and reduce the cost of GeSn manufacturing processes for edge computing and sensing applications.

42 ENGINEERING↗
DOE OSTI2021

Compensated Contacts for Three-Terminal Transistor Solar Cells

The heterojunction bipolar transistor solar cell (HBTSC) is an alternative to conventional double-junction solar cells that combines the advantages of three-terminal architectures with a compact design. A critical part of the HBTSC fabrication is the implementation of the middle contact, the one associated to the base layer in the transistor structure, because this layer can be damaged by the diffusion of metallic species during contact annealing. As a solution we propose to implement a "compensated contact", that is, to leave a thin (< 200 nm) portion of emitter or collector between the base layer and the contact metals and compensate its doping during contact annealing. Using an Au/Zn/Au metal structure to compensate a 150 nm thick portion of the collector, we obtain a specific contact resistance ~8 10-4 ..omega.. cm2. This value is fairly invariant for annealing temperatures between 400 and 460 degrees C and annealing times between 2 and 5 minutes, and it does not improve by adding Pd to the metallic stack. Optimizing the compensated contact technology opens the path to the realization of III-V-material-based HBTSCs with open-circuit voltages and fill factors comparable to those of conventional multijunction architectures.

contact resistance↗
DOE OSTI2023

Low-Frequency Noise and Deep Level Transient Spectroscopy in n-p-n Si Bipolar Junction Transistors Irradiated with Si Ions

The properties of defects in n-p-n Si bipolar junction transistors (BJTs) caused by 17 MeV Si ions are investigated via current-voltage, low-frequency noise, and deep-level transient spectroscopy (DLTS) measurements. Four prominent radiation-induced defects in the base-collector junction of these transistors are identified via DLTS. At least two defect levels are observed in temperature-dependent low-frequency 1/ f noise measurements, one that is similar to a prominent defect in DLTS and another that is not. Defect microstructures are discussed. Here our results show that DLTS and 1/ f noise measurements can provide complementary information about defects in linear bipolar devices.

42 ENGINEERING↗
DOE OSTI2018

Physical Principles of Self-Consistent Simulation of the Generation of Interface States and the Transport of Hot Charge Carriers in Field-Effect Transistors Based on Metal–Oxide–Semiconductor Structures

A detailed simulation of degradation (caused by hot charge carriers) based on self-consistent consideration of the transport of charge carriers and the generation of defects at the SiO{sub 2}/Si interface is carried out for the first time. The model is tested using degradation data obtained with decananometer n-type-channel field-effect transistors. It is shown that the mutual influence of the above aspects is significant and their independent simulation gives rise to considerable quantitative errors. In calculations of the energy distribution for charge carriers, the actual band structure of silicon and such mechanisms as impact ionization, scattering at an ionized impurity, and also electron–phonon and electron–electron interactions are taken into account. At the microscopic level, the generation of defects is considered as the superposition of single-particle and multiparticle mechanisms of breakage of the Si–H bond. A very important applied aspect of this study is the fact that our model makes it possible to reliably assess the operating lifetime of a transistor subjected to the effects of “hot” charge carriers.

36 MATERIALS SCIENCE↗
DOE OSTI2018

Analysis of the Behavior of Nonequilibrium Semiconductor Structures and Microwave Transistors During and After Pulsed γ- and γ-Neutron Irradiation

The influence of nonequilibrium processes in semiconductor structures under the effect of radiation on the characteristics of structures and microwave transistors based on them is analyzed. Special attention is paid to the comparison of pilot (experimental) and series-produced structures and transistors based on them before and after γ-neutron irradiation.

36 MATERIALS SCIENCE↗
DOE OSTI2019

Effect of the Electric Mode and γ Irradiation on Surface-Defect Formation at the Si–SiO{sub 2} Interface in a MOS Transistor

The results of experimental investigation into surface-defect formation under the effect of gamma-radiation with a dose rate P = 0.1 rad(Si)/s on MOS (metal-oxide-semiconductor) transistors with the n-type channel in the passive and active modes are presented. Two stages of surface-defect formation are observed. A qualitative model is proposed to explain the effect of the the drain transistor voltage on the defect formation process.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2019

Comparative Studies of AlGaAs/InGaAs Enhancement/Depletion-Mode High Electron Mobility Transistors with Virtual Channel Layers by Hybrid Gate Recesses Approaches

Unlike the conventional GaAs- and InP-based enhancement/depletion-mode (E/D-mode) transistors, the improved gate characteristics of the AlGaAs/InGaAs E-mode high electron mobility transistors (HEMTs) by way of hybrid gate recesses to remove the n-AlAs/i-GaAs/n-AlGaAs virtual channel layers upon 2DEG channels are demonstrated. As compared to the D-mode device (sample A), the gate reverse currents are effectively reduced by 45 and 102 times for the E-mode devices with additional gate recess time of 24 s (sample B) and 30 s (sample C) to remove part of the virtual channel layers, respectively. Under gate forward bias, the hybrid gate recesses also enable the gate turn-on voltages to increase. Furthermore, the threshold voltages of –1.25, 0.09, and 0.22 V are observed in the samples A, B, and C, respectively. The maximum transconductances of 187.3, 209.2, and 243.4 mS/mm and saturation current density of 482.8, 410.6, and 347.4 mA/mm are obtained in the samples A, B, and C, respectively.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2019

Redox transistors for neuromorphic computing

Efficiency bottlenecks inherent to conventional computing in executing neural algorithms have spurred the development of novel devices capable of “in-memory” computing. Commonly known as “memristors,” a variety of device concepts including conducting bridge, vacancy filament, phase change, and other types have been proposed as promising elements in artificial neural networks for executing inference and learning algorithms. In this article, we review the recent advances in memristor technology for neuromorphic computing and discuss strategies for addressing the most significant performance challenges, including nonlinearity, high read/write currents, and endurance. As an alternative to two-terminal memristors, we introduce the three-terminal electrochemical memory based on the redox transistor (RT), which uses a gate to tune the redox state of the channel. Decoupling the “read” and “write” operations using a third terminal and storage of information as a charge-compensated redox reaction in the bulk of the transistor enables high-density information storage. These properties enable low-energy operation without compromising analog performance and nonvolatility. Finally, we discuss the RT operating mechanisms using organic and inorganic materials, approaches for array integration, and prospects for achieving the device density and switching speeds necessary to make electrochemical memory competitive with established digital technology.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

Al 0.85 Ga 0.15 N/Al 0.70 Ga 0.30 N High Electron Mobility Transistors with Schottky Gates and Large On/Off Current Ratio over Temperature

AlGaN-channel high electron mobility transistors (HEMTs) are among a class of ultra wide-bandgap transistors that are promising candidates for RF and power applications. Long-channel Al x Ga 1-x N HEMTs with x = 0.7 in the channel have been built and evaluated across the -50°C to +200°C temperature range. These devices achieved room temperature drain current as high as 46 mA/mm and were absent of gate leakage until the gate diode forward bias turn-on at ~2.8 V, with a modest -2.2 V threshold voltage. A very large I on /I off current ratio, of 8 × 10 9 was demonstrated. A near ideal subthreshold slope that is just 35% higher than the theoretical limit across the temperature range was characterized. The ohmic contact characteristics were rectifying from -50°C to +50°C and became nearly linear at temperatures above 100°C. An activation energy of 0.55 eV dictates the temperature dependence of off-state leakage.

36 MATERIALS SCIENCE↗