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At least 145 records · Page 8

Understanding the Mechanism of Electronic Defect Suppression Enabled by Nonidealities in Atomic Layer Deposition

Silicon germanium (SiGe) is a multifunctional material considered for quantum computing, neuromorphic devices, and CMOS transistors. However, implementation of SiGe in nanoscale electronic devices necessitates suppression of surface states dominating the electronic properties. The absence of a stable and passive surface oxide for SiGe results in the formation of charge traps at the SiGe-oxide interface induced by GeOx. In an ideal ALD process in which oxide is grown layer by layer, the GeO x formation should be prevented with selective surface oxidation (i.e., formation of an SiO x interface) by controlling the oxidant dose in the first few ALD cycles of the oxide deposition on SiGe. However, in a real ALD process, the interface evolves during the entire ALD oxide deposition due to diffusion of reactant species through the gate oxide. In this work, this diffusion process in nonideal ALD is investigated and exploited: the diffusion through the oxide during ALD is utilized to passivate the interfacial defects by employing ozone as a secondary oxidant. Periodic ozone exposure during gate oxide ALD on SiGe is shown to reduce the integrated trap density (D it ) across the band gap by nearly 1 order of magnitude in Al 2 O 3 (<6 × 10 10 cm -2 ) and in HfO 2 (<3.9 × 10 11 cm -2 ) by forming a SiO x -rich interface on SiGe. Depletion of Ge from the interfacial layer (IL) by enhancement of volatile GeO x formation and consequent desorption from the SiGe with ozone insertion during the ALD growth process is confirmed by electron energy loss spectroscopy (STEM-EELS) and hypothesized to be the mechanism for reduction of the interfacial defects. In this work, the nanoscale mechanism for defect suppression at the SiGe-oxide interface is demonstrated, which is engineering of diffusion species in the ALD process due to facile diffusion of reactant species in nonideal ALD.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

Molten Target Sputtering: Non-Conventional Method for High Mobility Si0.15Ge0.85 Growth at 500°C

Since electrons travel over 100 times faster in Silicon-Germanium (SiGe) than in pure Si due to the low effective masses associated with Ge and SiGe-based devices continue to replace Si-based solid-state electronic devices. SiGe thin film on sapphire was successfully grown at 890°C, using a magnetron sputtering system within heteroepitaxial framework. However, SiGe growth at 890oC is a costly and difficult process to produce as a uniform wafer for semiconductor device manufacturing due to thermal soak times, and geometric thermal shadowing from the wafer holder. To leverage the semiconducting capabilities of SiGe, novel processing techniques for SiGe film growth with decreased thermal loading are required. This paper introduces the Molten Target Sputtering (MTS) method that produces high mobility SiGe on sapphire below 500°C. This non-conventional method has the advantage of high kinetic energy, high-energy latency, and high flux density of sputtered atoms by combining benefits of both magnetron sputtering and thermal evaporation. For the MTS method, a 1~2 mm (depth and width) ring-shaped groove was cut between the center magnet and surrounded by electromagnets creating a circular cavity between the copper plate and source target materials that melt the target material. The SiGe grown from the MTS shows continuous morphology and 99.7% single crystal Si0.15Ge0.85 films. The Hall electron mobilities of the Si0.15Ge0.85 are 456 sq. cmV(exp -1)s(exp -1) and 123.9 sq. cmV(exp -1)s(exp -1) at 5.59 x 10(exp 18) cubic cm and 3.5 x 10(exp 20) cubic cm carrier concentration at 22.38°C, respectively. This is approximately 5.5 times higher than that of Si and similar to the Ge value at equivalent carrier concentrations and temperatures.

High mobility SiGe↗

SiGe/Si heterojunction internal photoemission long-wavelength infrared detectors fabricated by molecular beam epitaxy

A new SiGe/Si heterojunction internal photoemission (HIP) long-wavelength infrared (LWIR) detector has been fabricated by molecular beam epitaxy (MBE). The detection mechanism of the SiGe/Si HIP detector is infrared absorption in the degenerately doped p+-SiGe layer followed by internal photoemission of photoexcited holes over a heterojunction barrier. By adjusting the Ge concentration in the SiGe layer, and, consequently, the valence band offset between SiGe and Si, the cutoff wavelength of SiGe HIP detectors can be extended into the LWIR (8-17-micron) regime. Detectors were fabricated by growing p+-SiGe layers using MBE on patterned p-type Si substrates. The SiGe layers were boron-doped, with concentrations ranging from 10 to the 19th/cu cm to 4 x 10 to the 20th/cu cm. Infrared absorption of 5-25 percent in a 30-nm-thick p+-SiGe layer was measured in the 3-20-micron range using a Fourier transform infrared spectrometer. Quantum efficiencies of 3-5 percent have been obtained from test devices in the 8-12-micron range.

Lin, True-Lon↗

Graded Index Silicon Geranium on Lattice Matched Silicon Geranium Semiconductor Alloy

A lattice matched silicon germanium (SiGe) semiconductive alloy is formed when a {111} crystal plane of a cubic diamond structure SiGe is grown on the {0001} C-plane of a single crystalline Al2O3 substrate such that a <110> orientation of the cubic diamond structure SiGe is aligned with a <1,0,-1,0> orientation of the {0001} C-plane. A lattice match between the substrate and the SiGe is achieved by using a SiGe composition that is 0.7223 atomic percent silicon and 0.2777 atomic percent germanium. A layer of Si(1-x), ,Ge(x) is formed on the cubic diamond structure SiGe. The value of X (i) defines an atomic percent of germanium satisfying 0.2277<X<1.0,(ii) is approximately 0.2777 where the layer of Si(1-x)Ge(x)interfaces with the cubic diamond structure SiGe, and (iii) increases linearly with the thickness of the layer of Si(1-x)Ge(x).

Park, Yeonjoon↗

Lattice-Matched Semiconductor Layers on Single Crystalline Sapphire Substrate

SiGe is an important semiconductor alloy for high-speed field effect transistors (FETs), high-temperature thermoelectric devices, photovoltaic solar cells, and photon detectors. The growth of SiGe layer is difficult because SiGe alloys have different lattice constants from those of the common Si wafers, which leads to a high density of defects, including dislocations, micro-twins, cracks, and delaminations. This innovation utilizes newly developed rhombohedral epitaxy of cubic semiconductors on trigonal substrates in order to solve the lattice mismatch problem of SiGe by using trigonal single crystals like sapphire (Al2O3) as substrate to give a unique growth-orientation to the SiGe layer, which is automatically controlled at the interface upon sapphire (0001). This technology is different from previous silicon on insulator (SOI) or SGOI (SiGe on insulator) technologies that use amorphous SiO2 as the growth plane. A cubic semiconductor crystal is a special case of a rhombohedron with the inter-planar angle, alpha = 90 deg. With a mathematical transformation, all rhombohedrons can be described by trigonal crystal lattice structures. Therefore, all cubic lattice constants and crystal planes (hkl) s can be transformed into those of trigonal crystal parameters. These unique alignments enable a new opportunity of perfect lattice matching conditions, which can eliminate misfit dislocations. Previously, these atomic alignments were thought to be impossible or very difficult. With the invention of a new x-ray diffraction measurement method here, growth of cubic semiconductors on trigonal crystals became possible. This epitaxy and lattice-matching condition can be applied not only to SiGe (111)/sapphire (0001) substrate relations, but also to other crystal structures and other materials, including similar crystal structures which have pointgroup rotational symmetries by 120 because the cubic (111) direction has 120 rotational symmetry. The use of slightly miscut (less than plus or minus 10 deg.) sapphire (0001) substrate can be used to improve epitaxial relationships better by providing attractive atomic steps in the epitaxial process.

Choi, Sang↗

Nanomembrane-based materials for Group IV semiconductor quantum electronics

Strained-silicon/relaxed-silicon-germanium alloy (strained-Si/SiGe) heterostructures are the foundation of Group IV-element quantum electronics and quantum computation, but current materials quality limits the reliability and thus the achievable performance of devices. In comparison to conventional approaches, single-crystal SiGe nanomembranes are a promising alternative as substrates for the epitaxial growth of these heterostructures. Because the nanomembrane is truly a single crystal, in contrast to the conventional SiGe substrate made by compositionally grading SiGe grown on bulk Si, significant improvements in quantum electronic-device reliability may be expected with nanomembrane substrates. We compare lateral strain inhomogeneities and the local mosaic structure (crystalline tilt) in strained-Si/SiGe heterostructures that we grow on SiGe nanomembranes and on compositionally graded SiGe substrates, with micro-Raman mapping and nanodiffraction, respectively. Significant structural improvements are found using SiGe nanomembranes.

NANOSCALE MATERIALS↗

Lattice-engineered Si{sub 1-x}Ge{sub x}-buffer on Si(001) for GaP integration

We report a detailed structure and defect characterization study on gallium phosphide (GaP) layers integrated on silicon (Si) (001) via silicon-germanium (SiGe) buffer layers. The presented approach uses an almost fully relaxed SiGe buffer heterostructure of only 400 nm thickness whose in-plane lattice constant is matched to GaP—not at room but at GaP deposition temperature. Single crystalline, pseudomorphic 270 nm thick GaP is successfully grown by metalorganic chemical vapour deposition on a 400 nm Si{sub 0.85}Ge{sub 0.15}/Si(001) heterosystem, but carries a 0.08% tensile strain after cooling down to room temperature due to the bigger thermal expansion coefficient of GaP with respect to Si. Transmission electron microscopy (TEM) studies confirm the absence of misfit dislocations in the pseudomorphic GaP film but growth defects (e.g., stacking faults, microtwins, etc.) especially at the GaP/SiGe interface region are detected. We interpret these growth defects as a residue of the initial 3D island coalescence phase of the GaP film on the SiGe buffer. TEM-energy-dispersive x-ray spectroscopy studies reveal that these defects are often correlated with stoichiometric inhomogeneities in the GaP film. Time-of-flight Secondary ion mass spectrometry detects sharp heterointerfaces between GaP and SiGe films with a minor level of Ga diffusion into the SiGe buffer.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Silicon germanium semiconductive alloy and method of fabricating same

A silicon germanium (SiGe) semiconductive alloy is grown on a substrate of single crystalline Al.sub.2O.sub.3. A {111} crystal plane of a cubic diamond structure SiGe is grown on the substrate's {0001} C-plane such that a <110> orientation of the cubic diamond structure SiGe is aligned with a <1,0,-1,0> orientation of the {0001} C-plane. A lattice match between the substrate and the SiGe is achieved by using a SiGe composition that is 0.7223 atomic percent silicon and 0.2777 atomic percent germanium.

Park, Yeonjoon↗

Differential Resonant Ring YIG Tuned Oscillator

A differential SiGe oscillator circuit uses a resonant ring-oscillator topology in order to electronically tune the oscillator over multi-octave bandwidths. The oscillator s tuning is extremely linear, because the oscillator s frequency depends on the magnetic tuning of a YIG sphere, whose resonant frequency is equal to a fundamental constant times the DC magnetic field. This extremely simple circuit topology uses two coupling loops connecting a differential pair of SiGe bipolar transistors into a feedback configuration using a YIG tuned filter creating a closed-loop ring oscillator. SiGe device technology is used for this oscillator in order to keep the transistor s 1/f noise to an absolute minimum in order to achieve minimum RF phase noise. The single-end resonant ring oscillator currently has an advantage in fewer parts, but when the oscillation frequency is greater than 16 GHz, the package s parasitic behavior couples energy to the sphere and causes holes and poor phase noise performance. This is because the coupling to the YIG is extremely low, so that the oscillator operates at near the unloaded Q. With the differential resonant ring oscillator, the oscillation currents are just in the YIG coupling mechanisms. The phase noise is even better, and the physical size can be reduced to permit monolithic microwave integrated circuit oscillators. This invention is a YIG tuned oscillator circuit making use of a differential topology to simultaneously achieve an extremely broadband electronic tuning range and ultra-low phase noise. As a natural result of its differential circuit topology, all reactive elements, such as tuning stubs, which limit tuning bandwidth by contributing excessive open loop phase shift, have been eliminated. The differential oscillator s open-loop phase shift is associated with completely non-dispersive circuit elements such as the physical angle of the coupling loops, a differential loop crossover, and the high-frequency phase shift of the n-p-n transistors. At the input of the oscillator s feedback loop is a pair of differentially connected n-p-n SiGe transistors that provides extremely high gain, and because they are bulk-effect devices, extremely low 1/f noise (leading to ultralow RF phase noise). The 1/f corner frequency for n-p-n SiGe transistors is approximately 500 Hz. The RF energy from the transistor s collector output is connected directly to the top-coupling loop (the excitation loop) of a single-sphere YIG tuned filter. A uniform magnetic field to bias the YIG must be at a right angle to any vector associated with an RF current in a coupling loop in order for the precession to interact with the RF currents.

Parrott, Ronald A.↗

Engineering High- k /SiGe Interface with ALD Oxide for Selective GeO x Reduction

Suppression of electronic defects induced by GeO x at the high- k gate oxide/SiGe interface is critical for implementation of high-mobility SiGe channels in complementary metal-oxide-semiconductor (CMOS) technology. Theoretical and experimental studies have shown that a low defect density interface can be formed with an SiO x -rich interlayer on SiGe. Experimental studies in the literature indicate a better interface formation with Al 2 O 3 in contrast to HfO 2 on SiGe; yet, the mechanism behind this is not well understood. In this study, the mechanism of forming a low defect density interface between Al 2 O 3 /SiGe is discovered using atomic layer deposited (ALD) Al 2 O 3 insertion into or on top of ALD HfO 2 gate oxides. To elucidate the mechanism, correlations are made between the defect density determined by impedance measurements and the chemical and physical structures of the interface determined by high-resolution scanning transmission electron microscopy and electron energy loss spectroscopy. The compositional analysis reveals an SiO x rich interlayer for both Al 2 O 3 /SiGe and HfO 2 /SiGe interfaces with the insertion of Al 2 O 3 into or on top of the HfO 2 oxide. The data is consistent with the Al 2 O 3 insertion inducing decomposition of the GeO x from the interface to form an electrically passive, SiO x rich interface on SiGe. This mechanism demonstrates that nanolaminate gate oxide chemistry cannot be interpreted as resulting from a simple layer-by-layer ideal ALD process, because the precursor or its reaction products can diffuse through the oxide during growth and react at the semiconductor interface. This finding shows that in scaled CMOS, remote oxide ALD (oxide ALD on top of the gate oxide) can be used to suppress electronic defects at gate oxide semiconductor interfaces by oxygen scavenging.

36 MATERIALS SCIENCE↗