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Recent report describes reliability study of two charge-coupled-device (CCD) shift registers. Major objective of study was to establish methodology for selecting, testing, screening, derating and applying CCD's. Includes a discussion of CCD structures and operating principles. Characteristics of SCCD and BCCD types are compared.
An imaging system comprises a multi-channel matrix array of CCD devices wherein a number of sensor cells (pixels) in each channel are subdivided and operated in discrete intercoupled groups of subarrays with a readout CCD shift register terminating each end of the channels. Clock voltages, applied to the subarrays, selectively cause charge signal flow in each subarray in either direction independent of the other subarrays. By selective application of four phase clock voltages, either one, two or all three of the sections subarray sections cause charge signal flow in one direction, while the remainder cause charge signal flow in the opposite direction. This creates a form of selective electronic exposure control which provides an effective variable time delay and integration of three, six or nine sensor cells or integration stages. The device is constructed on a semiconductor sustrate with a buried channel and is adapted for front surface imaging through transparent doped tin oxide gates.
A memory-based parallel data output controller employs associative memories and memory mapping to decommutate multiple channels of telemetry data. The output controller contains a random access memory (RAM) which has at least as many address locations as there are channels. A word counter addresses the RAM which provides as it outputs an encoded peripheral device number and a MSB/LSB-first flag. The encoded device number and a bit counter address a second RAM which contains START and STOP flags to pick out the required bits from the specified word number. The LSB/MSB, START and STOP flags, along with the serial input digital data go to a control block which selectively fills a shift register used to drive the parallel data output bus.
An improved Charge Injection Device (CID) stellar tracking sensor and an operating sensor in a control/readout electronics board were developed. The sensor consists of a shift register scanned, 256x256 CID array organized for readout of 4x4 subarrays. The 4x4 subarrays can be positioned anywhere within the 256x256 array with a 2 pixel resolution. This allows continuous tracking of a number of stars simultaneously since nine pixels (3x3) centered on any star can always be read out. Organization and operation of this sensor and the improvements in design and semiconductor processing are described. A hermetic package incorporating an internal thermoelectric cooler assembled using low temperature solders was developed. The electronics board, which contains the sensor drivers, amplifiers, sample hold circuits, multiplexer, analog to digital converter, and the sensor temperature control circuits, is also described. Packaged sensors were evaluated for readout efficiency, spectral quantum efficiency, temporal noise, fixed pattern noise, and dark current. Eight sensors along with two tracker electronics boards were completed, evaluated, and delivered.
This paper is concerned with the application of optics to digital computing. A Hughes liquid crystal light valve is used as an active optical element where a weak light beam can control a strong light beam with either a positive or negative gain characteristic. With this device as the central element the ability to produce bistable states from which different types of flip-flop can be implemented is demonstrated. In this paper, some general comments are first presented on digital computing as applied to optics. This is followed by a discussion of optical implementation of various types of flip-flop. These flip-flops are then used in the design of optical equivalents to a few simple sequential circuits such as shift registers and accumulators. As a typical sequential machine, a schematic layout for an optical binary temporal integrator is presented. Finally, a suggested experimental configuration for an optical master-slave flip-flop array is given.
Architecture developed for noise generator based on pseudorandom number sequence. Concept involves no additions or multiplications; outputs of set of feedback shift registers combined, bit-by-bit, in accordance with desired probability distribution. Digital, pseudorandom number output fed to digital-to-analog converter to generate pseudonoise signal suitable for testing broadband amplifiers.
The addressable inverter matrix consists of 222 inverters each accessible with the aid of a shift register. The structure has proven useful in characterizing the variability of inverter transfer curves and in diagnosing processing faults. For good 3-micron CMOS bulk inverters investigated, the percent standard deviation of the inverter threshold voltage was less than one percent and the inverter gain (the slope of the inverter transfer curve at the inverter threshold vltage) was less than 3 percent. The average noise margin for the inverters was near 2 volts for a power supply voltage of 5 volts. The specific faults studied included undersize pull-down transistor widths and various open contacts in the matrix.
The addressable inverter matrix consists of 222 inverters each accessible with the aid of a shift register. The structure has proven useful in characterizing the variability of inverter transfer curves and in diagnosing processing faults. For good 3-micron CMOS bulk inverters investigated in this study, the percent standard deviation of the inverter threshold voltage was less than one percent and the inverter gain (the slope of the inverter transfer curve at the inverter threshold voltage) was less than 3 percent. The average noise margin for the inverters was near 2 volts for a power supply voltage of 5 volts. The specific faults studied included undersize pull-down transistor widths and various open contacts in the matrix.
The features and performance parameters of the frequency domain laser velocimeter signal processor (FDSP) for examining flow phenomena are described. A candidate for replacing the standard signal processor, the FDSP can function receiving bursts of as few as 150 photons in an instantaneous mode or down to a photon resolved regime for an averaging mode. the FDSP has a nonlinear A/D converter and data storage shift registers (high speed recorder group), an elliptic digital filter bank, a controlling microprocessor and frequency and signal gain control circuits (low speed data processing group). The high speed group amplifies, digitizes, identifies and stores burst waveforms and the low speed group identifies the signal frequency within the burst after the signal passes through digital filters. The FDSP can operate in a near-autonomous mode using photon correlation techniques and requires no human intervention for calibration.
The invention relates to a single frequency multitransmitter telemetry system that will deliver a substantial amount of data at low cost. The invention consists essentially of a plurality of sensor transmitter units at different locations, with individual signal conditioning and logic, which send sampled data signals to a single receiver. The transmitters operate independently on the same frequency in a frequency shift keying modulation system and are not synchronized to the receiver. The problem of reception of data from more than one transmitter simultaneously is solved by discarding the data - when there is overlap of data from two or more transmitters, the data is discarded and when there is no overlap the data is retained. The invention utilizes a unique overlap detection technique to determine if data should be retained or discarded. When data is received from a transmitter, it goes into a shift register.
Experimental circuits faster than simulation programs run on digital computers. Serial shift register routes clock pulses C1 to neurons in sequence. Clock pulses C2 interrogate neurons. Neuron interconnection information stored in simulated synapses. Can be expanded to greater complexity.
Transmitter and receiver devised for asynchronous digital communication via optical fiber at rates above 100 Mb/s. Transmitter converts parallel data to serial for high-speed transmission; receiver recovers clock signal and converts data back to parallel. No phase-lock loops used. New receiver design avoids over-sampling altogether. Local sampling oscillator operating nominally at clock frequency generates N clock signals of equally spaced phase, used to clock incoming data into N separate shift registers.
Size, weight, and susceptibility to burst errors reduced. Encoding system built on single very-large-scale integrated (VLSI) circuit chip produces (255,223) Reed-Solomon (RS) code with programmable interleaving up to depth of 5. (225,223) RS encoder includes new remainder-and-interleaver unit providing programmable interleaving of code words. Remainder-and-interleaver unit contains shift registers and modulo-2 adders. Signals on "turn" and "no-turn" lines control depth of interleaving. Based on E. R. Berlekamp's bit-serial multiplication algorithm for (225,223) RS encoder over Galois Field (2 to the 8th power).
A VLSI design for computing exponentiation in finite fields is developed. An algorithm to generate a relatively long pseudorandom number sequence is presented. It is shown that the period of this sequence is significantly increased compared to that of the sequence generated by the most commonly used maximal length shift register scheme.
An array processing chip integrating 128 bit-serial processing elements (PEs) on a single die is discussed. Each PE has a 16-function logic unit, a single-bit adder, a 32-b variable-length shift register, and 1 kb of local RAM. Logic in each PE provides the capability to mask PEs individually. A modified grid interconnection scheme allows each PE to communicate with each of its eight nearest neighbors. A 32-b bus is used to transfer data to and from the array in a single cycle. Instruction execution is pipelined, enabling all instructions to be executed in a single cycle. The 1-micron CMOS design contains over 1.1 x 10 to the 6th transistors on an 11.0 x 11.7-mm die.
A systolic array processing technique is applied to implementing the stack algorithm form of the sequential decoding algorithm. It is shown that sorting, a key function in the stack algorithm, can be efficiently realized by a special type of systolic arrays known as systolic priority queues. Compared to the stack-bucket algorithm, this approach is shown to have the advantages that the decoding always moves along the optimal path, that it has a fast and constant decoding speed and that its simple and regular hardware architecture is suitable for VLSI implementation. Three types of systolic priority queues are discussed: random access scheme, shift register scheme and ripple register scheme. The property of the entries stored in the systolic priority queue is also investigated. The results are applicable to many other basic sorting type problems.
In a digital device, having an input comprised of a digital sample stream at a frequency F, a method is disclosed for employing a component designed to work at a frequency less than F. The method, in general, is comprised of the following steps: dividing the digital sample stream into odd and even digital samples streams each at a frequency of F/2; passing one of the digital sample streams through the component designed to work at a frequency less than F where the component responds only to the odd or even digital samples in one of the digital sample streams; delaying the other digital sample streams for the time it takes the digital sample stream to pass through the component; and adding the one digital sample stream after passing through the component with the other delayed digital sample streams. In the specific example, the component is a finite impulse response filter of the order ((N + 1)/2) and the delaying step comprised passing the other digital sample streams through a shift register for a time (in sampling periods) of ((N + 1)/2) + r, where r is a pipline delay through the finite impulse response filter.
Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be noted that the logic theory contained herein applies to all hardware. Discussed here are synchronous binary UP counters, synchronous DOWN and UP/DOWN counters, integrated circuit counters, shift registers, sequential techniques, and designing sequential counting machines.