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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
NASA NTRS2001

Lightweight Sun-Position Sensor Developed

An orbiting spacecraft needs to be able to accurately locate the position of the Sun so that the solar arrays can be pointed toward the Sun. This not only maximizes the production of power, but it also helps the arrays find their orientation in space so that they can accurately point antennae at ground stations. As part of the work on the (now postponed) Mars-2001 Surveyor Lander, NASA Glenn Research Center engineers developed a new Sun sensor that is far lighter and simpler than earlier designs. This sensor uses the technology of a linear photodiode array to find the position of the Sun in one axis. Two of these sensors, used together, can locate the x and y coordinates of the Sun relative to the spacecraft. These sensors have a mass of only 18 g each, nearly an order of magnitude lighter than earlier designs. (This mass does not include the electronic circuit to read the photodiode output, which is on the experiment microcontroller.) Near the center of the field of view, the Sun position can be found to 0.15

Landis, Geoffrey A.↗
NASA NTRS2004

Advanced Controller for the Free-Piston Stirling Convertor

The free-piston Stirling power convertor is being considered as an advanced power conversion technology to be used for future NASA deep space missions requiring long life radioisotope power systems. This technology has a conversion efficiency of over 25%, which is significantly higher than the efficiency of the Radioisotope Thermal-electric Generators (RTG) now in use. The NASA Glenn Research Center has long been recognized as a leader in Stirling technology and is responsible for the development of advanced technologies that are intended to significantly improve key characteristics of the Stirling convertor. The advanced technologies identified for development also consider the requirements of potential future missions and the new capabilities that have become available in the associated technical areas. One of the key areas identified for technology development is the engine controller. To support this activity, an advanced controller is being developed for the Stirling power convertor. This controller utilizes active power factor correction electronics and microcontroller-based controls. The object of this paper is to present an overview of the advanced controller concept with modeling, simulation and hardware test data.

Gerber, Scott S.↗
NASA NTRS2006

A High-Throughput Processor for Flight Control Research Using Small UAVs

There are numerous autopilot systems that are commercially available for small (<100 lbs) UAVs. However, they all share several key disadvantages for conducting aerodynamic research, chief amongst which is the fact that most utilize older, slower, 8- or 16-bit microcontroller technologies. This paper describes the development and testing of a flight control system (FCS) for small UAV s based on a modern, high throughput, embedded processor. In addition, this FCS platform contains user-configurable hardware resources in the form of a Field Programmable Gate Array (FPGA) that can be used to implement custom, application-specific hardware. This hardware can be used to off-load routine tasks such as sensor data collection, from the FCS processor thereby further increasing the computational throughput of the system.

Klenke, Robert H.↗
NASA NTRS2006

BAE Systems Radiation Hardened SpaceWire ASIC and Roadmap

An Application Specific Integrated Circuit (ASIC) that implements the SpaceWire protocol has been developed in a radiation hardened 0.25 micron CMOS, technology. This effort began in March 2003 as a joint development between the NASA Goddard Space Flight Center (GSFC) and BAE Systems. The BAE Systems SpaceWire ASlC is comprised entirely of reusable core elements, many of which are already flight-proven. It incorporates a 4-port SpaceWire router with two local ports, dual PC1 bus interfaces, a microcontroller, 32KB of internal memory, -and a memory controller for additional external memory use. The SpaceWire ASlC is planned for use on both the Geostationary Operational Environmental Satellites (GOES)-R and the Lunar Reconnaissance Orbiter (LRO). Engineering parts have already been delivered to both programs. This paper discusses the SpaceWire protocol and those elements of it that have been built into the current SpaceWire reusable core. There are features within the core that go beyond the current standard that can be enabled or disabled by the user and these will be described. The adaptation of SpaceWire to BAE Systems' On Chip Bus (OCB) for compatibility with the other reusable cores will be discussed. Optional configurations within user systems will be shown. The physical imp!ementation of the design will be described and test results from the hardware will be discussed. Finally, the BAE Systems roadmap for SpaceWire developments will be discussed, including some products already in design as well as longer term plans.

Berger, Richard↗
NASA NTRS2008

Downlink data multiplexer

A data multiplexer that accommodates both industry standard CCSDS data packets and bits streams and standard IEEE 1394 data is described. The multiplexer provides a statistical allotment of bandwidth to the channels in turn, preferably four, but expandable in increments of four up to sixteen. A microcontroller determines bandwidth requested by the plurality of channels, as well as the bandwidth available, and meters out the available bandwidth on a statistical basis employing flow control to the input channels.

Holland, S. Douglas↗
NASA NTRS2009

Microwave Temperature Profiler Mounted in a Standard Airborne Research Canister

Many atmospheric research aircraft use a standard canister design to mount instruments, as this significantly facilitates their electrical and mechanical integration and thereby reduces cost. Based on more than 30 years of airborne science experience with the Microwave Temperature Profiler (MTP), the MTP has been repackaged with state-of-the-art electronics and other design improvements to fly in one of these standard canisters. All of the controlling electronics are integrated on a single 4 ~5-in. (.10 ~13- cm) multi-layer PCB (printed circuit board) with surface-mount hardware. Improved circuit design, including a self-calibrating RTD (resistive temperature detector) multiplexer, was implemented in order to reduce the size and mass of the electronics while providing increased capability. A new microcontroller-based temperature controller board was designed, providing better control with fewer components. Five such boards are used to provide local control of the temperature in various areas of the instrument, improving radiometric performance. The new stepper motor has an embedded controller eliminating the need for a separate controller board. The reference target is heated to avoid possible emissivity (and hence calibration) changes due to moisture contamination in humid environments, as well as avoiding issues with ambient targets during ascent and descent. The radiometer is a double-sideband heterodyne receiver tuned sequentially to individual oxygen emission lines near 60 GHz, with the line selection and intermediate frequency bandwidths chosen to accommodate the altitude range of the aircraft and mission.

Mahoney, Michael J.↗
NASA NTRS2007

Wearable Environmental and Physiological Sensing Unit

The wearable environmental and physiological sensing unit (WEPS) is a prototype of systems to be worn by emergency workers (e.g., firefighters and members of hazardous-material response teams) to increase their level of safety. The WEPS includes sensors that measure a few key physiological and environmental parameters, a microcontroller unit that processes the digitized outputs of the sensors, and a radio transmitter that sends the processed sensor signals to a computer in a mobile command center for monitoring by a supervisor. The monitored parameters serve as real-time indications of the wearer s physical condition and level of activity, and of the degree and type of danger posed by the wearer s environment. The supervisor could use these indications to determine, for example, whether the wearer should withdraw in the face of an increasing hazard or whether the wearer should be rescued.

Spremo, Stevan↗
NASA NTRS2009

A Micro Fluorescent Activated Cell Sorter for Astrobiology Applications

A micro-scale Fluorescent Activated Cell Sorter (microFACS) for astrobiology applications is under development. This device is designed to have a footprint of 7 cm x 7 cm x 4 cm and allow live-dead counts and sorting of cells that have fluorescent characteristics from staining. The FACS system takes advantage of microfluidics to create a cell sorter that can fit in the palm of the hand. A micron-scale channel allows cells to pass by a blue diode which causes emission of marker-expressed cells which are detected by a filtered photodetector. A small microcontroller then counts cells and operates high speed valves to select which chamber the cell is collected in (a collection chamber or a waste chamber). Cells with the expressed characteristic will be collected in the collection chamber. This system has been built and is currently being tested. We are also designing a system with integrated MEMS-based pumps and valves for a small and compact unit to fly on small satellite-based biology experiments.

Platt, Donald W.↗
NASA NTRS2010

JSC Wireless Sensor Network Update

Sensor nodes composed of three basic components... radio module: COTS radio module implementing standardized WSN protocol; treated as WSN modem by main board main board: contains application processor (TI MSP430 microcontroller), memory, power supply; responsible for sensor data acquisition, pre-processing, and task scheduling; re-used in every application with growing library of embedded C code sensor card: contains application-specific sensors, data conditioning hardware, and any advanced hardware not built into main board (DSPs, faster A/D, etc.); requires (re-) development for each application.

Wagner, Robert↗
NASA NTRS2010

Crossed, Small-Deflection Energy Analyzer for Wind/Temperature Spectrometer

Determination of neutral winds and ion drifts in low-Earth-orbit missions requires measurements of the angular and energy distributions of the flux of neutrals and ions entering the satellite from the ram direction. The magnitude and direction of the neutral-wind (or ion-drift) determine the location of the maximum in the angular distribution of the flux. Knowledge of the angle of maximum flux with respect to satellite coordinates (pointing) is essential to determine the wind (or ion-drift) vector. The crossed Small-Deflection Energy Analyzer (SDEA) spectrometer (see Figure 1) occupies minimal volume and consumes minimal power. Designed for upper atmosphere/ionosphere investigations at Earth altitudes above 100 km, the spectrometer operates by detecting the angular and energy distributions of neutral atoms/molecules and ions in two mutually perpendicular planes. In this configuration, the two detection planes actually cross at the spectrometer center. It is possible to merge two SDEAs so they share a common optical axis and alternate measurements between two perpendicular planes, and reduce the number of ion sources from two to one. This minimizes the volume and footprint significantly and reduces the ion source power by a factor of two. The area of the entrance aperture affects the number of ions detected/second and also determines the energy resolution. Thermionic emitters require heater power of about 100 mW to produce 1 mA of electron beam current. Typically, electron energy is about 100 eV and requires a 100-V supply for electron acceleration to supply an additional 100 mW of power. Thus, ion source power is at most 200 mW. If two ion sources were to be used, the ion source power would be, at most, 400 mW. Detector power, deflection voltage power, and microcontroller and other functions require less than 150 mW. A WTS (wind/ temperature spectrometer) with two separate optical axes would consume about 650 mW, while the crossed SDEA described here consumes about 350 mW. The entrance aperture has a diameter of 0.004 in. (0.10 mm) to provide the required energy resolution between 0.05 and 0.15. This design (see Figure 2) provides a WTS occupying a volume less than 40 cm(sup 3), on a footprint of diameter about 1.5 in. (38 mm). The Crossed SDEA offers many advantages in the measurements of neutral wind and ion drifts in the Earth's thermosphere. As such, it will be useful in future commercial satellites dedicated to monitoring the ionosphere with a view to improving the integrity and predictability of GPS operations.

Herrero, Federico A.↗
NASA NTRS2011

Error Mitigation of Point-to-Point Communication for Fault-Tolerant Computing

Fault tolerant systems require the ability to detect and recover from physical damage caused by the hardware s environment, faulty connectors, and system degradation over time. This ability applies to military, space, and industrial computing applications. The integrity of Point-to-Point (P2P) communication, between two microcontrollers for example, is an essential part of fault tolerant computing systems. In this paper, different methods of fault detection and recovery are presented and analyzed.

Akamine, Robert L.↗
NASA NTRS2011

Performance Comparison of Wireless Sensor Network Standard Protocols in an Aerospace Environment: ISA100.11a and ZigBee

Wireless Sensor Networks (WSNs) can provide a substantial benefit in spacecraft systems, reducing launch weight and providing unprecedented flexibility by allowing instrumentation capabilities to grow and change over time. Achieving data transport reliability on par with that of wired systems, however, can prove extremely challenging in practice. Fortunately, much progress has been made in developing standard WSN radio protocols for applications from non-critical home automation to mission-critical industrial process control. The relative performances of candidate protocols must be compared in representative aerospace environments, however, to determine their suitability for spaceflight applications. In this paper, we will present the results of a rigorous laboratory analysis of the performance of two standards-based, low power, low data rate WSN protocols: ZigBee Pro and ISA100.11a. Both are based on IEEE 802.15.4 and augment that standard's specifications to build complete, multi-hop networking stacks. ZigBee Pro targets primarily the home and office automation markets, providing an ad-hoc protocol that is computationally lightweight and easy to implement in inexpensive system-on-a-chip components. As a result of this simplicity, however, ZigBee Pro can be susceptible to radio frequency (RF) interference. ISA100.11a, on the other hand, targets the industrial process control market, providing a robust, centrally-managed protocol capable of tolerating a significant amount of RF interference. To achieve these gains, a coordinated channel hopping mechanism is employed, which entails a greater computational complexity than ZigBee and requires more sophisticated and costly hardware. To guide future aerospace deployments, we must understand how well these standards relatively perform in analog environments under expected operating conditions. Specifically, we are interested in evaluating goodput -- application level throughput -- in a representative crewed environment in the presence of varying levels of 802.11g Wi-Fi traffic. To do so, we use the NASA Johnson Space Center Wireless Habitat Testbed (WHT), a metallic, habitation-sized module designed for co-existence testing of wireless systems. In its quiescent state, the sealed WHT provides an RF-quiet environment to which we can selectively add interfering systems; it also provides a realistic level of multi-path self-interference for systems under investigation. In our test, we deploy two representative five node networks, configured in a star topology with all nodes reporting directly to a WSN gateway. Each ZigBee network WSN node is built using a Texas Instruments (TI) CC2530 system-on-a-chip radio running TI's ZigBee Pro Z-stack. Each ISA100.11a network node is built using a Nivis VersaNode 210 system-on-a-chip radio. In both cases, radios interface with TI MSP430-F5438 microcontroller implementing a common test application. Interference is provided by a D-link 802.11g Wi-Fi router transporting traffic generated using the Iperf network testing tool. For the single-channel ZigBee network, effects of both direct and indirect Wi-Fi interference are evaluated. For the channel-hopping ISA100.11a network, effects of interference from multiple Wi-Fi routers configured in non-overlapping 802.11g channels are evaluated. Our results show that, in general, the more lightweight ZigBee network performs well at low interference levels, but performance degrades as interference increases. Conversely, the more complex and costly ISA100.11a network continues to perform well as Wi-Fi interference levels increase.

Wagner, Raymond S.↗
NASA NTRS2005

Traffic-Light-Preemption Vehicle-Transponder Software Module

A prototype wireless data-communication and control system automatically modifies the switching of traffic lights to give priority to emergency vehicles. The system, which was reported in several NASA Tech Briefs articles at earlier stages of development, includes a transponder on each emergency vehicle, a monitoring and control unit (an intersection controller) at each intersection equipped with traffic lights, and a central monitoring subsystem. An essential component of the system is a software module executed by a microcontroller in each transponder. This module integrates and broadcasts data on the position, velocity, acceleration, and emergency status of the vehicle. The position, velocity, and acceleration data are derived partly from the Global Positioning System, partly from deductive reckoning, and partly from a diagnostic computer aboard the vehicle. The software module also monitors similar broadcasts from other vehicles and from intersection controllers, informs the driver of which intersections it controls, and generates visible and audible alerts to inform the driver of any other emergency vehicles that are close enough to create a potential hazard. The execution of the software module can be monitored remotely and the module can be upgraded remotely and, hence, automatically

Bachelder, Aaron↗
NASA NTRS2005

Intersection-Controller Software Module

An important part of the emergency-vehicle traffic-light-preemption system summarized in the preceding article is a software module executed by a microcontroller in each intersection controller. This module monitors the broadcasts from all nearby participating emergency vehicles and intersections. It gathers the broadcast data pertaining to the positions and velocities of the vehicles and the timing of traffic and pedestrian lights and processes the data into predictions of the future positions of the vehicles. Analyzing the predictions by a combination of proximity tests, map-matching techniques, and statistical calculations designed to minimize the adverse effects of uncertainties in vehicle positions and headings, the module decides whether to preempt and issues the appropriate commands to the traffic lights, pedestrian lights, and electronic warning signs at the intersection. The module also broadcasts its state to all nearby vehicles and intersections. The module is designed to mitigate the effects of missing data and of unpredictable delays in the system. It has been intensively tested and refined so that it fails to warn in very few cases and issues very few false warnings.

Bachelder, Aaron↗
NASA NTRS2011

Project Summary Report

The project, being the development of resource management applications, consisted entirely of my own effort. From deliverable requirements provided by my mentor, and some functional requirement additions generated through design reviews, It was my responsibility to implement the requested features as well as possible, given the resources available. For the most part development work consisted of database programming and functional testing using real resource data. Additional projects I worked on included some firing room console training, configuring the new NE-A microcontroller development lab network, mentoring high school CubeSat students, and managing the NE interns' component of the mentor appreciation ceremony.

Upchurch, Christopher↗
NASA NTRS2004

Stroboscope Controller for Imaging Helicopter Rotors

A versatile electronic timing-and-control unit, denoted a rotorcraft strobe controller, has been developed for use in controlling stroboscopes, lasers, video cameras, and other instruments for capturing still images of rotating machine parts especially helicopter rotors. This unit is designed to be compatible with a variety of sources of input shaftangle or timing signals and to be capable of generating a variety of output signals suitable for triggering instruments characterized by different input-signal specifications. It is also designed to be flexible and reconfigurable in that it can be modified and updated through changes in its control software, without need to change its hardware. Figure 1 is a block diagram of the rotorcraft strobe controller. The control processor is a high-density complementary metal oxide semiconductor, singlechip 8-bit microcontroller. It is connected to a 32K x 8 nonvolatile static random-access memory (RAM) module. Also connected to the control processor is a 32K 8 electrically programmable read-only-memory (EPROM) module, which is used to store the control software. Digital logic support circuitry is implemented in a field-programmable gate array (FPGA). A 240 x 128-dot, 40- character 16-line liquid-crystal display (LCD) module serves as a graphical user interface; the user provides input through a 16-key keypad mounted next to the LCD. A 12-bit digital-to-analog converter (DAC) generates a 0-to-10-V ramp output signal used as part of a rotor-blade monitoring system, while the control processor generates all the appropriate strobing signals. Optocouplers are used to isolate all input and output digital signals, and optoisolators are used to isolate all analog signals. The unit is designed to fit inside a 19-in. (.48-cm) rack-mount enclosure. Electronic components are mounted on a custom printed-circuit board (see Figure 2). Two power-conversion modules on the printedcircuit board convert AC power to +5 VDC and 15 VDC, respectively.

Jensen, Scott↗
NASA NTRS2004

FPGA-Based, Self-Checking, Fault-Tolerant Computers

A proposed computer architecture would exploit the capabilities of commercially available field-programmable gate arrays (FPGAs) to enable computers to detect and recover from bit errors. The main purpose of the proposed architecture is to enable fault-tolerant computing in the presence of single-event upsets (SEUs). [An SEU is a spurious bit flip (also called a soft error) caused by a single impact of ionizing radiation.] The architecture would also enable recovery from some soft errors caused by electrical transients and, to some extent, from intermittent and permanent (hard) errors caused by aging of electronic components. A typical FPGA of the current generation contains one or more complete processor cores, memories, and highspeed serial input/output (I/O) channels, making it possible to shrink a board-level processor node to a single integrated-circuit chip. Custom, highly efficient microcontrollers, general-purpose computers, custom I/O processors, and signal processors can be rapidly and efficiently implemented by use of FPGAs. Unfortunately, FPGAs are susceptible to SEUs. Prior efforts to mitigate the effects of SEUs have yielded solutions that degrade performance of the system and require support from external hardware and software. In comparison with other fault-tolerant- computing architectures (e.g., triple modular redundancy), the proposed architecture could be implemented with less circuitry and lower power demand. Moreover, the fault-tolerant computing functions would require only minimal support from circuitry outside the central processing units (CPUs) of computers, would not require any software support, and would be largely transparent to software and to other computer hardware. There would be two types of modules: a self-checking processor module and a memory system (see figure). The self-checking processor module would be implemented on a single FPGA and would be capable of detecting its own internal errors. It would contain two CPUs executing identical programs in lock step, with comparison of their outputs to detect errors. It would also contain various cache local memory circuits, communication circuits, and configurable special-purpose processors that would use self-checking checkers. (The basic principle of the self-checking checker method is to utilize logic circuitry that generates error signals whenever there is an error in either the checker or the circuit being checked.) The memory system would comprise a main memory and a hardware-controlled check-pointing system (CPS) based on a buffer memory denoted the recovery cache. The main memory would contain random-access memory (RAM) chips and FPGAs that would, in addition to everything else, implement double-error-detecting and single-error-correcting memory functions to enable recovery from single-bit errors.

Some, Raphael↗
NASA NTRS2003

Command Interface ASIC - Analog Interface ASIC Chip Set

A command interface application-specific integrated circuit (ASIC) and an analog interface ASIC have been developed as a chip set for remote actuation and monitoring of a collection of switches, which can be used to control generic loads, pyrotechnic devices, and valves in a high-radiation environment. The command interface ASIC (CIA) can be used alone or in combination with the analog interface ASIC (AIA). Designed primarily for incorporation into spacecraft control systems, they are also suitable for use in high-radiation terrestrial environments (e.g., in nuclear power plants and facilities that process radioactive materials). The primary role of the CIA within a spacecraft or other power system is to provide a reconfigurable means of regulating the power bus, actuating all valves, firing all pyrotechnic devices, and controlling the switching of power to all switchable loads. The CIA is a mixed-signal (analog and digital) ASIC that includes an embedded microcontroller with supporting fault-tolerant switch control and monitoring circuitry that is capable of connecting to a redundant set of interintegrated circuit (I(sup 2)C) buses. Commands and telemetry requests are communicated to the CIA. Adherence to the I(sup 2)C bus standard helps to reduce development costs by facilitating the use of previously developed, commercially available components. The AIA is a mixed-signal ASIC that includes the analog circuitry needed to connect the CIA to a custom higher powered version of the I(sup 2)C bus. The higher-powered version is designed to enable operation with bus cables longer than those contemplated in the I(sup 2)C standard. If there are multiple higher-power I(sup 2)C-like buses, then there must an AIA between the CIA and each such bus. The AIA includes two identical interface blocks: one for the side-A I(sup 2)C clock and data buses and the other for the side B buses. All the AIAs on each side are powered from a common power converter module (PCM). Sides A and B of the I(sup 2)C buses are electrically isolated from each other (see figure). They are also isolated from the CIA by use of transformer coupling of signals between the AIA blocks and the CIA.

Ruiz, Baldes↗