Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “Memory systems”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
NASA NTRS1974

Man machine interactive imaging and data processing using high speed digital mass storage

Attention is given to general questions regarding television systems, aspects of image distortion in TV systems, approaches of image restoration, noise limitations, and the digital image integrator. The digital image recorder has been built around a high-speed digital memory system. It is shown that television systems can be used to augment man's capabilities in the control loop of remote manipulation systems.

Alsberg, H.↗
NASA NTRS1991

Asymmetric soft-error resistant memory

A memory system is provided, of the type that includes an error-correcting circuit that detects and corrects, that more efficiently utilizes the capacity of a memory formed of groups of binary cells whose states can be inadvertently switched by ionizing radiation. Each memory cell has an asymmetric geometry, so that ionizing radiation causes a significantly greater probability of errors in one state than in the opposite state (e.g., an erroneous switch from '1' to '0' is far more likely than a switch from '0' to'1'. An asymmetric error correcting coding circuit can be used with the asymmetric memory cells, which requires fewer bits than an efficient symmetric error correcting code.

Buehler, Martin G.↗
NASA NTRS1990

32-Bit-Wide Memory Tolerates Failures

Electronic memory system of 32-bit words corrects bit errors caused by some common type of failures - even failure of entire 4-bit-wide random-access-memory (RAM) chip. Detects failure of two such chips, so user warned that ouput of memory may contain errors. Includes eight 4-bit-wide DRAM's configured so each bit of each DRAM assigned to different one of four parallel 8-bit words. Each DRAM contributes only 1 bit to each 8-bit word.

Buskirk, Glenn A.↗
NASA NTRS1976

Optical mass memories

Optical and magnetic variants in the design of trillion-bit read/write memories are compared and tabulated. Components and materials suitable for a random access read/write nonmoving memory system are examined, with preference given to holography and photoplastic materials. Advantages and deficiencies of photoplastics are reviewed. Holographic page composer design, essential features of an optical memory with no moving parts, fiche-oriented random access memory design, and materials suitable for an efficient photoplastic fiche are considered. The optical variants offer advantages in lower volume and weight at data transfer rates near 1 Mbit/sec, but power drain is of the same order as for the magnetic variants (tape memory, disk memory). The mechanical properties of photoplastic film materials still leave much to be desired.

Bailey, G. A.↗
NASA NTRS2011

Interplanetary Overlay Network Bundle Protocol Implementation

The Interplanetary Overlay Network (ION) system's BP package, an implementation of the Delay-Tolerant Networking (DTN) Bundle Protocol (BP) and supporting services, has been specifically designed to be suitable for use on deep-space robotic vehicles. Although the ION BP implementation is unique in its use of zero-copy objects for high performance, and in its use of resource-sensitive rate control, it is fully interoperable with other implementations of the BP specification (Internet RFC 5050). The ION BP implementation is built using the same software infrastructure that underlies the implementation of the CCSDS (Consultative Committee for Space Data Systems) File Delivery Protocol (CFDP) built into the flight software of Deep Impact. It is designed to minimize resource consumption, while maximizing operational robustness. For example, no dynamic allocation of system memory is required. Like all the other ION packages, ION's BP implementation is designed to port readily between Linux and Solaris (for easy development and for ground system operations) and VxWorks (for flight systems operations). The exact same source code is exercised in both environments. Initially included in the ION BP implementations are the following: libraries of functions used in constructing bundle forwarders and convergence-layer (CL) input and output adapters; a simple prototype bundle forwarder and associated CL adapters designed to run over an IPbased local area network; administrative tools for managing a simple DTN infrastructure built from these components; a background daemon process that silently destroys bundles whose time-to-live intervals have expired; a library of functions exposed to applications, enabling them to issue and receive data encapsulated in DTN bundles; and some simple applications that can be used for system checkout and benchmarking.

Burleigh, Scott C.↗
NASA NTRS1973

Modeling of a bubble-memory organization with self-checking translators to achieve high reliability.

Study of the design and modeling of a highly reliable bubble-memory system that has the capabilities of: (1) correcting a single 16-adjacent bit-group error resulting from failures in a single basic storage module (BSM), and (2) detecting with a probability greater than 0.99 any double errors resulting from failures in BSM's. The results of the study justify the design philosophy adopted of employing memory data encoding and a translator to correct single group errors and detect double group errors to enhance the overall system reliability.

Bouricius, W. G.↗
NASA NTRS2002

Effects of Ordering Strategies and Programming Paradigms on Sparse Matrix Computations

The Conjugate Gradient (CG) algorithm is perhaps the best-known iterative technique to solve sparse linear systems that are symmetric and positive definite. For systems that are ill-conditioned, it is often necessary to use a preconditioning technique. In this paper, we investigate the effects of various ordering and partitioning strategies on the performance of parallel CG and ILU(O) preconditioned CG (PCG) using different programming paradigms and architectures. Results show that for this class of applications: ordering significantly improves overall performance on both distributed and distributed shared-memory systems, that cache reuse may be more important than reducing communication, that it is possible to achieve message-passing performance using shared-memory constructs through careful data ordering and distribution, and that a hybrid MPI+OpenMP paradigm increases programming complexity with little performance gains. A implementation of CG on the Cray MTA does not require special ordering or partitioning to obtain high efficiency and scalability, giving it a distinct advantage for adaptive applications; however, it shows limited scalability for PCG due to a lack of thread level parallelism.

Oliker, Leonid↗
NASA NTRS1982

Space-Derived Sewer Monitor

The QuadraScan Longterm Flow Monitoring System is a second generation sewer monitor developed by American Digital Systems, Inc.'s founder Peter Petroff. Petroff, a former spacecraft instrumentation designer at Marshall Space Flight Center, used expertise based on principles acquired in Apollo and other NASA programs. QuadraScan borrows even more heavily from space technology, for example in its data acquisition and memory system derived from NASA satellites. "One-time" measurements are often plagued with substantial errors due to the flow of groundwater absorbed into the system. These system sizing errors stem from a basic informational deficiency: accurate, reliable data on how much water flows through a sewer system over a long period of time is very difficult to obtain. City officials are turning to "permanent," or long-term sewer monitoring systems. QuadraScan offers many advantages to city officials such as the early warning capability to effectively plan for city growth in order to avoid the crippling economic impact of bans on new sewer connections in effect in many cities today.

Source record↗
NASA NTRS1988

Self-Testing Computer Memory

Memory system for computer repeatedly tests itself during brief, regular interruptions of normal processing of data. Detects and corrects transient faults as single-event upsets (changes in bits due to ionizing radiation) within milliseconds after occuring. Self-testing concept surpasses conventional by actively flushing latent defects out of memory and attempting to correct before accumulating beyond capacity for self-correction or detection. Cost of improvement modest increase in complexity of circuitry and operating time.

Chau, Savio, N.↗
NASA NTRS1995

Media Controller For Receiving Data From A TAXI(TM) Link

TAXI(TM) media controller (TMC) is interface circuit that supports operation of test equipment in diagnosis of telemetry system in which data communicated via TAXI(TM) links. TMC designed specifically for use with TAXI(TM) test adapter for monitoring and testing telemetry data signals generated by payloads and other subsystems of Space Station Freedom. Overall, TMC characterized as providing interface between output part of a TAXI(TM) receiving chip and input port of memory system in test adapter. TMC detects some abnormalities in received data stream and resynchronizes stream to locally generated clock signal.

Stauffer, David R.↗
NASA NTRS1972

Multiprocessor architectural study

An architectural design study was made of a multiprocessor computing system intended to meet functional and performance specifications appropriate to a manned space station application. Intermetrics, previous experience, and accumulated knowledge of the multiprocessor field is used to generate a baseline philosophy for the design of a future SUMC* multiprocessor. Interrupts are defined and the crucial questions of interrupt structure, such as processor selection and response time, are discussed. Memory hierarchy and performance is discussed extensively with particular attention to the design approach which utilizes a cache memory associated with each processor. The ability of an individual processor to approach its theoretical maximum performance is then analyzed in terms of a hit ratio. Memory management is envisioned as a virtual memory system implemented either through segmentation or paging. Addressing is discussed in terms of various register design adopted by current computers and those of advanced design.

Kosmala, A. L.↗
NASA NTRS2000

Testing New Programming Paradigms with NAS Parallel Benchmarks

Over the past decade, high performance computing has evolved rapidly, not only in hardware architectures but also with increasing complexity of real applications. Technologies have been developing to aim at scaling up to thousands of processors on both distributed and shared memory systems. Development of parallel programs on these computers is always a challenging task. Today, writing parallel programs with message passing (e.g. MPI) is the most popular way of achieving scalability and high performance. However, writing message passing programs is difficult and error prone. Recent years new effort has been made in defining new parallel programming paradigms. The best examples are: HPF (based on data parallelism) and OpenMP (based on shared memory parallelism). Both provide simple and clear extensions to sequential programs, thus greatly simplify the tedious tasks encountered in writing message passing programs. HPF is independent of memory hierarchy, however, due to the immaturity of compiler technology its performance is still questionable. Although use of parallel compiler directives is not new, OpenMP offers a portable solution in the shared-memory domain. Another important development involves the tremendous progress in the internet and its associated technology. Although still in its infancy, Java promisses portability in a heterogeneous environment and offers possibility to "compile once and run anywhere." In light of testing these new technologies, we implemented new parallel versions of the NAS Parallel Benchmarks (NPBs) with HPF and OpenMP directives, and extended the work with Java and Java-threads. The purpose of this study is to examine the effectiveness of alternative programming paradigms. NPBs consist of five kernels and three simulated applications that mimic the computation and data movement of large scale computational fluid dynamics (CFD) applications. We started with the serial version included in NPB2.3. Optimization of memory and cache usage was applied to several benchmarks, noticeably BT and SP, resulting in better sequential performance. In order to overcome the lack of an HPF performance model and guide the development of the HPF codes, we employed an empirical performance model for several primitives found in the benchmarks. We encountered a few limitations of HPF, such as lack of supporting the "REDISTRIBUTION" directive and no easy way to handle irregular computation. The parallelization with OpenMP directives was done at the outer-most loop level to achieve the largest granularity. The performance of six HPF and OpenMP benchmarks is compared with their MPI counterparts for the Class-A problem size in the figure in next page. These results were obtained on an SGI Origin2000 (195MHz) with MIPSpro-f77 compiler 7.2.1 for OpenMP and MPI codes and PGI pghpf-2.4.3 compiler with MPI interface for HPF programs.

Jin, H.↗
NASA NTRS1974

A magnetic bubble domain flight recorder

A feasibility model of an all-electronic bubble memory system has been constructed. It uses a small 60k bit bubble recorder consisting of 6 chips of 10k bits each mounted in three separate packages operating as a FIFO at a 150 KHz bubble data rate. In addition to serving as a direct tape recorder replacement, the bubble recorder can be programmed for random access to each individual chip for ranom block access operation or for self-checking or by-passing any malfunctioning memory chip. Read and write operations can be performed asynchronously from very low frequency up to basic recording field frequency. A large 50M bit prototype is planned.

Chen, T. T.↗
NASA NTRS1977

The utilization of bubble memories in defense systems

The paper considers two examples of bubble memory application: the NASA solid state data recorder for spacecraft, and the POS/8 800,000 bit recorder. A matrix chart of applications delineated by capacity and chip organization, which is primarily reflected in access time, is then presented.

Mavity, W. C.↗
NASA NTRS2004

Validation of CFD/Heat Transfer Software for Turbine Blade Analysis

I am an intern in the Turbine Branch of the Turbomachinery and Propulsion Systems Division. The division is primarily concerned with experimental and computational methods of calculating heat transfer effects of turbine blades during operation in jet engines and land-based power systems. These include modeling flow in internal cooling passages and film cooling, as well as calculating heat flux and peak temperatures to ensure safe and efficient operation. The branch is research-oriented, emphasizing the development of tools that may be used by gas turbine designers in industry. The branch has been developing a computational fluid dynamics (CFD) and heat transfer code called GlennHT to achieve the computational end of this analysis. The code was originally written in FORTRAN 77 and run on Silicon Graphics machines. However the code has been rewritten and compiled in FORTRAN 90 to take advantage of more modem computer memory systems. In addition the branch has made a switch in system architectures from SGI's to Linux PC's. The newly modified code therefore needs to be tested and validated. This is the primary goal of my internship. To validate the GlennHT code, it must be run using benchmark fluid mechanics and heat transfer test cases, for which there are either analytical solutions or widely accepted experimental data. From the solutions generated by the code, comparisons can be made to the correct solutions to establish the accuracy of the code. To design and create these test cases, there are many steps and programs that must be used. Before a test case can be run, pre-processing steps must be accomplished. These include generating a grid to describe the geometry, using a software package called GridPro. Also various files required by the GlennHT code must be created including a boundary condition file, a file for multi-processor computing, and a file to describe problem and algorithm parameters. A good deal of this internship will be to become familiar with these programs and the structure of the GlennHT code. Additional information is included in the original extended abstract.

Kiefer, Walter D.↗
NASA NTRS1975

A design study of a photorefractive page composer

A laboratory demonstration and preliminary system analysis of a page composer designed to have the dual advantages of low optical loss and small size, were reported. The current page composer is optically addressed and functions by virtue of optically induced refractive index changes in the active material. Laboratory demonstrations of the device were successfully performed using 10 x 10 bit and 128 x 128 bit data arrays. It was established that the only significant obstacle to the construction of a brass-board model working at megabit data rates is the lack of sensitivity of the photorefractive materials which were considered during the course of this study. Possible materials for future consideration are the photoplastics. While they have more than the required sensitivity, their stability and suitability for double exposure holography was not investigated. If a sufficiently sensitive material is found, then the photorefractive page composer could be built to perform in a highly efficient fashion which would result in a overall reduction of the size of the memory system and an easing of the requirements upon the sensitivity of the holographic recording material.

Source record↗
NASA NTRS1970

Improved solid state electron-charge-storage device

Storage device is applicable in memory systems and in high-resolution arrays for light-responsive image sensing. The device offers high yield in multiple arrays and allows charge release with light striking only the edge of a metal electrode.

Kuper, A. B.↗