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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8

Satellite Test of Radiation Impact on Ramtron 512K FRAM

The Memory Test Experiment is a space test of a ferroelectric memory device on a low Earth orbit satellite. The test consists of writing and reading data with a ferroelectric based memory device. Any errors are detected and are stored on board the satellite. The data is send to the ground through telemetry once a day. Analysis of the data can determine the kind of error that was found and will lead to a better understanding of the effects of space radiation on memory systems. The test will be one of the first flight demonstrations of ferroelectric memory in a near polar orbit which allows testing in a varied radiation environment. The memory devices being tested is a Ramtron Inc. 512K memory device. This paper details the goals and purpose of this experiment as well as the development process. The process for analyzing the data to gain the maximum understanding of the performance of the ferroelectric memory device is detailed.

MacLeod, Todd C.↗

A Graph Dynamical neural network approach for decoding dynamical states in ferroelectrics.

Ferroelectric materials such as BaTiO 3 show tremendous potential for emerging advances in memory devices, particular neuromorphic type devices. High density of memory can be obtained by stabilising polar domain walls at the nanoscale, regions of discontinuity between the well-defined polarization order parameter, but little is known about what controls their structure and dynamics in real nanoscale materials. Indeed, chiral polar domain walls have been observed in heterogeneous ferroelectrics, such as oxygen-deficient BaTiO 3 , but very little is known about how such polar-domains walls interact with defects. Indeed, a critical understanding of how dynamics of domain-walls depend on point-defects is crucial to create engineered ferroelectric memory devices. For this work, we perform large-scale simulations of nansocale domain-wall dynamics in pristine and defective BaTiO 3 using reactive force-field developed by us earlier (Phys. Chem. Chem. Phys., 2019, 21, 18240–18249), and capture their dynamical dependence on point defects using a graph dynamical neural-network approach, which we adapted to interrogate solids with well-defined order-parameters, and implemented using Pytorch based libraries. Our machine learning (ML) approach goes beyond the traditional post-processing methods to capture both spatial and temporal heterogeneities of large-scale molecular dynamics simulations of complex defective ferroelectric oxide materials. We crucially find that isolated oxygen vacancies introduce very localized spatial regions (~1–2 unit-cell in length) that show slow dipole relaxation due to formation of defect-dipoles, and that these defect-dipoles in turn slow the intrinsic dynamics of domain walls. Further, the roughness of domain walls, also influenced by vacancies, introduce dynamic heterogeneity along the domain-wall. As such we find a novel mechanism by which quenched disorder due to defects introduce dynamic heterogeneity thereby influencing response to external fields (particularly time varying fields) in a ferroelectric. Our study also emphasizes the need for creating digital twins of dynamical quantities to achieve autonomous in operando control of nanoscale switching.

42 ENGINEERING↗

Comb

Comb is a communication performance benchmarking tool. It is used to determine performance tradeoffs in implementing communication patterns on high performance computing (HPC) platforms. At its core comb runs combinations of communication patterns with execution patterns, and memory spaces. The current set of capabilities Comb provides includes: o Configurable structured mesh halo exchange communication. o A variety of communication patterns based on grouping messages. o A variety of execution patterns including serial, openmp threading, cuda, cuda batched kernels, and cuda persistent kernels. o A variety of memory spaces including default system allocated memory, pinned host memory, cuda device memory, and cuda managed memory with different cuda memory advice.

Burmark, Jason↗

Rotary stepping device with memory metal actuator

A rotary stepping device includes a rotatable shaft which is driven by means of a coiled spring clutch which is alternately tightened to grip and rotate the shaft and released to return it to a resting position. An actuator formed of a memory metal is used to pull the spring clutch to tighten it and rotate the shaft. The actuator is activated by heating it above its critical temperature and is returned to an elongated configuration by means of the force of the spring cloth.

Jamieson, Robert S.↗

Ordering of guarded and unguarded stores for no-sync I/O

A parallel computing system processes at least one store instruction. A first processor core issues a store instruction. A first queue, associated with the first processor core, stores the store instruction. A second queue, associated with a first local cache memory device of the first processor core, stores the store instruction. The first processor core updates first data in the first local cache memory device according to the store instruction. The third queue, associated with at least one shared cache memory device, stores the store instruction. The first processor core invalidates second data, associated with the store instruction, in the at least one shared cache memory. The first processor core invalidates third data, associated with the store instruction, in other local cache memory devices of other processor cores. The first processor core flushing only the first queue.

97 MATHEMATICS AND COMPUTING↗

Electrical characterization of organic resistive memory with interfacial oxide layers formed by O{sub 2} plasma treatment

We studied organic resistive memory devices with interfacial oxide layers, the thickness of which depended on O{sub 2} plasma treatment time. The different interfacial oxide thicknesses sequentially changed the ON and OFF states of the final memory devices. We found that the memory devices that had undergone additional plasma treatment showed higher ON/OFF ratios than devices without the treatment, which was due to the relatively large OFF resistance values. However, a long oxidation process widened the threshold voltage distribution and degraded the switching reproducibility. This indicates that the oxidation process should be carefully optimized to provide practical high-performance organic memory.

36 MATERIALS SCIENCE↗

Mneme

A simple tool allowing recording the execution of a GPU (CUDA) kernel and replaying that kernel as an independent executable. The tool operates in 3 phases. During compile time the user needs to apply a provided LLVM pass to instrument the code. The pass detects all device global variables and device functions and stores this information with the respective LLVM-IR in the global device memory. The compilation generates a record-able executable. The second phase involves running the application executable with a desired input and using LD_PRELOAD to enable recording. When recording before invoking a device kernel the pre-loaded library stores device memory in persistent storage and associates the memory with the device kernel and an LLVM IR file. At the end of the recorded execution the pre-load library generates a database in the form of a JSON file containing information regarding the LLVM-IR files and the snapshots of device memory. During the third and last phase the user can replay the execution of an kernel as a separate independent executable. Besides executing it the user can modify the LLVM IR file and auto-tune parameters such as kernel launch-bounds or kernel runtime execution parameters (e.g. Kernel Block and Grid Dimensions). Is

Parasyris, Konstantinos↗

FPGA-based computing system for processing data in size, weight, and power constrained environments

Technologies that are well-suited for use in size, weight, and power (SWAP)-constrained environments are described herein. A host controller dispatches data processing instructions to hardware acceleration engines (HAEs) of one or more field programmable gate arrays (FPGAs) and further dispatches data transfer instructions to a memory controller, such that the HAEs perform processing operations on data stored in local memory devices of the HAEs in parallel with other data being transferred from external memory devices coupled to the FPGA(s) to the local memory devices.

Napier, Matthew↗

Resistive Switching Memory Performance of Two-Dimensional Polyimide Covalent Organic Framework Films

Two-dimensional polyimide covalent organic framework (2D PI-NT COF) films were constructed on indium tin oxide-coated glass substrates to fabricate two-terminal sandwiched resistive memory devices. The 2D PI-NT COF films condensated from the reaction between 4,4',4"-triaminotriphenylamine and naphthalene-1,4,5,8-tetracarboxylic dianhydride under solvothermal conditions demonstrated high crystallinity, good orientation preference, tunable thickness, and low surface roughness. The well-aligned electron-donor (triphenylamine unit) and -acceptor (naphthalene diimide unit) arrays rendered the 2D PI-NT COF films a promising candidate for electronic applications. The memory devices based on 2D PI-NT COF films exhibited a typical write-once-read-many-time resistive switching behavior under an operating voltage of +2.30 V on the positive scan and -2.64 V on the negative scan. A high ON/OFF current ratio (>10 6 for the positive scan and 10 4 -10 6 for the negative scan) and long-term retention time indicated the high fidelity, low error, and high stability of the resistive memory devices. The memory behavior was attributed to an electric field-induced intramolecular charge transfer in an ordered donor-acceptor system, which provided the effective charge-transfer channels for injected charge carriers. Furthermore, this work represents the first example that explores the resistive memory properties of 2D PI-COF films, shedding light on the potential application of 2D COFs as information storage media.

2D covalent organic framework film↗

Feature Classification for Control System Devices

Control systems are used to automate industrial processes, smart grids, and smart cities. Unfortunately, cyber attacks on control systems are on the rise. Additionally, control systems lack the plethora of tools available for commodity systems for forensic investigation. An important step towards the proper forensic investigation is to analyze device memory. To assist in identifying features of device memory, we present a machine learning-based technique that integrates ontology information for feature classification in a control system device’s memory.

ahmed mithu, M Rayhan↗

Partitionable memory interfaces

A memory device receives a plurality of read commands and/or write commands in parallel. The memory device transmits data corresponding to respective read commands on respective portions of a data bus and receives data corresponding to respective write commands on respective portions of the data bus. The memory device includes I/O logic to receive the plurality of read commands in parallel, to transmit the data corresponding to the respective read commands on respective portions of the data bus, and to receive the data corresponding to the respective write commands on respective portions of the data bus.

Roberts, David A.↗

HAM: Hotspot-Aware Manager for Improving Communications with 3D-Stacked Memory

merging High-Performance Computing (HPC) workloads, such as graph analytics, machine learning, and big data science, are data-intensive. Data-intensive workloads usually present fine-grained memory accesses with limited or no data locality, and thus incur frequent cache misses and low utilization of memory bandwidth. 3D-stacked memory devices such as Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM) can provide significantly higher bandwidth than conventional memory modules. However, the traditional interfaces and optimization methods for JEDEC DDR devices do not allow to fully exploit the potential performance of 3D-stacked memory with the massive amount of irregular memory accesses of data-intensive applications. In this paper, we propose a novel Hotspot-Aware Manager (HAM) infrastructure for 3D-stacked memory devices capable of optimizing memory access streams via request aggregation, hotspot detection, and in-memory prefetching. %and an associated hotspot-aware page policy. We present the HAM design and implementation, and simulate it on a system using RISC-V embedded cores with attached HMC devices. We extensively evaluate HAM with over 12 benchmarks and applications representing diverse irregular memory access patterns. The results show that, on average, HAM reduces redundant requests by 37.51\% and increases the prefetch buffer hit rate by 4.2 times, compared to a baseline streaming prefetcher. On the selected benchmark set, HAM provides performance gains of 21.81\% in average (up to 34.28\%) and power savings of 35.07\% over a standard 3D-stacked memory.

Wang, Xi↗

ZrO2 Layer Thickness Dependent Electrical and Dielectric Properties of BST/ZrO2/BST Multilayer Thin Films

Recently, high K materials play an important role in microelectronic devices such as capacitors, memory devices, and microwave devices. Now a days ferroelectric barium strontium titanate [Ba{sub x}Sr{sub 1-x}TiO{sub 3}, (BST)] thin film is being actively investigated for applications in dynamic random access memories (DRAM), field effect transistor (FET), and tunable devices because of its properties such as high dielectric constant, low leakage current, low dielectric loss, and high dielectric breakdown strength. Several approaches have been used to optimize the dielectric and electrical properties of BST thin films such as doping, graded compositions, and multilayer structures. We have found that inserting a ZrO{sub 2} layer in between two BST layers results in a significant reduction in dielectric constant, loss tangent, and leakage current in the multilayer thin films. Also it is shown that the properties of multilayer structure are found to depend strongly on the sublayer thicknesses. In this work the effect of ZrO{sub 2} layer thickness on the dielectric, ferroelectric as well as electrical properties of BST/ZrO{sub 2}/BST multilayer structure is studied. The multilayer Ba{sub 0.8}Sr{sub 0.2}TiO{sub 3}/ZrO{sub 2}/Ba{sub 0.8}Sr{sub 0.2}TiO{sub 3} film is deposited by a sol-gel process on the platinized Si substrate. The thickness of the middle ZrO{sub 2} layer is varied while keeping the top and bottom BST layer thickness as fixed. It is observed that the dielectric constant, dielectric loss tangent, and leakage current of the multilayer films reduce with the increase of ZrO{sub 2} layer thickness and hence suitable for memory device applications. The ferroelectric properties of the multilayer film also decrease with the ZrO{sub 2} layer thickness.

14 SOLAR ENERGY↗

Systems, methods, and products for graphically illustrating and controlling a droplet actuator

Systems for controlling a droplet microactuator are provided. According to one embodiment, a system is provided and includes a controller, a droplet microactuator electronically coupled to the controller, and a display device displaying a user interface electronically coupled to the controller, wherein the system is programmed and configured to permit a user to effect a droplet manipulation by interacting with the user interface. According to another embodiment, a system is provided and includes a processor, a display device electronically coupled to the processor, and software loaded and/or stored in a storage device electronically coupled to the controller, a memory device electronically coupled to the controller, and/or the controller and programmed to display an interactive map of a droplet microactuator. According to yet another embodiment, a system is provided and includes a controller, a droplet microactuator electronically coupled to the controller, a display device displaying a user interface electronically coupled to the controller, and software for executing a protocol loaded and/or stored in a storage device electronically coupled to the controller, a memory device electronically coupled to the controller, and/or the controller.

Paik, Philip Y.↗

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

97 MATHEMATICS AND COMPUTING↗

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

42 ENGINEERING↗

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

Asaad, Sameh W.↗

Near-field NanoThermoMechanical memory

In this letter, we introduce the concept of NanoThermoMechanical Memory. Unlike electronic memory, a NanoThermoMechanical memory device uses heat instead of electricity to record, store, and recover data. Memory function is achieved through the coupling of near-field thermal radiation and thermal expansion resulting in negative differential thermal resistance and thermal latching. Here, we demonstrate theoretically via numerical modeling the concept of near-field thermal radiation enabled negative differential thermal resistance that achieves bistable states. Design and implementation of a practical silicon based NanoThermoMechanical memory device are proposed along with a study of its dynamic response under write/read cycles. With more than 50% of the world's energy losses being in the form of heat along with the ever increasing need to develop computer technologies which can operate in harsh environments (e.g., very high temperatures), NanoThermoMechanical memory and logic devices may hold the answer.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗