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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Decoding the Gate Opening Mechanism of the Flexible Framework RPM3–Zn upon Hydrocarbon Inclusion

Although the existence of a gate-opening phenomenon in the flexible RPM3–Zn is well known, the actual mechanism remains a mystery. Here, we provide a full picture that unambiguously identifies and explains the gate-opening mechanism in RPM3–Zn upon exposure to various hydrocarbons—acetylene, ethylene, ethane, propane, and butane—by combining insights gained from calorimetry, adsorption isotherms, PXRD, in situ infrared spectroscopy, and ab initio simulations. We find that the key to gate opening in this framework is the stretching of a bond between an O and the Zn metal center (COO–Zn), acting as a “stabilizer”, which weakens the necessary support required for the structure to remain intact. Consequently, an increasing concentration of guest molecules exerts sufficient internal pressure to induce strong structural transformations in the unit cell shape and volume, thus triggering the gate opening. Here, our results are critical to understanding the gate opening in several other flexible frameworks and provide an opportunity to fine- tune hydrocarbon separation.

36 MATERIALS SCIENCE↗
DOE OSTI2021

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MISHEMTs) using plasma deposited BN as gate dielectric

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MISHEMTs) were fabricated on Si substrates with a 10 nm boron nitride (BN) layer as a gate dielectric deposited by electron cyclotron resonance microwave plasma chemical vapor deposition. The material characterization of the BN/GaN interface was investigated by X-ray photoelectric spectroscopy (XPS) and UV photoelectron spectroscopy. The BN bandgap from the B1s XPS energy loss is ~5 eV consistent with sp2 bonding. The MISHEMTs exhibit a low off-state current of 1 × 10 –8 mA/mm, a high on/off current ratio of 10 9 , a threshold voltage of –2.76 V, a maximum transconductance of 32 mS/mm at a gate voltage of –2.1 V and a drain voltage of 1 V, a subthreshold swing of 69.1 mV/dec, and an on-resistance of 12.75 Ω·mm. The interface state density (D it ) is estimated to be less than 8.49 × 10 11 cm –2 eV –1 . Gate leakage current mechanisms were investigated by temperature-dependent current–voltage measurements from 300 K to 500 K. The maximum breakdown electric field is no less than 8.4 MV/cm. Poole–Frenkel emission and Fowler–Nordheim tunneling are indicated as the dominant mechanisms of the gate leakage through the BN gate dielectric at low and high electric fields, respectively.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Computationally efficient zero-noise extrapolation for quantum-gate-error mitigation

Zero noise extrapolation (ZNE) is a widely used technique for gate error mitigation on near term quantum computers because it can be implemented in software and does not require knowledge of the quantum computer noise parameters. Traditional ZNE requires a significant resource overhead in terms of quantum operations. A recent proposal using a targeted (or random) instead of fixed identity insertion method (riim versus fiim) requires significantly fewer quantum gates for the same formal precision. We start by showing that riim can allow for ZNE to be deployed on deeper circuits than fiim but requires many more measurements to maintain the same statistical uncertainty. We develop two extensions to fiim and riim. The List Identity Insertion Method (liim) allows to mitigate the error from certain cnot gates, typically those with the largest error. Set Identity Insertion Method (siim) naturally interpolates between the measurement-efficient fiim and the gate-efficient riim allowing to trade off fewer cnot gates for more measurements. Finally, we investigate a way to boost the number of measurements, namely to run ZNE in parallel, utilizing as many quantum devices as are available. We explore the performance of riim in a parallel setting where there is a non-trivial spread in noise across sets of qubits within or across quantum computers.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Code conversion with the quantum Golay code for a universal transversal gate set

The [[7,1,3]] Steane code and [[23,1,7]] quantum Golay code have been identified as good candidates for fault-tolerant quantum computing via code concatenation. These two codes have transversal implementations of all Clifford gates but require some other scheme for fault-tolerant T gates. Using magic states, Clifford operations, and measurements is one common scheme, but magic-state distillation can have a large overhead. Code conversion is one avenue for implementing a universal gate set fault tolerantly without the use of magic-state distillation. Analogously to how the [[7,1,3]] Steane code can be fault tolerantly converted to and from the [[15,1,3]] Reed-Muller code which has a transversal T gate, the [[23,1,7]] Golay code can be converted to a [[95,1,7]] triorthogonal code with a transversal T gate. Further, a crucial ingredient of this procedure is the [[49,1,5]] triorthogonal code, which can itself be seen as being related to the self-dual [[17,1,5]] two-dimensional color code. Additionally, a method for code conversion based on a transversal CNOT between the codes, rather than stabilizer measurements, is described.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2024

Fast Z Z free entangling gates for superconducting qubits assisted by a driven resonator

Engineering high-fidelity two-qubit gates is an indispensable step toward practical quantum computing. For superconducting quantum platforms, one important setback is the stray interaction between qubits, which causes significant coherent errors. For transmon qubits, protocols for mitigating such errors usually involve fine-tuning the hardware parameters or introducing usually noisy flux-tunable couplers. In this work, we propose a simple scheme to cancel these stray interactions. The coupler used for such cancelation is a driven high-coherence resonator, where the amplitude and frequency of the drive serve as control knobs. Through the resonator-induced-phase interaction, the static Z Z coupling can be entirely neutralized. We numerically show that such a scheme can enable short and high-fidelity entangling gates, including cross-resonance controlled-not (cnot) gates within 40 ns and adiabatic controlled- Z gates within 140 ns. Our architecture is not only Z Z -free, but also contains no extra noisy components, such that it preserves the coherence times of fixed-frequency transmon qubits. With the state-of-the-art coherence times, the error of our cross-resonance cnot gate can be reduced to below 10 − 4 .

Huang, Ziwen↗
DOE OSTI2022

Primitive quantum gates for an S U ( 2 ) discrete subgroup: Binary tetrahedral

We construct a primitive gate set for the digital quantum simulation of the binary tetrahedral ($\mathbb{BT}$) group on two quantum architectures. This nonabelian discrete group serves as a crude approximation to $SU(2)$ lattice gauge theory while requiring five qubits or one quicosotetrit per gauge link. The necessary basic primitives are the inversion gate, the group multiplication gate, the trace gate, and the $\mathbb{BT}$ Fourier transform over $\mathbb{BT}$. We experimentally benchmark the inversion and trace gates on ibm nairobi, with estimated fidelities between $14-55\%$, depending on the input state.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2021

Asymmetric Blockade and Multiqubit Gates via Dipole-Dipole Interactions

Because of their strong and tunable interactions, Rydberg atoms can be used to realize fast two-qubit entangling gates. We propose a generalization of a generic two-qubit Rydberg-blockade gate to multiqubit Rydberg-blockade gates that involve both many control qubits and many target qubits simultaneously. This is achieved by using strong microwave fields to dress nearby Rydberg states, leading to asymmetric blockade in which control-target interactions are much stronger than control-control and target-target interactions. Further, the implementation of these multiqubit gates can drastically simplify both quantum algorithms and state preparation. To illustrate this, we show that a 25-atom Greenberger-Horne-Zeilinger state can be created using only three gates with an error of 5.8%.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2024

Tunable Inductive Coupler for High-Fidelity Gates Between Fluxonium Qubits

The fluxonium qubit is a promising candidate for quantum computation due to its long coherence times and large anharmonicity. We present a tunable coupler that realizes strong inductive coupling between two heavy-fluxonium qubits, each with approximately 50-MHz frequencies and approximately 5-GHz anharmonicities. The coupler enables the qubits to have a large tuning range of 𝑋⁢𝑋 coupling strengths (−35 to 75 MHz). The 𝑍⁢𝑍 coupling strength is <3 kHz across the entire coupler bias range and <100 Hz at the coupler off position. These qualities lead to fast high-fidelity single- and two-qubit gates. By driving at the difference frequency of the two qubits, we realize a $\sqrt{i\textrm{SWAP}}$ gate in 258 ns with fidelity 99.72%, and by driving at the sum frequency of the two qubits, we achieve a $\sqrt{𝑏⁢\textrm{SWAP}}$ gate in 102 ns with fidelity 99.91%. This latter gate is only five qubit Larmor periods in length. We run cross-entropy benchmarking for over 20 consecutive hours and measure stable gate fidelities, with $\sqrt{𝑏⁢\textrm{SWAP}}$ drift (2⁢𝜎) <0.02% and $\sqrt{i\textrm{SWAP}}$ drift <0.08%.

Zhang, Helin↗
DOE OSTI2020

“The structure of the Type III secretion system export gate with CdsO, an ATPase lever arm”

Type III protein secretion systems (T3SS) deliver effector proteins from the Gram-negative bacterial cytoplasm into a eukaryotic host cell through a syringe-like, multi-protein nanomachine. Cytosolic components of T3SS include a portion of the export apparatus, which traverses the inner membrane and features the opening of the secretion channel, and the sorting complex for substrate recognition and for providing the energetics required for protein secretion. Two components critical for efficient effector export are the export gate protein and the ATPase, which are proposed to be linked by the central stalk protein of the ATPase. We present the structure of the soluble export gate homo-nonamer, CdsV, in complex with the central stalk protein, CdsO, of its cognate ATPase, both derived from Chlamydia pneumoniae. This structure defines the interface between these essential T3S proteins and reveals that CdsO engages the periphery of the export gate that may allow the ATPase to catalyze an opening between export gate subunits to allow cargo to enter the export apparatus. We also demonstrate through structure-based mutagenesis of the homologous export gate in Pseudomonas aeruginosa that mutation of this interface disrupts effector secretion. These results provide novel insights into the molecular mechanisms governing active substrate recognition and translocation through a T3SS.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2021

Gate Set Tomography

Gate set tomography (GST) is a protocol for detailed, predictive characterization of logic operations (gates) on quantum computing processors. Early versions of GST emerged around 2012-13, and since then it has been refined, demonstrated, and used in a large number of experiments. This paper presents the foundations of GST in comprehensive detail. The most important feature of GST, compared to older state and process tomography protocols, is that it is calibration-free . GST does not rely on pre-calibrated state preparations and measurements. Instead, it characterizes all the operations in a gate set simultaneously and self-consistently, relative to each other. Long sequence GST can estimate gates with very high precision and efficiency, achieving Heisenberg scaling in regimes of practical interest. In this paper, we cover GST's intellectual history, the techniques and experiments used to achieve its intended purpose, data analysis, gauge freedom and fixing, error bars, and the interpretation of gauge-fixed estimates of gate sets. Our focus is fundamental mathematical aspects of GST, rather than implementation details, but we touch on some of the foundational algorithmic tricks used in the pyGSTi implementation.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1984

GaAs dual-gate FET for operation up to K-band

A high-frequency equivalent-circuit model of a GaAs dual-gate FET and analytical expressions for the input/output impedances, transconductance, unilateral gain, and stability factor are presented. It is found that the gain of a dual-gate FET is higher than of a single-gate FET at low frequency but decreases faster as frequency increases because of the capacitive shunting effect of the second gate. A dual-gate power FET suitable for variable-gain-amplifier applications up to K-band has been developed. At 10 GHz, a 1.2-mm-gatewidth device has achieved an output power of 1.1 W with 10.5-dB gain and 31-percent power-added efficiency. At 20 GHz, the same device delivered an output power of 340 mW with 5.3-dB gain. At K-band, a dynamic-gain control range of up to 45 dB was obtained with an insertion phase change of no more than + or 2 degrees for the first 10 dB of gain control.

Kim, B.↗
NASA NTRS1993

Characteristics of 0.8- and 0.2-microns gate length In(x)Ga(1-x) As/In(0.52)Al(0.48)As/InP (0.53 less than or equal to x less than or equal to 0.70) modulation-doped field-effect transistors at cryogenic temperatures

The performance characteristics of InP-based In(x)Ga(1-x)As/In(0.52)Al(0.48)As (0.53 is less than or equal to x is less than or equal to 0.70) pseudomorphic modulation-doped field-effect transistors (MODFET's) as a function of strain in the channel, gate, length, and temperature were investigated analytically and experimentally. The strain in the channel was varied by varying the In composition x. The temperature was varied in the range of 40-300 K and the devices have gate lengths L(sub g) of 0.8 and 0.2 microns. Analysis of the device was done using a one-dimensional self consistent solution of the Poisson and Schroedinger equations in the channel, a two-dimensional Poisson solver to obtain the channel electric field, and a Monte Carlo simulation to estimate the carrier transit times in the channel. An increase in the value of the cutoff frequency is predicted for an increase in In composition, a decrease in temperature, and a decrease in gate length. The improvements seen with decreasing temperature, decreasing gate length, and increased In composition were smaller than those predicted by analysis. The experimental results on pseudomorphic InGaAs/InAlAs MODFET's showed that there is a 15-30 percent improvement in cutoff frequency in both the 0.8- and 0.2-micron gate length devices when the temperature is lowered from 300 to 40 K.

Lai, Richard↗
NASA NTRS2003

Design of a Ferroelectric Programmable Logic Gate Array

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

MacLeod, Todd C.↗
NASA NTRS2006

Dual Input AND Gate Fabricated From a Single Channel Poly (3-Hexylthiophene) Thin Film Field Effect Transistor

A regio-regular poly (3-hexylthiophene) (RRP3HT) thin film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. This device demonstrates AND logic functionality. The device functionality was controlled by applying either 0 or -10 V to each of the gate electrodes. When -10 V was simultaneously applied to both gates, the device was conductive (ON), while any other combination of gate voltages rendered the device resistive (OFF). The p-type carrier charge mobility was about 5x10(exp -4) per square centimeter per V-sec. The low mobility is attributed to the sharp contours of the RRP3HT film due to substrate non-planarity. A significant advantage of this architecture is that AND logic devices with multiple inputs can be fabricated using a single RRP3HT channel with multiple gates.

Pinto, N. J.↗
NASA NTRS2009

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Phillips, Thomas A.↗
NASA NTRS2009

Assessment of SOI AND Gate, Type CHT-7408, for Operation in Extreme Temperature Environments

Electronic parts based on silicon-on-insulator (SOI) technology are finding widespread applications due to their ability to operate in harsh environments and the benefits they offer as compared to their silicon counterparts. Due to their construction, they are tailored for high temperature operation and show good tolerance to radiation events. In addition, their inherent design lessens the formation of parasitic junctions, thereby reducing leakage currents, decreasing power consumption, and enhancing speed. These devices are typically rated in temperature capability from -55 C to about +225 C, and their characteristics over this temperature range are documented in data sheets. Since electronics in some of NASA space exploration missions are required to operate under extreme temperature conditions, both cold and hot, their characteristic behavior within the full temperature spectrum must be determined to establish suitability for use in space applications. The effects of extreme temperature exposure on the performance of a new commercial-off-the-shelf (COTS) SOI AND gate device were evaluated in this work. The high temperature, quad 2-inputs AND gate device, which was recently introduced by CISSOID, is fabricated using a CMOS SOI process. Some of the specifications of the CHT-7408 chip are listed in a table. By supplying a constant DC voltage to one gate input and a 10 kHz square wave into the other associated gate input, the chip was evaluated in terms of output response, output rise (t(sub r)) and fall times (tf), and propagation delays (using a 50% level between input and output during low to high (tPLH) and high to low (tPHL) transitions). The supply current of the gate circuit was also obtained. These parameters were recorded at various test temperatures between -195 C and +250 C using a Sun Systems environmental chamber programmed at a temperature rate of change of 10 C/min. In addition, the effects of thermal cycling on this chip were determined by exposing it to a total of 12 cycles between -195 C and +250 C. Following the cycling activity, measurements were performed again at the test temperatures of -195 C, +21 C, and +250 C.

Patterson, Richard↗
NASA NTRS2011

Characterization of a Common-Gate Amplifier Using Ferroelectric Transistors

In this paper, the empirical data collected through experiments performed using a FeFET in the common-gate amplifier circuit is presented. The FeFET common-gate amplifier was characterized by varying all parameters in the circuit, such as load resistance, biasing of the transistor, and input voltages. Due to the polarization of the ferroelectric layer, the particular behavior of the FeFET common-gate amplifier presents interesting results. Furthermore, the differences between a FeFET common-gate amplifier and a MOSFET common-gate amplifier are examined.

Hunt, Mitchell↗
NASA NTRS2019

Gate Drive Technology Evaluation and Development to Maximize Switching Speed of SiC Discrete Devices and Power Modules in Hard Switching Applications

To understand the limitation of maximizing the switching speed of SiC low current discrete devices and high current power modules in hard switching applications, double pulse tests are conducted and the testing results are analyzed. For power modules, the switching speed is generally limited by the parasitics rather than the gate drive capability. For the discrete SiC device, the conventional voltage source gate drive (VSG) is not sufficient to maximize the switching speed even if the external gate resistance is minimized. The limitation of existing current source gate drives (CSG) are analyzed, and a CSG dedicated for SiC discrete devices is proposed, which can provide constant current during the switching transient regardless of the high Miller voltage and large internal gate resistance. Compared with the conventional VSG, the proposed CSG achieves 67% faster turnon time and 50% turn-off time, and 68% reduction in switching loss at full load condition.

Handong Gui↗