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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
NASA NTRS1986

Total-dose radiation effects data for semiconductor devices. 1985 Supplement. Volume 2, part B

Steady-state, total-dose radiation test data are provided in graphic format, for use by electronic designers and other personnel using semiconductor devices in a radiation environment. The data were generated by JPL for various NASA space programs. The document is in two volumes: Volume 1 provides data on diodes, bipolar transistors, field effect transistors, and miscellaneous semiconductor types, and Volume 2 (Parts A and B) provides data on integrated circuits. The data are presented in graphic, tabular, and/or narrative format, depending on the complexity of the integrated circuit. Most tests were done steady-state 2.5-MeV electron beam. However, some radiation exposures were made with a Cobalt-60 gamma ray source, the results of which should be regarded as only an approximate measure of the radiation damage that would be incurred by an equivalent electron dose. All data were generated in support of NASA space programs by the JPL Radiation Effects and Testing Group (514).

Martin, K. E.↗
NASA NTRS1984

Radiation-Hardness Data For Semiconductor Devices

Document presents data on and analysis of radiation hardness of various semiconductor devices. Data specifies total-dose radiation tolerance of devices. Volume 1 of report covers diodes, bipolar transistors, field effect transistors, silicon controlled rectifiers and optical devices. Volume 2 covers integrated circuits. Volume 3 provides detailed analysis of data in volumes 1 and 2.

Price, W. E.↗
NASA NTRS1996

Current sensing circuit

A current sensing circuit is described in which a pair of bipolar transistors are arranged with a pair of field effect transistors such that the field effect transistors absorb most of the supply voltage associated with a load.

Franke, Ralph J.↗
NASA NTRSDate not supplied

Double ChemFET for the In-Line Monitoring of Silver Dosing in Potable Water Systems

With NASA Advanced Exploration Systems (AES) Life Support Systems (LSS)baselining ionic silver (Ag+) as the biocide of choice, development in silver monitoring technologies becomes necessary to monitor and control Ag+ release. Ion-selective field effect transistors (ISFETs) and chemically-sensitive field effect transistors (ChemFETs) are capable of selective detection of Ag+ with reversible and low detection limit responses. However, one major hurdle to ChemFET technologies is the requirement of a reference electrode, which can leak its fill solution into the potable water system and is prone to drift requiring frequent calibration. To circumvent this issue, a double chemically-sensitive field effect transistor (dChemFET) is proposed. The dChemFET uses a second ChemFET to selectively monitor the counter ion and serves in place of the reference electrode. This work reports on the development of the dChemFET, starting with the development of the Ag+ andNO3- ion selective membranes (ISMs) to be used in the ChemFETs. The Ag+ ISM was tested in 50-105 ppb Ag+ and showed linear, sub-Nernstian response. The NO3- ISM was tested in50-500 ppb silver ion equivalents of nitrate ion (Ag+ equiv. of NO3-) and shows linear, sub-Nernstian response as well . However, the Ag+ and NO3- ISMs face significant challenges in terms of drift that obstruct its application for long-term monitoring, but it can serve as a starting point for demonstrating the dChemFET proof of concept.

John Abdou↗
NASA NTRSDate not supplied

Double ChemFET for the In-Line Monitoring of Silver Dosing in Potable Water Systems

With NASA Advanced Exploration Systems (AES) Life Support Systems (LSS) baselining ionic silver (Ag+) as the biocide of choice, development in silver monitoring technologies becomes necessary to monitor and control Ag+ release. Ion-selctive field effect transistors (ISFETs) and chemically-sensitive field effect transistors (ChemFETs) are capable of selective detection of Ag+ with reversible and low detection limit responses. However, one major hurdle to ChemFET technologies is the requirement of a reference electrode, which can leak its fill solution into the potable water system and is prone to drift requiring frequent calibration. To circumvent this issue, we are developing a double chemically-sensitive field effect transistor (dChemFET). The dChemFET uses a second ChemFET to selectively monitor the counter ion and serves in place of the reference electrode. We report our work in developing the dChemFET, starting with the development of the Ag+ and NO3- ion selective memberanes (ISMs) to be used in the ChemFETs. The Ag+ ISM has a detection range of 50-105 ppb . The counter ion ISM, NO3- ISM, has shown a detection range of 400-105 ppb. NO3- ISMs are limited in detecting at lower ppb levels required for the dChemFET application on the potable water system. In response to this issue, we also report our studies in using the Ag+ ISM to measure deionized (DI) water as a reference measurement to be implemented in-line before the Ag+ is dosed.

Lance Dean Delzeit↗
NASA NTRS2008

Efficient G(sup 4)FET-Based Logic Circuits

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Vatan, Farrokh↗
NASA NTRS1972

Aluminum nitride insulating films for MOSFET devices

Application of aluminum nitrides as electrical insulator for electric capacitors is discussed. Electrical properties of aluminum nitrides are analyzed and specific use with field effect transistors is defined. Operational limits of field effect transistors are developed.

Lewicki, G. W.↗
NASA NTRS2013

N Channel JFET Based Digital Logic Gate Structure

An apparatus is provided that includes a first field effect transistor with a source tied to zero volts and a drain tied to voltage drain drain (Vdd) through a first resistor. The apparatus also includes a first node configured to tie a second resistor to a third resistor and connect to an input of a gate of the first field effect transistor in order for the first field effect transistor to receive a signal. The apparatus also includes a second field effect transistor configured as a unity gain buffer having a drain tied to Vdd and an uncommitted source.

Krasowski, Michael J↗
NASA NTRS1993

Cryogenic measurements of aerojet GaAs n-JFETs

The spectral noise characteristics of Aerojet gallium arsenide (GaAs) junction field effect transistors (JFET's) have been investigated down to liquid-helium temperatures. Noise characterization was performed with the field effect transistor (FET) in the floating-gate mode, in the grounded-gate mode to determine the lowest noise readings possible, and with an extrinsic silicon photodetector at various detector bias voltages to determine optimum operating conditions. The measurements indicate that the Aerojet GaAs JFET is a quiet and stable device at liquid helium temperatures. Hence, it can be considered a readout line driver or infrared detector preamplifier as well as a host of other cryogenic applications. Its noise performance is superior to silicon (Si) metal oxide semiconductor field effect transistor (MOSFET's) operating at liquid helium temperatures, and is equal to the best Si n channel junction field effect transistor (n-JFET's) operating at 300 K.

Goebel, John H.↗
NASA NTRS1974

A stable, linear frequency-modulated oscillator, part 1

The development of a push-pull frequency-modulated oscillator employing field-effect transistors is described. The advantages of field-effect transistors for use in a frequency-stable oscillator are presented. Linearization of the frequency deviation was accomplished by utilizing the square-law characteristic of an FET used as a modulating amplifier. The push-pull oscillator model produced a linear frequency deviation of more than 10 MHz at a center frequency of approximately 100 MHz. Output power is within 0.6 db of a nominal +8.5 dBm over the desired frequency range, and the modulation bandwidth is dc to 10 MHz. Frequency variation with temperature after compensation with a negative-temperature-coefficient capacitor is within + or - 0.05% from 0 to 60 C.

Honnell, M. A.↗
NASA NTRS1989

A digitally controlled system for effecting and presenting a selected electrical resistance

A digitally controlled resistance generator is described, in which resistors having values selected according to an expression 2(sup N-1)(R), where N is equal to the number of terms in the expression, and R is equal to the lowest value of resistance, are electrically inserted into a resistive circuit in accordance with a parallel binary signal provided by an analog-to-digital converter or a programmable computer. This binary signal is coupled via optical isolators which, when activated by a logical 1, provides a negative potential to some or all of the gate inputs of the normally on field effect transistors which, when on, shorts out the associated resistor. This applied negative potential turns the field effect transistors off and electrically inserts the resistor coupled between the source terminal and the drain terminal of that field effect transistor into the resistive circuit between the terminals.

Fletcher, James C.↗
NASA NTRS1979

Solid-state X-band Combiner Study

The feasibility of developing solid-state amplifiers at 4 and 10 GHz for application in spacecraft altimeters was studied. Bipolar-transistor, field-effect-transistor, and Impatt-diode amplifier designs based on 1980 solid-state technology are investigated. Several output power levels of the pulsed, low-duty-factor amplifiers are considered at each frequency. Proposed transistor and diode amplifier designs are illustrated in block diagrams. Projections of size, weight, and primary power requirements are given for each design.

Pitzalis, O., Jr.↗
NASA NTRS1984

Energy-Saving Inverter

Commutation by field-effect transistor allows more efficient operation. High voltage field-effect transistor (FET) controls silicon controlled rectifiers (SCR's). Circuit requires only one capacitor and one inductor in commutation circuit: simpler, more efficient, and more economical than conventional inverters. Adaptable to dc-to-dc converters.

Rippel, W. E.↗
NASA NTRS2007

G4-FETs as Universal and Programmable Logic Gates

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Johnson, Travis↗
NASA NTRS2009

G(sup 4)FET Implementations of Some Logic Circuits

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Mojarradi, Mohammad↗