Drift compensation circuit for analog to digital converter Patent
Voltage drift compensation circuit for analog-to-digital converter
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Voltage drift compensation circuit for analog-to-digital converter
An i(sub DD) temporal analysis technique which is used to detect defects (faults) and fabrication variations in both digital and analog IC's by pulsing the power supply rails and analyzing the temporal data obtained from the resulting transient rail currents is presented. A simple bias voltage is required for all the inputs, to excite the defects. Data from hardware tests supporting this technique are presented.
Spacecraft require all manner of both digital and analog circuits. Onboard digital systems are constructed almost exclusively from field-programmable gate array (FPGA) circuits providing numerous advantages over discrete design including high integration density, high reliability, fast turn-around design cycle time, lower mass, volume, and power consumption, and lower parts acquisition and flight qualification costs. Analog and mixed-signal circuits perform tasks ranging from housekeeping to signal conditioning and processing. These circuits are painstakingly designed and built using discrete components due to a lack of options for field-programmability. FPAA (Field-Programmable Analog Array) and FPMA (Field-Programmable Mixed-signal Array) parts exist but not in radiation-tolerant technology and not necessarily in an architecture optimal for the design of analog circuits for spaceflight applications. This paper outlines an architecture proposed for an FPAA fabricated in an existing commercial digital CMOS process used to make radiation-tolerant antifuse-based FPGA devices. The primary concerns are the impact of the technology and the overall array architecture on the flexibility of programming, the bandwidth available for high-speed analog circuits, and the accuracy of the components for high-performance applications.
Coarsely digitized maximum levels recorded in blown fuses. Circuit feeds power to accelerometer and makes nonvolatile record of maximum level to which output of accelerometer rises during measurement interval. In comparison with inertia-type single-preset-trip-point mechanical maximum-acceleration-recording devices, circuit weighs less, occupies less space, and records accelerations within narrower bands of uncertainty. In comparison with prior electronic data-acquisition systems designed for same purpose, circuit simpler, less bulky, consumes less power, costs and analysis of data recorded in magnetic or electronic memory devices. Circuit used, for example, to record accelerations to which commodities subjected during transportation on trucks.
Circuit includes array of low-cost multivibrators. Inexpensive circuit converts frequency-modulated (FM) signal into digital signal. Consists of zero-crossing detector and series of monostable multivibrators and D-type flip-flops. Used to control filter.
Circuits that include compensation circuitry time a capacitance relative to a reference voltage so that a digital presentation occurs that is representative of the positional condition of the mechanical shaft being monitored. This circuitry may be employed in multiples to furnish binary encoding of a number of rotating devices simultaneously.
Digital all-magnetic circuit technique used in pulse code modulation telemetry systems
Selective gold diffusion on monolithic silicon chips for switching and nonswitching amplifier devices and circuits and linear and digital logic circuits
Interfacing ultrasonic delay lines in digital systems using integrated circuit logic
Zero- and third-order digital-to-analog conversion techniques are described, and the theoretical error performances are compared. The design equations and procedures for constructing a third-order digital-to-analog converter by using analog design elements are presented. Both a zero- and a third-order digital-to-analog converter were built, and the performances are compared with various signal inputs.
Circuit extracts clock signal from random non-return-to-zero data stream, locking onto clock within one bit period at 1-gigabitper-second data rate. Circuit used for synchronization in opticalfiber communications. Derives speed from very short response time of gallium arsenide metal/semiconductor field-effect transistors (MESFET's).
Complementary symmetry flip-flop and similar transistor micropower digital logic circuit design
Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.
A processing circuit is provided for correcting for input parameter variations, such as data and clock signal symmetry, phase offset and jitter, noise and signal amplitude, in incoming data signals. An asymmetry corrector circuit performs the correcting function and furnishes the corrected data signals to a convolutional encoder circuit. The corrector circuit further forms a regenerated clock signal from clock pulses in the incoming data signals and another clock signal at a multiple of the incoming clock signal. These clock signals are furnished to the encoder circuit so that encoded data may be furnished to a modulator at a high data rate for transmission.
Pulse-sequencing circuit uses only shift register and Exclusive-OR gates. Circuit also serves as date-transition edge detector (for rising or falling edges). It is used in sample-and-hold, analog-to-digital conversion sequence control, multiphase clock logic, precise delay control computer control logic, edge detectors, other timing applications, and provides simple means to generate timing and control signals for data transfer, addressing, or mode control in microprocessors and minicomputers.
Spacecraft electronic are affected by the space radiation environment. Among the different types of radiation effects that can affect spacecraft electronics is the single event transient (SET). The space environment is responsible for many of the single event transients which can upset the performance of the spacecraft avionics hardware. In this chapter we first explore the origins of single event transients, then explore the modeling of a single event transient in digital and analog circuit. The chapter also addresses the concept of crosstalk that could develop among digital circuits in the present of a SET event. The chapter also provides a discussion of SET hardening. We then provide a discussion concerning propagation of a single event transient event at the local, subsystem, and system level in a spacecraft using two different models, one of the models developed by the author, known as the state transition model. The final goal of the chapter is to provide a qualitatively methodology for assessing single event transients and its effects so that spacecraft avionics engineers can develop either hardware or software countermeasures in their designs. SET is not a form of electromagnetic interference (EMI) in its origin, but semantically SET is very similar to EMI because they are both caused a current source not previously accounted for. SET has the same effects as EMI and it can cause interference problems in electronic circuits via multiple coupling mechanisms similar to EMI, and therefore makes such circuits incompatible.
Performance analysis, used to evaluated fitness of several circuits to digital automatic gain control (AGC), indicates that digital integrator employing coherent amplitude detector (CAD) is best device suited for application. Circuit reduces gain error to half that of conventional analog AGC while making it possible to automatically modify response of receiver to match incoming signal conditions.
Development of electric circuit for production of different pulse width signals