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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
NASA NTRS2005

Software-Reconfigurable Processors for Spacecraft

A report presents an overview of an architecture for a software-reconfigurable network data processor for a spacecraft engaged in scientific exploration. When executed on suitable electronic hardware, the software performs the functions of a physical layer (in effect, acts as a software radio in that it performs modulation, demodulation, pulse-shaping, error correction, coding, and decoding), a data-link layer, a network layer, a transport layer, and application-layer processing of scientific data. The software-reconfigurable network processor is undergoing development to enable rapid prototyping and rapid implementation of communication, navigation, and scientific signal-processing functions; to provide a long-lived communication infrastructure; and to provide greatly improved scientific-instrumentation and scientific-data-processing functions by enabling science-driven in-flight reconfiguration of computing resources devoted to these functions. This development is an extension of terrestrial radio and network developments (e.g., in the cellular-telephone industry) implemented in software running on such hardware as field-programmable gate arrays, digital signal processors, traditional digital circuits, and mixed-signal application-specific integrated circuits (ASICs).

Farrington, Allen↗
NASA NTRS2012

Correlation Between Analog Noise Measurements and the Expected Bit Error Rate of a Digital Signal Propagating Through Passive Components

A method of determining the bit error rate (BER) of a digital circuit from the measurement of the analog S-parameters of the circuit has been developed. The method is based on the measurement of the noise and the standard deviation of the noise in the S-parameters. Once the standard deviation and the mean of the S-parameters are known, the BER of the circuit can be calculated using the normal Gaussian function.

Warner, Joseph D.↗
NASA NTRS1973

Airborne Laser Polar Nephelometer

A polar nephelometer has been developed at NCAR to measure the angular variation of the intensity of light scattered by air molecules and particles. The system has been designed for airborne measurements using outside air ducted through a 5-cm diameter airflow tube; the sample volume is that which is common to the intersection of a collimated source beam and the detector field of view within the airflow tube. The source is a linearly polarized helium-neon laser beam. The optical system defines a collimated field-of-view (0.5deg half-angle) through a series of diaphragms located behind a I72-mm focal length objective lens. A photomultiplier tube is located immediately behind an aperture in the focal plane of the objective lens. The laser beam is mechanically chopped (on-off) at a rate of 5 Hz; a two-channel pulse counter, synchronized to the laser output, measures the photomultiplier pulse rate with the light beam both on and off. The difference in these measured pulse rates is directly proportional to the intensity of the scattered light from the volume common to the intersection of the laser beam and the detector field-of-view. Measurements can be made at scattering angles from 15deg to 165deg with reference to the direction of propagation of the light beam. Intermediate angles are obtained by selecting the angular increments desired between these extreme angles (any multiple of 0.1deg can be selected for the angular increment; 5deg is used in normal operation). Pulses provided by digital circuits control a stepping motor which sequentially rotates the detector by pre-selected angular increments. The synchronous photon-counting system automatically begins measurement of the scattered-light intensity immediately after the rotation to a new angle has been completed. The instrument has been flown on the NASA Convair 990 airborne laboratory to obtain data on the complex index of refraction of atmospheric aerosols. A particle impaction device is operated simultaneously to collect particles from the same airflow tube used to make the scattered-light measurements. A size distribution function is obtained by analysis of the particles collected by the impaction device. Calculated values of the angular variation of the scattered-light intensity are obtained by applying Mie scattering theory to the observed size distribution function and assuming different values of the complex index of refraction of the particles. The calculated values are then compared with data on the actual variation of the scattered-light intensity obtained with the polar nephelometer. The most probable value of the complex refractive index is that which provides the best fit between the experimental light scattering data and the parameters calculated from the observed size distribution function.

Grams, Gerald W.↗
NASA NTRS2003

Increasing software testability with standard access and control interfaces

Testing is the most common method of determining whether a software system satisfies its requirements. Traditionally, testing starts with the detailed examination of individual functions or methods, progresses through the integration of functions or methods into subsystems, and ends with testing the functionality and behavior of the completely integrated system. At each stage of testing, the amount of functionality and behavior of the artifact being tested is increasingly limited. One reason for this is that it becomes impossible to test all paths through the system within a reasonable amount of time. However, another reason for this progressive decrease of test coverage has to do with increasingly limited control of and visibility into the state of the artifact being tested. During unit test, it is rather simple to control the inputs of individual functions or methods or view their internal state - modem development environments provide adequate facilities for doing so. However, these facilities do not scale up to the testing of partially or completely integrated systems. Control of and visibility into the system's state is then limited to the input and output facilities provided by the software itself as well as the hardware on which the software is hosted during the test. These facilities are usually insufficient to precisely control the state of individual components or sets of components of the system; they are also inadequate to the task of displaying on demand the state of specific components. We describe an approach to improving the testability of complex software systems with software constructs modeled after the hardware JTAG bus, used to provide visibility and controllability in testing digital circuits.

Tamir, Yuval↗
NASA NTRS1984

Upset susceptibility study employing circuit analysis and digital simulation

This paper describes an approach to predicting the susceptibility of digital systems to signal disturbances. Electrical disturbances on a digital system's input and output lines can be induced by activities and conditions including static electricity, lightning discharge, Electromagnetic Interference (EMI) and Electromagnetic Pulsation (EMP). The electrical signal disturbances employed for the susceptibility study were limited to nondestructive levels, i.e., the system does not sustain partial or total physical damage and reset and/or reload will bring the system to an operational status. The front-end transition from the electrical disturbances to the equivalent digital signals was accomplished by computer-aided circuit analysis. The Super-Sceptre (system for circuit evaluation of transient radiation effects) Program was used. Gate models were developed according to manufacturers' performance specifications and parameters resulting from construction processes characteristic of the technology. Digital simulation at the gate and functional level was employed to determine the impact of the abnormal signals on system performance and to study the propagation characteristics of these signals through the system architecture. Example results are included for an Intel 8080 processor configuration.

Carreno, V. A.↗
NASA NTRS1984

Upset susceptibility study employing circuit analysis and digital simulation

An approach to predict the susceptibility of digital systems to signal disturbances is described. Electrical disturbances on a digital system's input and output lines can be induced by activities and conditions including static electricity, lightning discharge, electromagnetic interference (EMI), and electromagnetic pulsation (EMP). The electrical signal disturbances employed for the susceptibility study were limited to nondestructive levels, i.e., the system does not sustain partial or total physical damage and reset and/or reload brings the system to an operational status. The front-end transition from the electrical disturbances to the equivalent digital signals was accomplished by computer-aided circuit analysis. The super-sceptre (system for circuit evaluation of transient radiation effects) programs was used. Gate models were developed according to manufacturers' performance specifications and parameters resulting from construction processes characteristic of the technology. Digital simulation at the gate and functional level was employed to determine the impact of the abnormal signals on system performance and to study the propagation characteristics of these signals through the system architecture. Example results are included for an Intel 8080 processor configuration.

Carreno, V. A.↗
NASA NTRS1991

Mixed application MMIC technologies - Progress in combining RF, digital and photonic circuits

Approaches for future 'mixed application' monolithic integrated circuits (ICs) employing optical receive/transmit, RF amplification and modulation and digital control functions are discussed. We focus on compatibility of the photonic component fabrication with conventional RF and digital IC technologies. Recent progress at Honeywell in integrating several parts of the desired RF/digital/photonic circuit integration suite required for construction of a future millimeter-wave optically-controlled phased-array element are illustrated.

Swirhun, S.↗
NASA NTRS1981

An evaluation of the Intel 2920 digital signal processing integrated circuit

The circuit consists of a digital to analog converter, accumulator, read write memory and UV erasable read only memory. The circuit can convert an analog signal to a digital representation, perform mathematical operations on the digital signal and subsequently convert the digital signal to an analog output. Development software tailored for programming the 2920 is presented.

Heller, J.↗
NASA NTRS1993

Fault detection in digital and analog circuits using an i(DD) temporal analysis technique

An i(sub DD) temporal analysis technique which is used to detect defects (faults) and fabrication variations in both digital and analog IC's by pulsing the power supply rails and analyzing the temporal data obtained from the resulting transient rail currents is presented. A simple bias voltage is required for all the inputs, to excite the defects. Data from hardware tests supporting this technique are presented.

Beasley, J.↗
NASA NTRS1999

Analog Module Architecture for Space-Qualified Field-Programmable Mixed-Signal Arrays

Spacecraft require all manner of both digital and analog circuits. Onboard digital systems are constructed almost exclusively from field-programmable gate array (FPGA) circuits providing numerous advantages over discrete design including high integration density, high reliability, fast turn-around design cycle time, lower mass, volume, and power consumption, and lower parts acquisition and flight qualification costs. Analog and mixed-signal circuits perform tasks ranging from housekeeping to signal conditioning and processing. These circuits are painstakingly designed and built using discrete components due to a lack of options for field-programmability. FPAA (Field-Programmable Analog Array) and FPMA (Field-Programmable Mixed-signal Array) parts exist but not in radiation-tolerant technology and not necessarily in an architecture optimal for the design of analog circuits for spaceflight applications. This paper outlines an architecture proposed for an FPAA fabricated in an existing commercial digital CMOS process used to make radiation-tolerant antifuse-based FPGA devices. The primary concerns are the impact of the technology and the overall array architecture on the flexibility of programming, the bandwidth available for high-speed analog circuits, and the accuracy of the components for high-performance applications.

Edwards, R. Timothy↗
NASA NTRS1995

Maximum Acceleration Recording Circuit

Coarsely digitized maximum levels recorded in blown fuses. Circuit feeds power to accelerometer and makes nonvolatile record of maximum level to which output of accelerometer rises during measurement interval. In comparison with inertia-type single-preset-trip-point mechanical maximum-acceleration-recording devices, circuit weighs less, occupies less space, and records accelerations within narrower bands of uncertainty. In comparison with prior electronic data-acquisition systems designed for same purpose, circuit simpler, less bulky, consumes less power, costs and analysis of data recorded in magnetic or electronic memory devices. Circuit used, for example, to record accelerations to which commodities subjected during transportation on trucks.

Bozeman, Richard J., Jr.↗
DOE OSTI2026

Advancements in NbTiN based circuits for Superconducting Digital Logic

Superconducting (SC) electronics have emerged as a promising platform for high-speed, energy-efficient computing and quantum information processing. This work, centered on NbTiN, presents recent advances in material science and fabrication methods leading to significant improvements in performance, scalability and vertical integration. We specifically report on fabrication and characterization of key components, including Josephson junctions (JJs), flux trapping structures and SC interconnects. Together, these efforts represent critical steps towards realizing practical, complex, dense and large-scale SC integrated circuits.

Pokhrel, A. [Imec,Heverlee,Belgium]↗
NASA NTRS1987

FM-to-Digital Converter

Circuit includes array of low-cost multivibrators. Inexpensive circuit converts frequency-modulated (FM) signal into digital signal. Consists of zero-crossing detector and series of monostable multivibrators and D-type flip-flops. Used to control filter.

Moniuszko, Michael↗
NASA NTRS1966

Shaft encoder presents digital output

Circuits that include compensation circuitry time a capacitance relative to a reference voltage so that a digital presentation occurs that is representative of the positional condition of the mechanical shaft being monitored. This circuitry may be employed in multiples to furnish binary encoding of a number of rotating devices simultaneously.

Hillis, D. A.↗
DOE OSTI2022

A Low-Power 1 Gb/s Line Driver with Configurable Pre-Emphasis for Lossy Transmission Lines

A line driver with configurable pre-emphasis is implemented in a 65 nm CMOS process. The driver utilizes a three-tap feed-forward equalization (FFE) architecture. The relative delays between the taps are selectable in increments of 1/16th of the unit interval (UI) via an 8-stage delay-locked loop (DLL) and digital interpolator. It is also possible to control the output amplitude and source impedance for each tap via a programmable array of eight source-series terminated (SST) drivers. The entire design consumes 9 mW from a 1.2 V supply at 1 Gb/s.

47 OTHER INSTRUMENTATION↗
DOE OSTI2022

The CMS Barrel Calorimeter Processor demonstrator (BCPv1) board evaluation

For the CERN LHC phase 2, the barrel region of the CMS electromagnetic (ECAL EB) and hadronic calorimeters (HCAL HB) require new back-end electronics for their readout. To this purpose, a first version of the ATCA-based blade, the Barrel Calorimeter Processor (BCPv1), has been developed. The performance of the optical links as well as clock distribution are also presented here. Here, the BCPv1 has been tested together with front-end and trigger boards, as well as with the new DAQ and TCDS Hub (DTH) [1], to demonstrate that the BCPv1 meets the required specifications.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

An integer- N frequency synthesizer for flexible on-chip clock generation

A low-power integer-N frequency synthesizer for flexible on-chip clock generation has been designed in a 65 nm CMOS process. The circuit can be programmed to generate two independent low-jitter clocks between 30 MHz and 3 GHz that are locked to a 10–50 MHz reference input. The design uses a phase-locked loop (PLL) with a dual-tuned LC voltage-controlled oscillator (VCO), programmable feedback divider, and dual output dividers. The total power consumption from 1.2 V and 0.8 V supplies is 4.0 mW. In conclusion, experimental results confirm the functionality of the proposed synthesizer over a wide range of output frequencies.

47 OTHER INSTRUMENTATION↗